Lines Matching +full:rx +full:- +full:max +full:- +full:burst
1 /* SPDX-License-Identifier: GPL-2.0 */
17 #define B44_BIST_STAT 0x000CUL /* Built-In Self-Test Status */
43 #define ISTAT_RX 0x00010000 /* RX Interrupt */
56 #define B44_TXBURST 0x00A0UL /* TX Max Burst Length */
57 #define B44_RXBURST 0x00A4UL /* RX Max Burst Length */
94 #define B44_DMARX_CTRL 0x0210UL /* DMA RX Control */
98 #define B44_DMARX_ADDR 0x0214UL /* DMA RX Descriptor Ring Address */
99 #define B44_DMARX_PTR 0x0218UL /* DMA RX Last Posted Descriptor */
100 #define B44_DMARX_STAT 0x021CUL /* DMA RX Current Active Desc. + Status */
126 #define B44_RXCONFIG 0x0400UL /* EMAC RX Config */
136 #define B44_RXMAXLEN 0x0404UL /* EMAC RX Max Packet Length */
137 #define B44_TXMAXLEN 0x0408UL /* EMAC TX Max Packet Length */
197 #define B44_TX_1024_MAX 0x052CUL /* MIB TX 1024 to max byte Packets */
210 #define B44_RX_GOOD_O 0x0580UL /* MIB RX Good Octets */
211 #define B44_RX_GOOD_P 0x0584UL /* MIB RX Good Packets */
212 #define B44_RX_O 0x0588UL /* MIB RX Octets */
213 #define B44_RX_P 0x058CUL /* MIB RX Packets */
214 #define B44_RX_BCAST 0x0590UL /* MIB RX Broadcast Packets */
215 #define B44_RX_MCAST 0x0594UL /* MIB RX Multicast Packets */
216 #define B44_RX_64 0x0598UL /* MIB RX <= 64 byte Packets */
217 #define B44_RX_65_127 0x059CUL /* MIB RX 65 to 127 byte Packets */
218 #define B44_RX_128_255 0x05A0UL /* MIB RX 128 to 255 byte Packets */
219 #define B44_RX_256_511 0x05A4UL /* MIB RX 256 to 511 byte Packets */
220 #define B44_RX_512_1023 0x05A8UL /* MIB RX 512 to 1023 byte Packets */
221 #define B44_RX_1024_MAX 0x05ACUL /* MIB RX 1024 to max byte Packets */
222 #define B44_RX_JABBER 0x05B0UL /* MIB RX Jabber Packets */
223 #define B44_RX_OSIZE 0x05B4UL /* MIB RX Oversize Packets */
224 #define B44_RX_FRAG 0x05B8UL /* MIB RX Fragment Packets */
225 #define B44_RX_MISS 0x05BCUL /* MIB RX Missed Packets */
226 #define B44_RX_CRCA 0x05C0UL /* MIB RX CRC Align Errors */
227 #define B44_RX_USIZE 0x05C4UL /* MIB RX Undersize Packets */
228 #define B44_RX_CRC 0x05C8UL /* MIB RX CRC Errors */
229 #define B44_RX_ALIGN 0x05CCUL /* MIB RX Align Errors */
230 #define B44_RX_SYM 0x05D0UL /* MIB RX Symbol Errors */
231 #define B44_RX_PAUSE 0x05D4UL /* MIB RX Pause Packets */
232 #define B44_RX_NPAUSE 0x05D8UL /* MIB RX Non-Pause Packets */
274 #define RX_FLAG_LARGE 0x00000010 /* Frame is > RX MAX Length */
287 /* no local phy regs, e.g: Broadcom switches pseudo-PHY */