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/linux/drivers/usb/serial/
H A Dio_16654.h1 /* SPDX-License-Identifier: GPL-2.0+ */
21 // Numbers 0-7 are passed to the Edgeport directly. Numbers 8 and
22 // above are used internally to indicate that we must enable access
27 // the EdgePort firmware -- that includes THR, RHR, IER, FCR.
32 #define IER 1 // ! Interrupt Enable Register
44 #define XON1 12 // Bank2[ 4 ] Xon-1
45 #define XON2 13 // Bank2[ 5 ] Xon-2
46 #define XOFF1 14 // Bank2[ 6 ] Xoff-1
47 #define XOFF2 15 // Bank2[ 7 ] Xoff-2
57 #define IER_RX 0x01 // Enable receive interrupt
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/linux/sound/arm/
H A Daaci.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/sound/arm/aaci.c - ARM PrimeCell AACI PL041 driver
19 #define AACI_RXCR 0x000 /* 29 bits Control Rx FIFO */
23 #define AACI_IE 0x010 /* 7 bits Int Enable */
36 #define AACI_SLIEN 0x070 /* slot interrupt enable */
49 * TX/RX fifo control register (CR). P48
51 #define CR_FEN (1 << 16) /* fifo enable */
69 #define CR_EN (1 << 0) /* transmit enable */
74 #define SR_RXTOFE (1 << 11) /* rx timeout fifo empty */
75 #define SR_TXTO (1 << 10) /* rx timeout fifo nonempty */
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/linux/drivers/net/wan/
H A Dhd64570.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 /* SCA HD64570 register definitions - all addresses for mode 0 (8086 MPU)
24 #define DMER 0x09 /* DMA Master Enable */
32 #define IER0 0x14 /* Interrupt Enable 0 */
33 #define IER1 0x15 /* Interrupt Enable 1 */
34 #define IER2 0x16 /* Interrupt Enable 2 */
42 /* MSCI channel (port) 0 registers - offset 0x20
43 MSCI channel (port) 1 registers - offset 0x40 */
48 #define TRBL 0x00 /* TX/RX buffer L */
49 #define TRBH 0x01 /* TX/RX buffer H */
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H A Dhd64572.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * hd64572.h Description of the Hitachi HD64572 (SCA-II), valid for
8 * Copyright: (c) 2000-2001 Cyclades Corp.
15 * PC300 initial CVS version (3.4.0-pre1)
42 #define IER0 0x74 /* Interrupt Enable Register 0 */
43 #define IER1 0x78 /* Interrupt Enable Register 1 */
47 #define DRX_REG(reg, chan) (reg + 0x40*chan) /* DMA Rx */
49 #define TRX_REG(reg, chan) (reg + 0x20*chan) /* Timer Rx */
52 #define IR0_DRX(val, chan) ((val)<<(8*(chan))) /* Int DMA Rx */
65 #define RXS 0x13c /* RX clock source */
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/linux/drivers/net/ethernet/broadcom/
H A Db44.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 #define DEVCTRL_MPM 0x00000040 /* Magic Packet PME Enable (B0 only) */
10 #define DEVCTRL_PFE 0x00000080 /* Pattern Filtering Enable */
13 #define DEVCTRL_PME 0x00001000 /* PHY Mode Enable */
14 #define DEVCTRL_PMCE 0x00002000 /* PHY Mode Clocks Enable */
17 #define B44_BIST_STAT 0x000CUL /* Built-In Self-Test Status */
43 #define ISTAT_RX 0x00010000 /* RX Interrupt */
57 #define B44_RXBURST 0x00A4UL /* RX Max Burst Length */
59 #define MAC_CTRL_CRC32_ENAB 0x00000001 /* CRC32 Generation Enable */
66 #define MAC_FLOW_PAUSE_ENAB 0x00008000 /* Enable Pause Frame Generation */
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/linux/drivers/net/ethernet/xilinx/
H A Dxilinx_axienet.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
35 /* Jumbo frame support for Tx & Rx. Default: disabled (cleared) */
38 /* VLAN Rx & Tx frame support. Default: disabled (cleared) */
41 /* Enable recognition of flow control frames on Rx. Default: enabled (set) */
54 /* Enable Length/Type error checking for incoming frames. When this option is
62 /* Enable the transmitter. Default: enabled (set) */
65 /* Enable the receiver. Default: enabled (set) */
124 /* Default TX/RX Threshold and delay timer values for SGDMA mode */
139 #define XAXIDMA_BD_STS_RXSOF_MASK 0x08000000 /* First rx pkt */
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/linux/drivers/net/ethernet/sun/
H A Dsunqe.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 #define GLOB_MSIZE 0x0cUL /* Local-memory Size */
22 #define GLOB_CTRL_EPAR 0x00000020 /* Enable parity */
45 /* The following registers are for per-qe channel information/status. */
48 #define CREG_RXDS 0x08UL /* RX descriptor ring ptr */
50 #define CREG_RIMASK 0x10UL /* RX Interrupt Mask */
54 #define CREG_RXWBUFPTR 0x20UL /* Local memory rx write ptr */
55 #define CREG_RXRBUFPTR 0x24UL /* Local memory rx read ptr */
59 #define CREG_PIPG 0x34UL /* Inter-Frame Gap */
74 #define CREG_STAT_CCOFLOW 0x00100000 /* TX Coll-counter Overflow */
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H A Dsungem.h1 /* SPDX-License-Identifier: GPL-2.0 */
26 #define GREG_SEBSTATE_RXWON 0x00000004 /* RX won internal arbitration */
31 #define GREG_CFG_RXDMALIM 0x000007c0 /* RX DMA grant limit */
34 #define GREG_CFG_ENBUG2FIX 0x00001000 /* Fix Rx hang after overflow */
39 * This auto-clearing does not occur when the alias at GREG_STAT2
48 #define GREG_STAT_RXDONE 0x00000010 /* One RX frame arrived */
49 #define GREG_STAT_RXNOBUF 0x00000020 /* No free RX buffers available */
50 #define GREG_STAT_RXTAGERR 0x00000040 /* RX tag framing is corrupt */
53 #define GREG_STAT_RXMAC 0x00008000 /* RX MAC signalled interrupt */
69 * signalled to the cpu. GREG_IACK can be used to clear specific top-level
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/linux/net/ncsi/
H A Dncsi-pkt.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 unsigned char revision; /* NCSI version - 0x01 */
75 /* AEN Enable */
101 unsigned char enable; /* Enable or disable */ member
106 /* Enable VLA
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/linux/drivers/net/hamradio/
H A Dz8530.h1 /* SPDX-License-Identifier: GPL-2.0 */
33 #define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */
39 #define EXT_INT_ENAB 0x1 /* Ext Int Enable */
40 #define TxINT_ENAB 0x2 /* Tx Int Enable */
43 #define RxINT_DISAB 0 /* Rx Int Disable */
44 #define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */
45 #define INT_ALL_Rx 0x10 /* Int on all Rx Characters or error */
50 #define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */
56 #define RxENABLE 0x1 /* Rx Enable */
59 #define RxCRC_ENAB 0x8 /* Rx CRC Enable */
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/linux/drivers/net/ethernet/intel/igb/
H A De1000_82575.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
58 /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
62 /* Receive Descriptor - Advanced */
95 /* Transmit Descriptor - Advanced */
117 #define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */
118 #define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
134 /* IPSec Encrypt Enable for ESP */
141 #define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Queue */
145 #define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Queue */
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/linux/drivers/tty/serial/
H A Dzs.h1 /* SPDX-License-Identifier: GPL-2.0 */
38 * Per-SCC state for locking and the interrupt handler.
53 #define ZS_BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
86 #define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */
90 /* Write Register 1 (Tx/Rx/Ext Int Enable and WAIT/DMA Commands) */
91 #define EXT_INT_ENAB 0x1 /* Ext Int Enable */
92 #define TxINT_ENAB 0x2 /* Tx Int Enable */
95 #define RxINT_DISAB 0 /* Rx Int Disable */
96 #define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */
97 #define RxINT_ALL 0x10 /* Int on all Rx Characters or error */
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H A Dsunzilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
24 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
57 #define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */
63 #define EXT_INT_ENAB 0x1 /* Ext Int Enable */
64 #define TxINT_ENAB 0x2 /* Tx Int Enable */
67 #define RxINT_DISAB 0 /* Rx Int Disable */
68 #define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */
69 #define INT_ALL_Rx 0x10 /* Int on all Rx Characters or error */
75 #define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */
81 #define RxENAB 0x1 /* Rx Enable */
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H A Dip22zilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
32 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
65 #define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */
71 #define EXT_INT_ENAB 0x1 /* Ext Int Enable */
72 #define TxINT_ENAB 0x2 /* Tx Int Enable */
75 #define RxINT_DISAB 0 /* Rx Int Disable */
76 #define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */
77 #define INT_ALL_Rx 0x10 /* Int on all Rx Characters or error */
83 #define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */
89 #define RxENAB 0x1 /* Rx Enable */
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H A Dpmac_zilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
25 * of "escc" node (ie. ch-a or ch-b)
64 if (uap->flags & PMACZILOG_FLAG_IS_CHANNEL_A) in pmz_get_port_A()
66 return uap->mate; in pmz_get_port_A()
78 writeb(reg, port->control_reg); in read_zsreg()
79 return readb(port->control_reg); in read_zsreg()
85 writeb(reg, port->control_reg); in write_zsreg()
86 writeb(value, port->control_reg); in write_zsreg()
91 return readb(port->data_reg); in read_zsdata()
96 writeb(data, port->data_reg); in write_zsdata()
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H A Dxilinx_uartps.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (c) 2011 - 2014 Xilinx, Inc.
7 * This driver has originally been pushed by Xilinx using a Zynq-branding. This
38 /* Rx Trigger level */
41 MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
43 /* Rx Timeout */
46 MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
51 #define CDNS_UART_IER 0x08 /* Interrupt Enable */
56 #define CDNS_UART_RXTOUT 0x1C /* RX Timeout */
57 #define CDNS_UART_RXWM 0x20 /* RX FIFO Trigger Level */
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/linux/drivers/net/ethernet/intel/e1000e/
H A Ddefines.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
13 #define E1000_WUC_APME 0x00000001 /* APM Enable */
14 #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
20 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
21 #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
22 #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
23 #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
24 #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
25 #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
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/linux/drivers/net/ethernet/intel/e1000/
H A De1000_hw.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2006 Intel Corporation. */
422 /* MAC decode size is 128K - This is the size of BAR0 */
443 (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
486 * E1000_RAR_ENTRIES - 1 multicast addresses.
503 /* Receive Descriptor - Extended */
511 __le32 mrq; /* Multiple Rx Queues */
529 /* Receive Descriptor - Packet Split */
537 __le32 mrq; /* Multiple Rx Queues */
553 __le16 length[3]; /* length of buffers 1-3 */
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/linux/Documentation/devicetree/bindings/usb/
H A Dsnps,dwc3-common.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/snps,dwc3-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Felipe Balbi <balbi@kernel.org>
14 vendor-specific implementation or as a standalone component.
17 - $ref: usb-drd.yaml#
18 - if:
24 - dr_mode
28 $ref: usb-xhci.yaml#
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/linux/drivers/net/ethernet/marvell/
H A Dsky2.h1 /* SPDX-License-Identifier: GPL-2.0 */
30 /* Yukon-2 */
32 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
33 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */
34 PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */
35 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
36 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
37 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
38 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
42 PCI_ENA_L1_EVENT = 1<<7, /* Enable PEX L1 Event */
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H A Dskge.h1 /* SPDX-License-Identifier: GPL-2.0 */
133 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
134 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
135 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
154 PC_VAUX_ENA = 1<<7, /* Switch VAUX Enable */
156 PC_VCC_ENA = 1<<5, /* Switch VCC Enable */
221 IS_NO_STAT_M1 = 1<<9, /* No Rx Status from MAC 1 */
222 IS_NO_STAT_M2 = 1<<8, /* No Rx Status from MAC 2 */
246 TST_CFG_WRITE_ON = 1<<1, /* Enable Config Reg WR */
262 CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
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/linux/sound/soc/loongson/
H A Dloongson_i2s.h1 /* SPDX-License-Identifier: GPL-2.0 */
19 #define LS_I2S_RX_DATA 0x0C /* I2S DMA RX Address */
27 #define LS_I2S_RX_ORDER 0x110 /* RX DMA Order */
33 #define I2S_CTRL_RX_EN BIT(13) /* RX enable */
34 #define I2S_CTRL_TX_EN BIT(12) /* TX enable */
35 #define I2S_CTRL_RX_DMA_EN BIT(11) /* DMA RX enable */
37 #define I2S_CTRL_TX_DMA_EN BIT(7) /* DMA TX enable */
39 #define I2S_CTRL_MCLK_EN BIT(3) /* Enable MCLK */
40 #define I2S_CTRL_RX_INT_EN BIT(1) /* RX interrupt enable */
41 #define I2S_CTRL_TX_INT_EN BIT(0) /* TX interrupt enable */
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/linux/drivers/net/ethernet/intel/igc/
H A Digc_defines.h1 /* SPDX-License-Identifier: GPL-2.0 */
19 #define IGC_WUC_PME_EN 0x00000002 /* PME Enable */
22 #define IGC_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
23 #define IGC_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
24 #define IGC_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
25 #define IGC_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
26 #define IGC_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
28 #define IGC_WUFC_FLX0 BIT(16) /* Flexible Filter 0 Enable */
29 #define IGC_WUFC_FLX1 BIT(17) /* Flexible Filter 1 Enable */
30 #define IGC_WUFC_FLX2 BIT(18) /* Flexible Filter 2 Enable */
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/linux/drivers/net/ethernet/oki-semi/pch_gbe/
H A Dpch_gbe.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 1999 - 2010 Intel Corporation.
26 * pch_gbe_regs_mac_adr - Structure holding values of mac address registers
35 * pch_udc_regs - Structure holding values of MAC registers
92 /* Interrupt Enable */
119 #define PCH_GBE_RX_RST 0x00004000 /* RX MAC, RX FIFO, RX DMA reset */
122 #define PCH_GBE_EX_LIST_EN 0x00000008 /* External List Enable */
123 #define PCH_GBE_RX_TCPIPACC_OFF 0x00000004 /* RX TCP/IP ACC Disabled */
124 #define PCH_GBE_TX_TCPIPACC_EN 0x00000002 /* TX TCP/IP ACC Enable */
125 #define PCH_GBE_RX_TCPIPACC_EN 0x00000001 /* RX TCP/IP ACC Enable */
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/linux/drivers/net/ethernet/mellanox/mlxbf_gige/
H A Dmlxbf_gige_rx.c1 // SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
5 * Copyright (C) 2020-2021 NVIDIA CORPORATION & AFFILIATES
16 void __iomem *base = priv->base; in mlxbf_gige_enable_multicast_rx()
26 void __iomem *base = priv->base; in mlxbf_gige_disable_multicast_rx()
37 void __iomem *base = priv->base; in mlxbf_gige_enable_mac_rx_filter()
40 /* Enable MAC receive filter mask for specified index */ in mlxbf_gige_enable_mac_rx_filter()
49 void __iomem *base = priv->base; in mlxbf_gige_disable_mac_rx_filter()
61 void __iomem *base = priv->base; in mlxbf_gige_set_mac_rx_filter()
63 /* Write destination MAC to specified MAC RX filter */ in mlxbf_gige_set_mac_rx_filter()
71 void __iomem *base = priv->base; in mlxbf_gige_get_mac_rx_filter()
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