Lines Matching +full:rx +full:- +full:enable

1 /* SPDX-License-Identifier: GPL-2.0 */
38  * Per-SCC state for locking and the interrupt handler.
53 #define ZS_BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
86 #define RES_Rx_CRC	0x40	/* Reset Rx CRC Checker */
90 /* Write Register 1 (Tx/Rx/Ext Int Enable and WAIT/DMA Commands) */
91 #define EXT_INT_ENAB	0x1	/* Ext Int Enable */
92 #define TxINT_ENAB	0x2	/* Tx Int Enable */
95 #define RxINT_DISAB	0	/* Rx Int Disable */
96 #define RxINT_FCERR	0x8	/* Rx Int on First Character Only or Error */
97 #define RxINT_ALL	0x10	/* Int on all Rx Characters or error */
103 #define WT_RDY_ENAB	0x80	/* Wait/Ready Enable */
108 #define RxENABLE	0x1	/* Rx Enable */
111 #define RxCRC_ENAB	0x8	/* Rx CRC Enable */
114 #define Rx5		0x0	/* Rx 5 Bits/Character */
115 #define Rx7		0x40	/* Rx 7 Bits/Character */
116 #define Rx6		0x80	/* Rx 6 Bits/Character */
117 #define Rx8		0xc0	/* Rx 8 Bits/Character */
121 #define PAR_ENA		0x1	/* Parity Enable */
124 #define SYNC_ENAB	0	/* Sync Modes Enable */
142 #define TxCRC_ENAB	0x1	/* Tx CRC Enable */
144 #define SDLC_CRC	0x4	/* SDLC/CRC-16 */
145 #define TxENAB		0x8	/* Tx Enable */
154 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
156 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
164 #define MIE		8	/* Master Interrupt Enable */
205 #define BRENABL		1	/* Baud rate generator enable */
219 #define WR7P_EN		1	/* WR7 Prime SDLC Feature Enable */
229 #define Rx_CH_AV	0x1	/* Rx Character Available */
240 /* Residue Data for 8 Rx bits/char programmed */
249 /* Special Rx Condition Interrupts */
251 #define Rx_OVR		0x20	/* Rx Overrun Error */
255 /* Read Register 2 (Interrupt Vector (WR2) -- channel A).  */
257 /* Read Register 2 (Modified Interrupt Vector -- channel B).  */
259 /* Read Register 3 (Interrupt Pending Bits -- channel A only).  */
262 #define CHBRxIP		0x4	/* Channel B Rx IP */
265 #define CHARxIP		0x20	/* Channel A Rx IP */