Home
last modified time | relevance | path

Searched full:rtcclk (Results 1 – 15 of 15) sorted by relevance

/linux/arch/riscv/boot/dts/sifive/
H A Dhifive-unleashed-a00.dts9 /* Clock frequency (in Hz) of the PCB crystal for rtcclk */
37 rtcclk: rtcclk { label
41 clock-output-names = "rtcclk";
H A Dhifive-unmatched-a00.dts10 /* Clock frequency (in Hz) of the PCB crystal for rtcclk */
38 rtcclk: rtcclk { label
42 clock-output-names = "rtcclk";
H A Dfu540-c000.dtsi198 clocks = <&hfclk>, <&rtcclk>;
H A Dfu740-c000.dtsi199 clocks = <&hfclk>, <&rtcclk>;
/linux/Documentation/devicetree/bindings/clock/sifive/
H A Dfu540-prci.yaml20 The hfclk and rtcclk nodes are required, and represent physical
39 - const: rtcclk
57 clocks = <&hfclk>, <&rtcclk>;
H A Dfu740-prci.yaml21 The hfclk and rtcclk nodes are required, and represent physical
40 - const: rtcclk
61 clocks = <&hfclk>, <&rtcclk>;
/linux/drivers/rtc/
H A Drtc-sunplus.c59 struct clk *rtcclk; member
254 sp_rtc->rtcclk = devm_clk_get(&plat_dev->dev, NULL); in sp_rtc_probe()
255 if (IS_ERR(sp_rtc->rtcclk)) in sp_rtc_probe()
256 return dev_err_probe(&plat_dev->dev, PTR_ERR(sp_rtc->rtcclk), in sp_rtc_probe()
264 ret = clk_prepare_enable(sp_rtc->rtcclk); in sp_rtc_probe()
301 clk_disable_unprepare(sp_rtc->rtcclk); in sp_rtc_probe()
312 clk_disable_unprepare(sp_rtc->rtcclk); in sp_rtc_remove()
/linux/Documentation/devicetree/bindings/rtc/
H A Dapm,xgene-rtc.yaml44 clocks = <&rtcclk 0>;
/linux/drivers/pinctrl/pxa/
H A Dpinctrl-pxa25x.c31 PXA_FUNCTION(1, 1, "RTCCLK")),
173 PXA_FUNCTION(1, 1, "RTCCLK"),
/linux/drivers/pinctrl/
H A Dpinctrl-amd.c148 0 0 61 usec (2 RtcClk) 976 usec in amd_gpio_set_debounce()
149 0 1 244 usec (8 RtcClk) 3.9 msec in amd_gpio_set_debounce()
150 1 0 15.6 msec (512 RtcClk) 250 msec in amd_gpio_set_debounce()
151 1 1 62.5 msec (2048 RtcClk) 1 sec in amd_gpio_set_debounce()
/linux/drivers/clk/sifive/
H A Dsifive-prci.h19 * hfclk and rtcclk
/linux/arch/arm/boot/dts/microchip/
H A Dat91-sama5d27_wlsom1.dtsi367 conf-rtcclk {
/linux/drivers/clk/hisilicon/
H A Dclk-hi3620.c137 { HI3620_RTCCLK, "rtcclk", "pclk", CLK_SET_RATE_PARENT, 0x20, 5, 0, },
/linux/drivers/clk/samsung/
H A Dclk-exynos850.c1615 PNAME(mout_hsi_rtc_p) = { "rtcclk", "oscclk" };
H A Dclk-exynos2200.c2843 PNAME(mout_mux_clk_hsi0_rtcclk_p) = { "rtcclk", "oscclk" };