| /linux/Documentation/arch/loongarch/ |
| H A D | introduction.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V. There are
8 currently 3 variants: a reduced 32-bit version (LA32R), a standard 32-bit
9 version (LA32S) and a 64-bit version (LA64). There are 4 privilege levels
22 ----
24 LoongArch has 32 GPRs ( ``$r0`` ~ ``$r31`` ); each one is 32-bit wide in LA32
25 and 64-bit wide in LA64. ``$r0`` is hard-wired to zero, and the other registers
26 are not architecturally special. (Except ``$r1``, which is hard-wired as the
27 link register of the BL instruction.)
29 The kernel uses a variant of the LoongArch register convention, as described in
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| /linux/drivers/net/ethernet/chelsio/cxgb4vf/ |
| H A D | t4vf_defs.h | 2 * This file is part of the Chelsio T4 PCI-E SR-IOV Virtual Function Ethernet
5 * Copyright (c) 2009-2010 Chelsio Communications, Inc. All rights reserved.
17 * - Redistributions of source code must retain the above
21 * - Redistributions in binary form must reproduce the above
42 * The VF Register Map.
45 * bus module (PL) and CPU Interface Module (CIM) components are mapped via
46 * the Slice to Module Map Table (see below) in the Physical Function Register
47 * Map. The Mail Box Data (MBDATA) range is mapped via the PCI-E Mailbox Base
48 * and Offset registers in the PF Register Map. The MBDATA base address is
50 * and VFs, and therefore must fit in both the VF and PF Register Maps without
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| /linux/Documentation/devicetree/bindings/net/ |
| H A D | mdio-mux-mmioreg.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/mdio-mux-mmioreg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Properties for an MDIO bus multiplexer controlled by a memory-mapped device
10 - Andrew Lunn <andrew@lunn.ch>
13 This is a special case of a MDIO bus multiplexer. A memory-mapped device,
14 like an FPGA, is used to control which child bus is connected. The mdio-mux
15 node must be a child of the memory-mapped device. The driver currently only
16 supports devices with 8, 16 or 32-bit registers.
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| /linux/Documentation/devicetree/bindings/pci/ |
| H A D | snps,dw-pcie.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
16 # Please create a separate DT-schema for your DWC PCIe Root Port controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie
23 - compatible
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| /linux/Documentation/driver-api/ |
| H A D | io_ordering.rst | 2 Ordering I/O writes to memory-mapped addresses
5 On some platforms, so-called memory-mapped I/O is weakly ordered. On such
7 memory-mapped addresses on their device arrive in the order intended. This is
8 typically done by reading a 'safe' device or bridge register, causing the I/O
39 CPU A: (void)readl(safe_register); /* maybe a config register? */
46 CPU B: (void)readl(safe_register); /* maybe a config register? */
|
| H A D | uio-howto.rst | 5 :Author: Hans-Jürgen Koch Linux developer, Linutronix
6 :Date: 2006-12-11
12 ------------
18 -------
39 - The device has memory that can be mapped. The device can be
42 - The device usually generates interrupts.
44 - The device does not fit into one of the standard kernel subsystems.
47 ---------------
54 --------
64 - only one small kernel module to write and maintain.
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| /linux/drivers/virt/nitro_enclaves/ |
| H A D | ne_pci_dev.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright 2020-2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
21 * PCI_DEVICE_ID_NE - Nitro Enclaves PCI device id.
25 * PCI_BAR_NE - Nitro Enclaves PCI device MMIO BAR.
34 * NE_ENABLE - (1 byte) Register to notify the device that the driver is using
42 * NE_VERSION - (2 bytes) Register to select the device run-time version
49 * NE_COMMAND - (4 bytes) Register to notify the device what command was
50 * requested (Write-Only).
55 * NE_EVTCNT - (4 bytes) Register to notify the driver that a reply or a device
56 * event is available (Read-Only):
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| /linux/Documentation/devicetree/bindings/power/reset/ |
| H A D | syscon-reboot-mode.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/power/reset/syscon-reboot-mode.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sebastian Reichel <sre@kernel.org>
13 This driver gets reboot mode magic value from reboot-mode driver
14 and stores it in a SYSCON mapped register. Then the bootloader
16 value stored. The SYSCON mapped register is retrieved from the
17 parental dt-node plus the offset. So the SYSCON reboot-mode node
18 should be represented as a sub-node of a "syscon", "simple-mfd" node.
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| /linux/Documentation/arch/m68k/ |
| H A D | buddha-driver.rst | 8 ------------------------------------------------------------------------
10 Register map of the Buddha IDE controller and the
11 Buddha-part of the Catweasel Zorro-II version
21 product number: 0 (42 for Catweasel Z-II)
23 Rom-vector: $1000
25 The card should be a Z-II board, size 64K, not for freemem
26 list, Rom-Vektor is valid, no second Autoconfig-board on the
30 as the Amiga Kickstart does: The lower nibble of the 8-Bit
34 the whole card disappears from $e8 and is mapped to the new
36 otherwise your chance is only 1:16 to find the board :-).
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| /linux/drivers/net/ethernet/arc/ |
| H A D | emac.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2004-2013 Synopsys, Inc. (www.synopsys.com)
12 #include <linux/dma-mapping.h>
17 /* STATUS and ENABLE Register bit masks */
29 /* CONTROL Register bit masks */
34 #define ENFL_MASK (1 << 10) /* Enable Full-duplex */
38 #define OWN_MASK (1 << 31) /* 0-CPU or 1-EMAC owns buffer */
52 /* ARC EMAC register set combines entries for MAC and MDIO */
77 * struct arc_emac_bd - EMAC buffer descriptor (BD).
80 * @data: 32-bit byte addressable pointer to the packet data.
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| /linux/drivers/media/rc/ |
| H A D | ite-cir.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 /* platform driver name to register */
9 #define ITE_DRIVER_NAME "ite-cir"
34 /* hw-specific operation function pointers; most of these must be
98 /* duty cycle, 0-100 */
114 /* low-speed carrier frequency limits (Hz) */
118 /* high-speed carrier frequency limits (Hz) */
130 * n in RDCR produces a tolerance of +/- n * 6.25% around the center
135 * frequency A = (H - L) / (H + L). We can use this in order to honor the
136 * s_rx_carrier_range() call in ir-core. We'll suppose that any request
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| /linux/drivers/net/ethernet/wiznet/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
55 after mapping to Memory-Mapped I/O space.
61 using Indirect Mode Address Register and Indirect Mode Data Register,
62 which are directly mapped to Memory-Mapped I/O space.
85 will be called w5100-spi.
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| /linux/sound/soc/sof/intel/ |
| H A D | hda-ipc.h | 1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
15 * Primary register, mapped to
16 * - DIPCTDR (HIPCIDR) in sideband IPC (cAVS 1.8+)
17 * - DIPCT in cAVS 1.5 IPC
19 * Secondary register, mapped to:
20 * - DIPCTDD (HIPCIDD) in sideband IPC (cAVS 1.8+)
21 * - DIPCTE in cAVS 1.5 IPC
24 /* Common bits in primary register */
28 /* Target, 0 - normal message, 1 - compact message(cAVS compatible) */
30 /* Direction, 0 - request, 1 - response */
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| /linux/Documentation/devicetree/bindings/powerpc/fsl/ |
| H A D | pamu.txt | 5 The PAMU is an I/O MMU that provides device-to-memory access control and
10 - compatible : <string>
11 First entry is a version-specific string, such as
12 "fsl,pamu-v1.0". The second is "fsl,pamu".
13 - ranges : <prop-encoded-array>
14 A standard property. Utilized to describe the memory mapped
16 be set to the total size of the register space of all
20 - interrupts : <prop-encoded-array>
25 - #address-cells: <u32>
27 - #size-cells : <u32>
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| /linux/arch/riscv/include/uapi/asm/ |
| H A D | kvm.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
23 #define KVM_INTERRUPT_SET -1U
24 #define KVM_INTERRUPT_UNSET -2U
200 * extension IDs defined by the RISC-V SBI specification.
248 /* Config registers are mapped as type 1 */
253 /* Core registers are mapped as type 2 */
258 /* Control and status registers are mapped as type 3 */
270 /* Timer registers are mapped as type 4 */
275 /* F extension registers are mapped as type 5 */
280 /* D extension registers are mapped as type 6 */
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| /linux/drivers/net/ethernet/freescale/ |
| H A D | fsl_pq_mdio.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Freescale PowerQUICC Ethernet Driver -- MIIM bus implementation
9 * Copyright 2002-2004, 2008-2009 Freescale Semiconductor, Inc.
52 u32 ieventm; /* MDIO Interrupt event register (for etsec2)*/
53 u32 imaskm; /* MDIO Interrupt mask register (for etsec2)*/
55 u32 emapm; /* MDIO Event mapping register (for etsec2)*/
63 /* Number of microseconds to wait for an MII register to respond */
72 * Per-device-type data. Each type of device tree node that we support gets
79 * @get_tbipa: determines the address of the TBIPA register
90 * Write value to the PHY at mii_id at register regnum, on the bus attached
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| /linux/Documentation/devicetree/bindings/clock/ |
| H A D | keystone-pll.txt | 3 and PAPLL are controlled by the memory mapped register where as the Main
4 PLL is controlled by a PLL controller registers along with memory mapped
9 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
12 - #clock-cells : from common clock binding; shall be set to 0.
13 - compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock"
14 - clocks : parent clock phandle
15 - reg - pll control0 and pll multiplier registers
16 - reg-names : control, multiplier and post-divider. The multiplier and
17 post-divider registers are applicable only for main pll clock
18 - fixed-postdiv : fixed post divider value. If absent, use clkod register bits
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| /linux/drivers/net/arcnet/ |
| H A D | com20020.h | 2 * Linux ARCnet driver - COM20020 chipset support - function declarations
5 * Written 1994-1999 by Avery Pennarun.
48 u32 size; /* 0x00 - auto, e.g. length of entire bar */
85 #define COM20020_REG_W_ADDR_HI 2 /* control for IO-mapped memory */
87 #define COM20020_REG_RW_MEMDATA 4 /* data port for IO-mapped memory */
94 /* in the ADDR_HI register */
97 /* in the DIAGSTAT register */
100 /* in the CONFIG register */
105 /* in SETUP register */
107 #define P1MODE 0x80 /* enable P1-MODE for Backplane */
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| /linux/arch/sh/mm/ |
| H A D | tlb-pteaex.c | 2 * arch/sh/mm/tlb-pteaex.c
4 * TLB operations for SH-X3 CPUs featuring PTE ASID Extensions.
25 if (vma && current->active_mm != vma->vm_mm) in __update_tlb()
30 /* Set PTEH register */ in __update_tlb()
39 /* Set PTEA register */ in __update_tlb()
44 * the protection bits (with the exception of the compat-mode SZ in __update_tlb()
50 /* Set PTEL register */ in __update_tlb()
64 * While SH-X2 extended TLB mode splits out the memory-mapped I/UTLB
65 * data arrays, SH-X3 cores with PTEAEX split out the memory-mapped
67 * in extended mode, the legacy 8-bit ASID field in address array 1 has
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| /linux/drivers/char/tpm/ |
| H A D | tpm_tis_i2c.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2014-2021 Nuvoton Technology corporation
4 * Copyright (C) 2019-2022 Infineon Technologies AG
14 #include <linux/crc-ccitt.h>
27 /* TIS-compatible register address to avoid clash with TPM_ACCESS (0x00) */
30 /* Mask to extract the I2C register from TIS register addresses */
33 /* Default Guard Time of 250µs until interface capability register is read */
74 * tpm_tis_core uses the register addresses as defined in Table 19 "Allocation
75 * of Register Space for FIFO TPM Access" of the TCG PC Client PTP
77 * those addresses need to mapped to the registers defined for I2C TPMs in
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| /linux/drivers/net/wwan/iosm/ |
| H A D | iosm_ipc_pcie.h | 1 /* SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2020-21 Intel Corporation.
35 * enum ipc_pcie_sleep_state - Enum type to different sleep state transitions
45 * struct iosm_pcie - IPC_PCIE struct.
48 * @ipc_regs: Remapped CP doorbell address of the irq register
59 * @doorbell_write: doorbell write register
81 * struct ipc_skb_cb - Struct definition of the socket buffer which is mapped to
83 * @mapping: Store physical or IOVA mapped address of skb virtual add.
85 * @len: Length of the DMA mapped region
96 * enum ipc_ul_usr_op - Control operation to execute the right action on
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| /linux/drivers/net/ethernet/cavium/liquidio/ |
| H A D | octeon_mem_ops.h | 7 * Copyright (c) 2003-2016 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
27 /** Read a 64-bit value from a BAR1 mapped core memory address.
28 * @param oct - pointer to the octeon device.
29 * @param core_addr - the address to read from.
31 * The range_idx gives the BAR1 index register for the range of address
32 * in which core_addr is mapped.
34 * @return 64-bit value read from Core memory
38 /** Read a 32-bit value from a BAR1 mapped core memory address.
39 * @param oct - pointer to the octeon device.
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| H A D | octeon_device.h | 7 * Copyright (c) 2003-2016 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
53 /** Endian-swap modes supported by Octeon. */
78 /*--------------- PCI BAR1 index registers -------------*/
123 /*---------------------------DISPATCH LIST-------------------------------*/
160 /*----------------------- THE OCTEON DEVICE ---------------------------*/
165 * Octeon gets mapped to different physical address spaces in
169 /** PCI address to which the BAR is mapped. */
175 /** Length that has been mapped to phys. address space. */
178 /** The physical address to which the PCI address space is mapped. */
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| /linux/drivers/net/ethernet/sfc/falcon/ |
| H A D | io.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2005-2006 Fen Systems Ltd.
5 * Copyright 2006-2013 Solarflare Communications Inc.
16 * NIC register I/O
24 * up to 128 bits. Whenever the host writes part of such a register,
26 * underlying register until all 4 dwords have been written. A
27 * similar buffering scheme applies to host access to the NIC's 64-bit
30 * Writes to different CSRs and 64-bit SRAM words must be serialised,
34 * We also serialise reads from 128-bit CSRs and SRAM with the same
39 * 128-bit but are special-cased in the BIU to avoid the need for
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| /linux/drivers/block/mtip32xx/ |
| H A D | mtip32xx.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * mtip32xx.h - Header file for the P320 SSD Block Driver
22 /* offset of Device Control register in PCIe extended capabilites space */
54 * is used to access the correct s_active/Command Issue register based
67 * NOTE: This is the driver maximum; check dd->slot_groups for actual value.
95 * Per-tag bitfield size in longs.
104 (U32_PER_LONG-1))/U32_PER_LONG)
181 mtip_workq_sdbfx(w->port, group, w->completed); \
184 /* Register Frame Information Structure (FIS), host to device. */
188 * - 27h Register FIS, host to device.
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