Lines Matching +full:register +full:- +full:mapped
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 /* platform driver name to register */
9 #define ITE_DRIVER_NAME "ite-cir"
34 /* hw-specific operation function pointers; most of these must be
98 /* duty cycle, 0-100 */
114 /* low-speed carrier frequency limits (Hz) */
118 /* high-speed carrier frequency limits (Hz) */
130 * n in RDCR produces a tolerance of +/- n * 6.25% around the center
135 * frequency A = (H - L) / (H + L). We can use this in order to honor the
136 * s_rx_carrier_range() call in ir-core. We'll suppose that any request
170 * Environment Control - Low Pin Count Input / Output
171 * (EC - LPC I/O)
175 /* register offsets */
176 #define IT87_DR 0x00 /* data register */
177 #define IT87_IER 0x01 /* interrupt enable register */
178 #define IT87_RCR 0x02 /* receiver control register */
179 #define IT87_TCR1 0x03 /* transmitter control register 1 */
180 #define IT87_TCR2 0x04 /* transmitter control register 2 */
181 #define IT87_TSR 0x05 /* transmitter status register */
182 #define IT87_RSR 0x06 /* receiver status register */
183 #define IT87_BDLR 0x05 /* baud rate divisor low byte register */
184 #define IT87_BDHR 0x06 /* baud rate divisor high byte register */
185 #define IT87_IIR 0x07 /* interrupt identification register */
187 #define IT87_IOREG_LENGTH 0x08 /* length of register file */
194 #define IT87_BR 0x10 /* baud rate register enable */
202 #define IT87_HCFS 0x40 /* high-speed carrier frequency select */
212 * 0x00 -> 1, 0x10 -> 7, 0x20 -> 17,
213 * 0x30 -> 25 */
228 #define IT87_RXFTO 0x80 /* receiver FIFO time-out */
252 * IT8512E/F register definitions for register definitions for those
256 /* register offsets */
257 #define IT85_C0DR 0x00 /* data register */
258 #define IT85_C0MSTCR 0x01 /* master control register */
259 #define IT85_C0IER 0x02 /* interrupt enable register */
260 #define IT85_C0IIR 0x03 /* interrupt identification register */
261 #define IT85_C0CFR 0x04 /* carrier frequency register */
262 #define IT85_C0RCR 0x05 /* receiver control register */
263 #define IT85_C0TCR 0x06 /* transmitter control register */
264 #define IT85_C0SCK 0x07 /* slow clock control register */
265 #define IT85_C0BDLR 0x08 /* baud rate divisor low byte register */
266 #define IT85_C0BDHR 0x09 /* baud rate divisor high byte register */
267 #define IT85_C0TFSR 0x0a /* transmitter FIFO status register */
268 #define IT85_C0RFSR 0x0b /* receiver FIFO status register */
269 #define IT85_C0WCL 0x0d /* wakeup code length register */
270 #define IT85_C0WCR 0x0e /* wakeup code read/write register */
271 #define IT85_C0WPS 0x0f /* wakeup power control/status register */
273 #define IT85_IOREG_LENGTH 0x10 /* length of register file */
280 * 0x00 -> 1, 0x04 -> 7, 0x08 -> 17,
281 * 0x0c -> 25 */
329 #define IT85_RXFTO 0x80 /* receiver FIFO time-out */
349 * suggest that it maps the 16 registers of IT8512 onto two 8-register banks,
350 * selectable by a single bank-select bit that's mapped onto both banks. The
351 * IT8512 registers are mapped in a different order, so that the first bank
353 * reserved high-order bit are placed at the same offset in both banks in
357 /* register offsets */
359 /* mapped onto both banks */
360 #define IT8708_BANKSEL 0x07 /* bank select register */
363 /* mapped onto the low bank */
364 #define IT8708_C0DR 0x00 /* data register */
365 #define IT8708_C0MSTCR 0x01 /* master control register */
366 #define IT8708_C0IER 0x02 /* interrupt enable register */
367 #define IT8708_C0IIR 0x03 /* interrupt identification register */
368 #define IT8708_C0RFSR 0x04 /* receiver FIFO status register */
369 #define IT8708_C0RCR 0x05 /* receiver control register */
370 #define IT8708_C0TFSR 0x06 /* transmitter FIFO status register */
371 #define IT8708_C0TCR 0x07 /* transmitter control register */
373 /* mapped onto the high bank */
374 #define IT8708_C0BDLR 0x01 /* baud rate divisor low byte register */
375 #define IT8708_C0BDHR 0x02 /* baud rate divisor high byte register */
376 #define IT8708_C0CFR 0x04 /* carrier frequency register */
381 #define IT8708_C0SCK 0x03 /* slow clock control register */
382 #define IT8708_C0WCL 0x05 /* wakeup code length register */
383 #define IT8708_C0WCR 0x06 /* wakeup code read/write register */
384 #define IT8708_C0WPS 0x07 /* wakeup power control/status register */
386 #define IT8708_IOREG_LENGTH 0x08 /* length of register file */
408 * a specific firmware running on the IT8512's embedded micro-controller.
409 * In addition of the embedded micro-controller, the IT8512 chip contains a
412 * micro-controller. The CIR module is only accessible by the
413 * micro-controller.
415 * The battery-backed SRAM module is accessible by the host CPU and the
416 * micro-controller. So one of the MC's firmware role is to act as a bridge
420 * communication protocol is not, so it was reverse-engineered.
423 /* register offsets */
427 #define IT8709_IOREG_LENGTH 0x02 /* length of register file */
429 /* register offsets inside the SRAM module */
431 #define IT8709_REG_IDX 0x1b /* index of the CIR register to access */
433 #define IT8709_IIR 0x1e /* interrupt identification register */
434 #define IT8709_RFSR 0x1f /* receiver FIFO status register */