| /linux/Documentation/devicetree/bindings/powerpc/fsl/ |
| H A D | dcsr.txt | 17 debug blocks defined within this memory space.
21 - compatible
24 Definition: Must include "fsl,dcsr" and "simple-bus".
25 The DCSR space exists in the memory-mapped bus.
27 - #address-cells
33 - #size-cells
40 - ranges
42 Value type: <prop-encoded-array>
44 range of the DCSR space.
48 #address-cells = <1>;
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| H A D | dma.txt | 4 This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
9 - compatible : must include "fsl,elo-dma"
10 - reg : DMA General Status Register, i.e. DGSR which contains
12 - ranges : describes the mapping between the address space of the
13 DMA channels and the address space of the DMA controller
14 - cell-index : controller index. 0 for controller @ 0x8100
15 - interrupts : interrupt specifier for DMA IRQ
17 - DMA channel nodes:
18 - compatible : must include "fsl,elo-dma-channel"
20 - reg : DMA channel specific registers
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| H A D | interlaken-lac.txt | 2 Freescale Interlaken Look-Aside Controller Device Bindings
6 - Interlaken Look-Aside Controller (LAC) Node
7 - Example LAC Node
8 - Interlaken Look-Aside Controller (LAC) Software Portal Node
9 - Interlaken Look-Aside Controller (LAC) Software Portal Child Nodes
10 - Example LAC SWP Node with Child Nodes
13 Interlaken Look-Aside Controller (LAC) Node
17 The Interlaken is a narrow, high speed channelized chip-to-chip interface. To
18 facilitate interoperability between a data path device and a look-aside
19 co-processor, the Interlaken Look-Aside protocol is defined for short
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| H A D | raideng.txt | 3 RAID Engine nodes are defined to describe on-chip RAID accelerators. Each RAID
11 - compatible: Should contain "fsl,raideng-v1.0" as the value
15 - reg: offset and length of the register set for the device
16 - ranges: standard ranges property specifying the translation
17 between child address space and parent address space
22 compatible = "fsl,raideng-v1.0";
23 #address-cells = <1>;
24 #size-cells = <1>;
25 reg = <0x320000 0x10000>;
30 There must be a sub-node for each job queue present in RAID Engine
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| /linux/drivers/gpu/drm/amd/include/ |
| H A D | cgs_common.h | 32 * enum cgs_ind_reg - Indirect register spaces
45 * enum cgs_ucode_id - Firmware types for different IPs
65 * struct cgs_firmware_info - Firmware information
84 * cgs_read_register() - Read an MMIO register
93 * cgs_write_register() - Write an MMIO register
102 * cgs_read_ind_register() - Read an indirect register
108 typedef uint32_t (*cgs_read_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space,
112 * cgs_write_ind_register() - Write an indirect register
117 typedef void (*cgs_write_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space,
120 #define CGS_REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT argument
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| /linux/arch/sh/drivers/pci/ |
| H A D | pci-sh7751.h | 1 /* SPDX-License-Identifier: GPL-2.0
3 * Low-Level PCI Support for SH7751 targets
6 * Paul Mundt (lethal@linux-sh.org) (c) 2003
18 #define SH7751_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */
19 #define SH7751_PCI_CONFIG_SIZE 0x1000000 /* Config space size */
20 #define SH7751_PCI_MEMORY_BASE 0xFD000000 /* Memory space base addr */
22 #define SH7751_PCI_IO_BASE 0xFE240000 /* IO space base address */
27 #define SH7751_PCICONF0 0x0 /* PCI Config Reg 0 */
30 #define SH7751_PCICONF1 0x4 /* PCI Config Reg 1 */
50 #define SH7751_PCICONF1_MES 0x00000002 /* Memory Space Control */
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| /linux/Documentation/devicetree/bindings/mtd/ |
| H A D | st,stm32-fmc2-nand.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/st,stm32-fmc2-nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christophe Kerello <christophe.kerello@foss.st.com>
15 - st,stm32mp15-fmc2
16 - st,stm32mp1-fmc2-nfc
17 - st,stm32mp25-fmc2-nfc
19 reg:
28 - description: tx DMA channel
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| /linux/drivers/pci/ |
| H A D | pci-bridge-emul.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
7 /* PCI configuration space of a PCI-to-PCI bridge. */
42 /* PCI configuration space of the PCIe capabilities */
78 * configuration space. Return PCI_BRIDGE_EMUL_HANDLED when the
82 * in-memory copy of the configuration space.
85 int reg, u32 *value);
88 * Same as ->read_base(), except it is for reading from the
89 * PCIe capability configuration space.
92 int reg, u32 *value);
95 * Same as ->read_base(), except it is for reading from the
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| H A D | pci-bridge-emul.c | 1 // SPDX-License-Identifier: GPL-2.0
12 * space (and optionally a PCIe capability configuration space) in
14 * this fake configuration space in memory. However, PCI controller
21 #include "pci-bridge-emul.h"
28 * struct pci_bridge_reg_behavior - register bits behaviors
29 * @ro: Read-Only bits
30 * @rw: Read-Write bits
31 * @w1c: Write-1-to-Clear bits
36 * multi-bit fields) when read".
39 /* Read-only bits */
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| /linux/arch/mips/loongson2ef/common/cs5536/ |
| H A D | cs5536_pci.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * read/write operation to the PCI config space of CS5536
12 * configure space are defined in cs5536_modulename.c respectively,
14 * after this virtulizing, user can access the PCI configure space
15 * directly as a normal multi-function PCI device which follows
16 * the PCI-2.2 spec.
24 CS5536_FUNC_START = -1,
53 * write to PCI config space and transfer it to MSR write.
55 void cs5536_pci_conf_write4(int function, int reg, u32 value) in cs5536_pci_conf_write4() argument
59 if ((reg < 0) || (reg > 0x100) || ((reg & 0x03) != 0)) in cs5536_pci_conf_write4()
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| /linux/Documentation/devicetree/bindings/pci/ |
| H A D | snps,dw-pcie-ep.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
16 # Please create a separate DT-schema for your DWC PCIe Endpoint controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie-ep
23 - compatible
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| H A D | nvidia,tegra20-pcie.txt | 4 - compatible: Must be:
5 - "nvidia,tegra20-pcie": for Tegra20
6 - "nvidia,tegra30-pcie": for Tegra30
7 - "nvidia,tegra124-pcie": for Tegra124 and Tegra132
8 - "nvidia,tegra210-pcie": for Tegra210
9 - "nvidia,tegra186-pcie": for Tegra186
10 - power-domains: To ungate power partition by BPMP powergate driver. Must
13 - device_type: Must be "pci"
14 - reg: A list of physical base address and length for each set of controller
15 registers. Must contain an entry for each entry in the reg-names property.
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| /linux/arch/arm/kernel/ |
| H A D | io.c | 1 // SPDX-License-Identifier: GPL-2.0
12 * Allows thread-safe access to registers shared by unrelated subsystems.
13 * The access is protected by a single MMIO-wide lock.
15 void atomic_io_modify_relaxed(void __iomem *reg, u32 mask, u32 set) in atomic_io_modify_relaxed() argument
21 value = readl_relaxed(reg) & ~mask; in atomic_io_modify_relaxed()
23 writel_relaxed(value, reg); in atomic_io_modify_relaxed()
28 void atomic_io_modify(void __iomem *reg, u32 mask, u32 set) in atomic_io_modify() argument
34 value = readl_relaxed(reg) & ~mask; in atomic_io_modify()
36 writel(value, reg); in atomic_io_modify()
42 * Copy data from IO memory space to "real" memory space.
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| /linux/Documentation/devicetree/bindings/net/pcs/ |
| H A D | snps,dw-xpcs.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/pcs/snps,dw-xpcs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Serge Semin <fancer.lancer@gmail.com>
17 optionally synthesized with a vendor-specific interface connected to
23 right to the system IO memory space.
28 - description: Synopsys DesignWare XPCS with none or unknown PMA
29 const: snps,dw-xpcs
30 - description: Synopsys DesignWare XPCS with Consumer Gen1 3G PMA
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| /linux/drivers/scsi/aic94xx/ |
| H A D | aic94xx_reg.c | 1 // SPDX-License-Identifier: GPL-2.0-only
13 /* Writing to device address space.
20 if (unlikely(asd_ha->iospace)) in asd_write_byte()
22 (unsigned long)asd_ha->io_handle[0].addr + (offs & 0xFF)); in asd_write_byte()
24 writeb(val, asd_ha->io_handle[0].addr + offs); in asd_write_byte()
31 if (unlikely(asd_ha->iospace)) in asd_write_word()
33 (unsigned long)asd_ha->io_handle[0].addr + (offs & 0xFF)); in asd_write_word()
35 writew(val, asd_ha->io_handle[0].addr + offs); in asd_write_word()
42 if (unlikely(asd_ha->iospace)) in asd_write_dword()
44 (unsigned long)asd_ha->io_handle[0].addr + (offs & 0xFF)); in asd_write_dword()
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| /linux/arch/mips/pci/ |
| H A D | pci-bcm63xx.c | 19 #include "pci-bcm63xx.h"
28 .name = "bcm63xx PCI memory space",
35 .name = "bcm63xx PCI IO space",
58 .name = "bcm63xx Cardbus memory space",
65 .name = "bcm63xx Cardbus IO space",
79 .name = "bcm63xx PCIe memory space",
86 .name = "bcm63xx PCIe IO space",
98 static u32 bcm63xx_int_cfg_readl(u32 reg) in bcm63xx_int_cfg_readl() argument
102 tmp = reg & MPI_PCICFGCTL_CFGADDR_MASK; in bcm63xx_int_cfg_readl()
109 static void bcm63xx_int_cfg_writel(u32 val, u32 reg) in bcm63xx_int_cfg_writel() argument
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| /linux/Documentation/devicetree/bindings/dma/ |
| H A D | apm-xgene-dma.txt | 1 Applied Micro X-Gene SoC DMA nodes
3 DMA nodes are defined to describe on-chip DMA interfaces in
4 APM X-Gene SoC.
7 - compatible: Should be "apm,xgene-dma".
8 - device_type: set to "dma".
9 - reg: Address and length of the register set for the device.
11 1st - DMA control and status register address space.
12 2nd - Descriptor ring control and status register address space.
13 3rd - Descriptor ring command register address space.
14 4th - Soc efuse register address space.
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| /linux/Documentation/devicetree/bindings/display/ti/ |
| H A D | ti,omap3-dss.txt | 4 See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic
8 --------
11 - compatible: "ti,omap3-dss"
12 - reg: address and length of the register space
13 - ti,hwmods: "dss_core"
14 - clocks: handle to fclk
15 - clock-names: "fck"
18 - Video ports:
19 - Port 0: DPI output
20 - Port 1: SDI output
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| H A D | ti,omap2-dss.txt | 4 See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic
8 --------
11 - compatible: "ti,omap2-dss"
12 - reg: address and length of the register space
13 - ti,hwmods: "dss_core"
16 - Video port for DPI output
19 - data-lines: number of lines used
23 -----
26 - compatible: "ti,omap2-dispc"
27 - reg: address and length of the register space
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| H A D | ti,omap4-dss.txt | 4 See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic
8 --------
11 - compatible: "ti,omap4-dss"
12 - reg: address and length of the register space
13 - ti,hwmods: "dss_core"
14 - clocks: handle to fclk
15 - clock-names: "fck"
18 - DISPC
21 - DSS Submodules: RFBI, VENC, DSI, HDMI
22 - Video port for DPI output
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| /linux/arch/arm64/include/asm/ |
| H A D | kvm_mmu.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2012,2013 - ARM Ltd
26 * runtime VA space, at the same time.
28 * Given that the kernel uses VA_BITS for its entire address space,
29 * and that half of that space (VA_BITS - 1) is used for the linear
30 * mapping, we can also limit the EL2 space t
203 int reg; vcpu_has_cache_enabled() local
262 int reg = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); kvm_get_vmid_bits() local
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| /linux/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | brcm,dpfe-cpu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/brcm,dpfe-cpu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Markus Mayer <mmayer@broadcom.com>
16 - enum:
17 - brcm,bcm7271-dpfe-cpu
18 - brcm,bcm7268-dpfe-cpu
19 - const: brcm,dpfe-cpu
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| /linux/Documentation/arch/x86/x86_64/ |
| H A D | fsgs.rst | 1 .. SPDX-License-Identifier: GPL-2.0
3 Using FS and GS segments in user space applications
10 Segment-register:Byte-address
12 The segment base address is added to the Byte-address to compute the
14 instances of data with the identical Byte-address, i.e. the same code. The
15 selection of a particular instance is purely based on the base-address in
18 In 32-bit mode the CPU provides 6 segments, which also support segment
19 limits. The limits can be used to enforce address space protections.
21 In 64-bit mode the CS/SS/DS/ES segments are ignored and the base address is
22 always 0 to provide a full 64bit address space. The FS and GS segments are
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| /linux/Documentation/devicetree/bindings/pwm/ |
| H A D | pwm-tipwmss.txt | 4 - compatible: Must be "ti,<soc>-pwmss".
5 for am33xx - compatible = "ti,am33xx-pwmss";
6 for am4372 - compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
7 for dra746 - compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"
9 - reg: physical base address and size of the registers map.
10 - address-cells: Specify the number of u32 entries needed in child nodes.
12 - size-cells: specify number of u32 entries needed to specify child nodes size
13 in reg property. Should set to 1.
14 - ranges: describes the address mapping of a memory-mapped bus. Should set to
16 parent's address space and length of the address map. For am33xx,
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| /linux/arch/powerpc/boot/dts/ |
| H A D | currituck.dts | 11 /dts-v1/;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 dcr-parent = <&{/cpus/cpu@0}>;
27 #address-cells = <1>;
28 #size-cells = <0>;
33 reg = <0>;
34 clock-frequency = <1600000000>; // 1.6 GHz
35 timebase-frequency = <100000000>; // 100Mhz
36 i-cache-line-size = <32>;
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