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/linux/drivers/net/ethernet/intel/e1000/
H A De1000_osdep.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2006 Intel Corporation. */
22 #define GBE_CONFIG_FLASH_WRITE(base, offset, count, data) \ argument
23 (iowrite16_rep(base + offset, data, count))
25 #define GBE_CONFIG_FLASH_READ(base, offset, count, data) \ argument
26 (ioread16_rep(base + (offset << 1), data, count))
28 #define er32(reg) \ argument
29 (readl(hw->hw_addr + ((hw->mac_type >= e1000_82543) \
30 ? E1000_##reg : E1000_82542_##reg)))
32 #define ew32(reg, value) \ argument
[all …]
/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn10/
H A Dhw_translate_dcn10.c2 * Copyright 2013-15 Advanced Micro Devices, Inc.
27 * Pre-requisites: headers required by header of this unit
51 #define REG(reg_name)\ macro
62 uint32_t offset, in offset_to_id() argument
67 switch (offset) { in offset_to_id()
69 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
99 case REG(DC_GPIO_HPD_A): in offset_to_id()
126 case REG(DC_GPIO_SYNCA_A): in offset_to_id()
140 /* REG(DC_GPIO_GENLK_MASK */ in offset_to_id()
141 case REG(DC_GPIO_GENLK_A): in offset_to_id()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/gpio/dce120/
H A Dhw_translate_dce120.c2 * Copyright 2013-15 Advanced Micro Devices, Inc.
27 * Pre-requisites: headers required by header of this unit
51 #define REG(reg_name)\ macro
62 uint32_t offset, in offset_to_id() argument
67 switch (offset) { in offset_to_id()
69 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
99 case REG(DC_GPIO_HPD_A): in offset_to_id()
126 case REG(DC_GPIO_SYNCA_A): in offset_to_id()
140 /* REG(DC_GPIO_GENLK_MASK */ in offset_to_id()
141 case REG(DC_GPIO_GENLK_A): in offset_to_id()
[all …]
/linux/drivers/gpio/
H A Dgpio-palmas.c1 // SPDX-License-Identifier: GPL-2.0-only
26 static int palmas_gpio_get(struct gpio_chip *gc, unsigned offset) in palmas_gpio_get() argument
29 struct palmas *palmas = pg->palmas; in palmas_gpio_get()
32 unsigned int reg; in palmas_gpio_get() local
33 int gpio16 = (offset/8); in palmas_gpio_get()
35 offset %= 8; in palmas_gpio_get()
36 reg = (gpio16) ? PALMAS_GPIO_DATA_DIR2 : PALMAS_GPIO_DATA_DIR; in palmas_gpio_get()
38 ret = palmas_read(palmas, PALMAS_GPIO_BASE, reg, &val); in palmas_gpio_get()
40 dev_err(gc->parent, "Reg 0x%02x read failed, %d\n", reg, ret); in palmas_gpio_get()
44 if (val & BIT(offset)) in palmas_gpio_get()
[all …]
H A Dgpio-pmic-eic-sprd.c1 // SPDX-License-Identifier: GPL-2.0
33 #define SPRD_PMIC_EIC_BIT(x) ((x) & (SPRD_PMIC_EIC_PER_BANK_NR - 1))
48 * struct sprd_pmic_eic - PMIC EIC controller
51 * @offset: the EIC controller's offset address of the PMIC.
52 * @reg: the array to cache the EIC registers.
59 u32 offset; member
60 u8 reg[CACHE_NR_REGS]; member
65 static void sprd_pmic_eic_update(struct gpio_chip *chip, unsigned int offset, in sprd_pmic_eic_update() argument
66 u16 reg, unsigned int val) in sprd_pmic_eic_update() argument
69 u32 shift = SPRD_PMIC_EIC_BIT(offset); in sprd_pmic_eic_update()
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H A Dgpio-cs5535.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2007-2009 Andres Salomon <dilinger@collabora.co.uk>
17 #define DRV_NAME "cs5535-gpio"
21 * 31-29,23 : reserved (always mask out)
24 * 22-16 : LPC
44 * design pattern, see Documentation/driver-api/driver-model/design-patterns.rst
61 unsigned int reg) in errata_outl() argument
63 unsigned long addr = chip->base + 0x80 + reg; in errata_outl()
68 * non-selected bits; the recommended workaround is a in errata_outl()
69 * read-modify-write operation. in errata_outl()
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H A Dgpio-npcm-sgpio.c1 // SPDX-License-Identifier: GPL-2.0
139 const enum npcm_sgpio_reg reg) in bank_reg() argument
141 switch (reg) { in bank_reg()
143 return gpio->base + bank->rdata_reg; in bank_reg()
145 return gpio->base + bank->wdata_reg; in bank_reg()
147 return gpio->base + bank->event_config; in bank_reg()
149 return gpio->base + bank->event_status; in bank_reg()
152 dev_WARN(gpio->chip.parent, "Getting here is an error condition"); in bank_reg()
157 static const struct npcm_sgpio_bank *offset_to_bank(unsigned int offset) in offset_to_bank() argument
159 unsigned int bank = GPIO_BANK(offset); in offset_to_bank()
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/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn401/
H A Dhw_translate_dcn401.c1 // SPDX-License-Identifier: MIT
27 #undef REG
28 #define REG(reg_name)\ macro
29 BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name
39 uint32_t offset, in offset_to_id() argument
44 switch (offset) { in offset_to_id()
46 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
73 case REG(DC_GPIO_HPD_A): in offset_to_id()
96 /* REG(DC_GPIO_GENLK_MASK */ in offset_to_id()
97 case REG(DC_GPIO_GENLK_A): in offset_to_id()
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/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn30/
H A Dhw_translate_dcn30.c27 * Pre-requisites: headers required by header of this unit
59 #undef REG
60 #define REG(reg_name)\ macro
71 uint32_t offset, in offset_to_id() argument
76 switch (offset) { in offset_to_id()
78 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
108 case REG(DC_GPIO_HPD_A): in offset_to_id()
134 /* REG(DC_GPIO_GENLK_MASK */ in offset_to_id()
135 case REG(DC_GPIO_GENLK_A): in offset_to_id()
160 case REG(DC_GPIO_DDC1_A): in offset_to_id()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn20/
H A Dhw_translate_dcn20.c27 * Pre-requisites: headers required by header of this unit
54 #undef REG
55 #define REG(reg_name)\ macro
66 uint32_t offset, in offset_to_id() argument
71 switch (offset) { in offset_to_id()
73 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
103 case REG(DC_GPIO_HPD_A): in offset_to_id()
129 /* REG(DC_GPIO_GENLK_MASK */ in offset_to_id()
130 case REG(DC_GPIO_GENLK_A): in offset_to_id()
155 case REG(DC_GPIO_DDC1_A): in offset_to_id()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn315/
H A Dhw_translate_dcn315.c54 #undef REG
55 #define REG(reg_name)\ macro
56 BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name
66 uint32_t offset, in offset_to_id() argument
71 switch (offset) { in offset_to_id()
73 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
103 case REG(DC_GPIO_HPD_A): in offset_to_id()
129 /* REG(DC_GPIO_GENLK_MASK */ in offset_to_id()
130 case REG(DC_GPIO_GENLK_A): in offset_to_id()
155 case REG(DC_GPIO_DDC1_A): in offset_to_id()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn20/
H A Ddcn20_dpp_cm.c36 #define REG(reg)\ macro
37 dpp->tf_regs->reg
43 dpp->base.ctx
47 dpp->tf_shift->field_name, dpp->tf_mask->field_name
57 if (dpp_base->ctx->dc->debug.cm_in_bypass) in dpp2_enable_cm_block()
130 dpp2_program_degamma_lut(dpp_base, params->rgb_resulted, params->hw_points_num, !is_ram_a); in dpp2_set_degamma_pwl()
183 /* value stored in dbg reg will be 1 greater than mode we want */ in program_gamut_remap()
189 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; in program_gamut_remap()
190 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; in program_gamut_remap()
191 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12; in program_gamut_remap()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn21/
H A Dhw_translate_dcn21.c27 * Pre-requisites: headers required by header of this unit
54 #undef REG
55 #define REG(reg_name)\ macro
65 uint32_t offset, in offset_to_id() argument
70 switch (offset) { in offset_to_id()
72 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
102 case REG(DC_GPIO_HPD_A): in offset_to_id()
128 /* REG(DC_GPIO_GENLK_MASK */ in offset_to_id()
129 case REG(DC_GPIO_GENLK_A): in offset_to_id()
154 case REG(DC_GPIO_DDC1_A): in offset_to_id()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn32/
H A Dhw_translate_dcn32.c27 * Pre-requisites: headers required by header of this unit
52 #undef REG
53 #define REG(reg_name)\ macro
54 BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name
64 uint32_t offset, in offset_to_id() argument
69 switch (offset) { in offset_to_id()
71 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
98 case REG(DC_GPIO_HPD_A): in offset_to_id()
121 /* REG(DC_GPIO_GENLK_MASK */ in offset_to_id()
122 case REG(DC_GPIO_GENLK_A): in offset_to_id()
[all …]
/linux/io_uring/
H A Dtctx.c1 // SPDX-License-Identifier: GPL-2.0
22 mutex_lock(&ctx->uring_lock); in io_init_wq_offload()
23 hash = ctx->hash_map; in io_init_wq_offload()
27 mutex_unlock(&ctx->uring_lock); in io_init_wq_offload()
28 return ERR_PTR(-ENOMEM); in io_init_wq_offload()
30 refcount_set(&hash->refs, 1); in io_init_wq_offload()
31 init_waitqueue_head(&hash->wait); in io_init_wq_offload()
32 ctx->hash_map = hash; in io_init_wq_offload()
34 mutex_unlock(&ctx->uring_lock); in io_init_wq_offload()
42 concurrency = min(ctx->sq_entries, 4 * num_online_cpus()); in io_init_wq_offload()
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/linux/drivers/gpu/drm/nouveau/nvkm/subdev/bios/
H A Dinit.c42 nvkm_printk(init->subdev, lvl, info, "0x%08x[%c]: "fmt, \
43 init->offset, init_exec(init) ? \
44 '0' + (init->nested - 1) : ' ', ##args); \
47 if (init->subdev->debug >= NV_DBG_TRACE) \
61 return (init->execute == 1) || ((init->execute & 5) == 5); in init_exec()
67 if (exec) init->execute &= 0xfd; in init_exec_set()
68 else init->execute |= 0x02; in init_exec_set()
74 init->execute ^= 0x02; in init_exec_inv()
80 if (exec) init->execute |= 0x04; in init_exec_force()
81 else init->execute &= 0xfb; in init_exec_force()
[all …]
/linux/drivers/net/ethernet/mscc/
H A Docelot_io.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
13 int __ocelot_bulk_read_ix(struct ocelot *ocelot, enum ocelot_reg reg, in __ocelot_bulk_read_ix() argument
14 u32 offset, void *buf, int count) in __ocelot_bulk_read_ix() argument
19 ocelot_reg_to_target_addr(ocelot, reg, &target, &addr); in __ocelot_bulk_read_ix()
22 return regmap_bulk_read(ocelot->targets[target], addr + offset, in __ocelot_bulk_read_ix()
27 u32 __ocelot_read_ix(struct ocelot *ocelot, enum ocelot_reg reg, u32 offset) in __ocelot_read_ix() argument
32 ocelot_reg_to_target_addr(ocelot, reg, &target, &addr); in __ocelot_read_ix()
35 regmap_read(ocelot->targets[target], addr + offset, &val); in __ocelot_read_ix()
40 void __ocelot_write_ix(struct ocelot *ocelot, u32 val, enum ocelot_reg reg, in __ocelot_write_ix() argument
41 u32 offset) in __ocelot_write_ix() argument
[all …]
/linux/drivers/gpu/drm/amd/include/
H A Dcgs_common.h32 * enum cgs_ind_reg - Indirect register spaces
45 * enum cgs_ucode_id - Firmware types for different IPs
65 * struct cgs_firmware_info - Firmware information
84 * cgs_read_register() - Read an MMIO register
86 * @offset: register offset
90 typedef uint32_t (*cgs_read_register_t)(struct cgs_device *cgs_device, unsigned offset);
93 * cgs_write_register() - Write an MMIO register
95 * @offset: register offset
98 typedef void (*cgs_write_register_t)(struct cgs_device *cgs_device, unsigned offset,
102 * cgs_read_ind_register() - Read an indirect register
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/linux/drivers/gpu/drm/amd/display/dc/mpc/dcn32/
H A Ddcn32_mpc.c35 #define REG(reg)\ macro
36 mpc30->mpc_regs->reg
39 mpc30->base.ctx
43 mpc30->mpc_shift->field_name, mpc30->mpc_mask->field_name
53 if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) { in mpc32_mpc_init()
54 …if (mpc30->mpc_mask->MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE && mpc30->mpc_mask->MPCC_MCM_3DLUT_MEM_LOW_P… in mpc32_mpc_init()
55 for (mpcc_id = 0; mpcc_id < mpc30->num_mpcc; mpcc_id++) { in mpc32_mpc_init()
61 if (mpc30->mpc_mask->MPCC_OGAM_MEM_LOW_PWR_MODE) { in mpc32_mpc_init()
62 for (mpcc_id = 0; mpcc_id < mpc30->num_mpcc; mpcc_id++) in mpc32_mpc_init()
77 if (mpc->ctx->dc->debug.enable_mem_low_power.bits.cm) { in mpc32_power_on_blnd_lut()
[all …]
/linux/drivers/reset/
H A Dreset-eyeq.c1 // SPDX-License-Identifier: GPL-2.0-only
10 * (see enum eqr_domain_type), with a valid offset mask (up to 32 resets per
13 * Domain types define expected behavior: one-register-per-reset,
14 * one-bit-per-reset, status detection method, busywait duration, etc.
16 * We use eqr_ as prefix, as-in "EyeQ Reset", but way shorter.
54 * 4. UART1 5. I2C0 6. I2C1 7. -hole-
65 * - PMA: Programmable Macro Array
66 * - MPC: Multi-threaded Processing Clusters
67 * - VMP: Vector Microcode Processors
89 #include <linux/reset-controller.h>
[all …]
/linux/net/netfilter/
H A Dnft_payload.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2008-2009 Patrick McHardy <kaber@trash.net>
19 /* For layer 4 checksum field offset. */
34 veth->h_vlan_proto = skb->vlan_proto; in nft_payload_rebuild_vlan_hdr()
35 veth->h_vlan_TCI = htons(skb_vlan_tag_get(skb)); in nft_payload_rebuild_vlan_hdr()
36 veth->h_vlan_encapsulated_proto = skb->protocol; in nft_payload_rebuild_vlan_hdr()
43 nft_payload_copy_vlan(u32 *d, const struct sk_buff *skb, u8 offset, u8 len) in nft_payload_copy_vlan() argument
45 int mac_off = skb_mac_header(skb) - skb->data; in nft_payload_copy_vlan()
50 if (offset < VLAN_ETH_HLEN) { in nft_payload_copy_vlan()
56 if (offset + len > VLAN_ETH_HLEN) in nft_payload_copy_vlan()
[all …]
/linux/tools/perf/util/
H A Dannotate-data.c1 /* SPDX-License-Identifier: GPL-2.0 */
14 #include "annotate-data.h"
18 #include "dwarf-regs.h"
83 static void pr_debug_location(Dwarf_Die *die, u64 pc, int reg) in pr_debug_location() argument
98 if (reg != DWARF_REG_PC && end <= pc) in pr_debug_location()
100 if (reg != DWARF_REG_PC && start > pc) in pr_debug_location()
104 switch (ops->atom) { in pr_debug_location()
106 pr_info("reg%d\n", ops->atom - DW_OP_reg0); in pr_debug_location()
109 pr_info("base=reg%d, offset=%#lx\n", in pr_debug_location()
110 ops->atom - DW_OP_breg0, (long)ops->number); in pr_debug_location()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/mpc/dcn30/
H A Ddcn30_mpc.c33 #define REG(reg)\ macro
34 mpc30->mpc_regs->reg
37 mpc30->base.ctx
41 mpc30->mpc_shift->field_name, mpc30->mpc_mask->field_name
55 if (REG(MUX[opp_id])) in mpc3_mpc_init()
71 if (mpcc_id < MAX_OPP && REG(MUX[mpcc_id])) in mpc3_mpc_init_single_inst()
166 /* Wait for memory to be powered on - we won't be able to write to it otherwise. */ in mpc3_power_on_ogam_lut()
186 struct dcn3_xfer_func_reg *reg) in mpc3_ogam_get_reg_field() argument
190 reg->shifts.field_region_start_base = mpc30->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B; in mpc3_ogam_get_reg_field()
191 reg->masks.field_region_start_base = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B; in mpc3_ogam_get_reg_field()
[all …]
/linux/arch/mips/boot/dts/mti/
H A Dsead3.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/mips-gic.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
13 compatible = "mti,sead-3";
14 model = "MIPS SEAD-3";
17 stdout-path = "serial1:115200";
33 reg = <0x0 0x08000000>;
36 cpu_intc: interrupt-controller {
[all …]
/linux/drivers/net/dsa/mv88e6xxx/
H A Dglobal2.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
19 int mv88e6xxx_g2_read(struct mv88e6xxx_chip *chip, int reg, u16 *val) in mv88e6xxx_g2_read() argument
21 return mv88e6xxx_read(chip, chip->info->global2_addr, reg, val); in mv88e6xxx_g2_read()
24 int mv88e6xxx_g2_write(struct mv88e6xxx_chip *chip, int reg, u16 val) in mv88e6xxx_g2_write() argument
26 return mv88e6xxx_write(chip, chip->info->global2_addr, reg, val); in mv88e6xxx_g2_write()
29 int mv88e6xxx_g2_wait_bit(struct mv88e6xxx_chip *chip, int reg, int in mv88e6xxx_g2_wait_bit() argument
32 return mv88e6xxx_wait_bit(chip, chip->info->global2_addr, reg, in mv88e6xxx_g2_wait_bit()
36 /* Offset 0x00: Interrupt Source Register */
44 /* Offset 0x01: Interrupt Mask Register */
[all …]

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