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/linux/drivers/net/ethernet/intel/e1000/
H A De1000_osdep.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2006 Intel Corporation. */
22 #define GBE_CONFIG_FLASH_WRITE(base, offset, count, data) \ argument
23 (iowrite16_rep(base + offset, data, count))
25 #define GBE_CONFIG_FLASH_READ(base, offset, count, data) \ argument
26 (ioread16_rep(base + (offset << 1), data, count))
28 #define er32(reg) \ argument
29 (readl(hw->hw_addr + ((hw->mac_type >= e1000_82543) \
30 ? E1000_##reg : E1000_82542_##reg)))
32 #define ew32(reg, value) \ argument
[all …]
/linux/drivers/gpu/drm/amd/display/dc/gpio/dce120/
H A Dhw_translate_dce120.c2 * Copyright 2013-15 Advanced Micro Devices, Inc.
27 * Pre-requisites: headers required by header of this unit
51 #define REG(reg_name)\ macro
62 uint32_t offset, in offset_to_id() argument
67 switch (offset) { in offset_to_id()
69 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
99 case REG(DC_GPIO_HPD_A): in offset_to_id()
126 case REG(DC_GPIO_SYNCA_A): in offset_to_id()
140 /* REG(DC_GPIO_GENLK_MASK */ in offset_to_id()
141 case REG(DC_GPIO_GENLK_A): in offset_to_id()
[all …]
/linux/drivers/gpio/
H A Dgpio-palmas.c1 // SPDX-License-Identifier: GPL-2.0-only
26 static int palmas_gpio_get(struct gpio_chip *gc, unsigned offset) in palmas_gpio_get() argument
29 struct palmas *palmas = pg->palmas; in palmas_gpio_get()
32 unsigned int reg; in palmas_gpio_get() local
33 int gpio16 = (offset/8); in palmas_gpio_get()
35 offset %= 8; in palmas_gpio_get()
36 reg = (gpio16) ? PALMAS_GPIO_DATA_DIR2 : PALMAS_GPIO_DATA_DIR; in palmas_gpio_get()
38 ret = palmas_read(palmas, PALMAS_GPIO_BASE, reg, &val); in palmas_gpio_get()
40 dev_err(gc->parent, "Reg 0x%02x read failed, %d\n", reg, ret); in palmas_gpio_get()
44 if (val & BIT(offset)) in palmas_gpio_get()
[all …]
H A Dgpio-pmic-eic-sprd.c1 // SPDX-License-Identifier: GPL-2.0
33 #define SPRD_PMIC_EIC_BIT(x) ((x) & (SPRD_PMIC_EIC_PER_BANK_NR - 1))
48 * struct sprd_pmic_eic - PMIC EIC controller
51 * @offset: the EIC controller's offset address of the PMIC.
52 * @reg: the array to cache the EIC registers.
59 u32 offset; member
60 u8 reg[CACHE_NR_REGS]; member
65 static void sprd_pmic_eic_update(struct gpio_chip *chip, unsigned int offset, in sprd_pmic_eic_update() argument
66 u16 reg, unsigned int val) in sprd_pmic_eic_update() argument
69 u32 shift = SPRD_PMIC_EIC_BIT(offset); in sprd_pmic_eic_update()
[all …]
H A Dgpio-xra1403.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * GPIO driver for EXAR XRA1403 16-bit GPIO expander
23 #define XRA_PUR 0x08 /* Input Internal Pull-up Resistor Enable/Disable */
25 #define XRA_TSCR 0x0C /* Output Three-State Control */
45 static unsigned int to_reg(unsigned int reg, unsigned int offset) in to_reg() argument
47 return reg + (offset > 7); in to_reg()
50 static int xra1403_direction_input(struct gpio_chip *chip, unsigned int offset) in xra1403_direction_input() argument
54 return regmap_update_bits(xra->regmap, to_reg(XRA_GCR, offset), in xra1403_direction_input()
55 BIT(offset % 8), BIT(offset % 8)); in xra1403_direction_input()
58 static int xra1403_direction_output(struct gpio_chip *chip, unsigned int offset, in xra1403_direction_output() argument
[all …]
H A Dgpio-npcm-sgpio.c1 // SPDX-License-Identifier: GPL-2.0
139 const enum npcm_sgpio_reg reg) in bank_reg() argument
141 switch (reg) { in bank_reg()
143 return gpio->base + bank->rdata_reg; in bank_reg()
145 return gpio->base + bank->wdata_reg; in bank_reg()
147 return gpio->base + bank->event_config; in bank_reg()
149 return gpio->base + bank->event_status; in bank_reg()
152 dev_WARN(gpio->chip.parent, "Getting here is an error condition"); in bank_reg()
157 static const struct npcm_sgpio_bank *offset_to_bank(unsigned int offset) in offset_to_bank() argument
159 unsigned int bank = GPIO_BANK(offset); in offset_to_bank()
[all …]
H A Dgpio-logicvc.c1 // SPDX-License-Identifier: GPL-2.0+
29 static void logicvc_gpio_offset(struct logicvc_gpio *logicvc, unsigned offset, in logicvc_gpio_offset() argument
30 unsigned int *reg, unsigned int *bit) in logicvc_gpio_offset() argument
32 if (offset >= LOGICVC_CTRL_GPIO_BITS) { in logicvc_gpio_offset()
33 *reg = LOGICVC_POWER_CTRL_REG; in logicvc_gpio_offset()
35 /* To the (virtual) power ctrl offset. */ in logicvc_gpio_offset()
36 offset -= LOGICVC_CTRL_GPIO_BITS; in logicvc_gpio_offset()
37 /* To the actual bit offset in reg. */ in logicvc_gpio_offset()
38 offset += LOGICVC_POWER_CTRL_GPIO_SHIFT; in logicvc_gpio_offset()
40 *reg = LOGICVC_CTRL_REG; in logicvc_gpio_offset()
[all …]
/linux/tools/perf/util/
H A Dannotate-data.c1 /* SPDX-License-Identifier: GPL-2.0 */
14 #include "annotate-data.h"
18 #include "dwarf-regs.h"
88 static void pr_debug_location(Dwarf_Die *die, u64 pc, int reg) in pr_debug_location()
103 if (reg != DWARF_REG_PC && end <= pc) in pr_debug_location()
105 if (reg != DWARF_REG_PC && start > pc) in pr_debug_location()
109 switch (ops->atom) { in pr_debug_location()
111 pr_info("reg in pr_debug_location()
87 pr_debug_location(Dwarf_Die * die,u64 pc,int reg) pr_debug_location() argument
158 has_reg_type(struct type_state * state,int reg) has_reg_type() argument
322 fill_member_name(char * buf,size_t sz,struct annotated_member * m,int offset,bool first) fill_member_name() argument
518 check_variable(struct data_loc_info * dloc,Dwarf_Die * var_die,Dwarf_Die * type_die,int reg,int offset,bool is_fbreg) check_variable() argument
519 check_variable(struct data_loc_info * dloc,Dwarf_Die * var_die,Dwarf_Die * type_die,int reg,int offset,bool is_fbreg) check_variable() argument
564 find_stack_state(struct type_state * state,int offset) find_stack_state() argument
579 set_stack_state(struct type_state_stack * stack,int offset,u8 kind,Dwarf_Die * type_die,int ptr_offset) set_stack_state() argument
617 findnew_stack_state(struct type_state * state,int offset,u8 kind,Dwarf_Die * type_die,int ptr_offset) findnew_stack_state() argument
800 int offset; get_global_var_type() local
883 int offset = var->offset; update_var_state() local
911 struct type_state_reg *reg; update_var_state() local
1094 int reg = dloc->op->reg1; check_matching_type() local
1095 int offset = dloc->op->offset; check_matching_type() local
1463 int offset = dloc->op->offset; find_data_type_block() local
1501 int reg, offset = loc->offset; find_data_type_die() local
1795 annotated_data_type__update_samples(struct annotated_data_type * adt,struct evsel * evsel,int offset,int nr_samples,u64 period) annotated_data_type__update_samples() argument
[all...]
/linux/drivers/net/ethernet/mscc/
H A Docelot_io.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
13 int __ocelot_bulk_read_ix(struct ocelot *ocelot, enum ocelot_reg reg, in __ocelot_bulk_read_ix() argument
14 u32 offset, void *buf, int count) in __ocelot_bulk_read_ix() argument
19 ocelot_reg_to_target_addr(ocelot, reg, &target, &addr); in __ocelot_bulk_read_ix()
22 return regmap_bulk_read(ocelot->targets[target], addr + offset, in __ocelot_bulk_read_ix()
27 u32 __ocelot_read_ix(struct ocelot *ocelot, enum ocelot_reg reg, u32 offset) in __ocelot_read_ix() argument
32 ocelot_reg_to_target_addr(ocelot, reg, &target, &addr); in __ocelot_read_ix()
35 regmap_read(ocelot->targets[target], addr + offset, &val); in __ocelot_read_ix()
40 void __ocelot_write_ix(struct ocelot *ocelot, u32 val, enum ocelot_reg reg, in __ocelot_write_ix() argument
41 u32 offset) in __ocelot_write_ix() argument
[all …]
/linux/drivers/reset/
H A Dreset-eyeq.c1 // SPDX-License-Identifier: GPL-2.0-only
11 * (see enum eqr_domain_type), with a valid offset mask (up to 32 resets per
14 * Domain types define expected behavior: one-register-per-reset,
15 * one-bit-per-reset, status detection method, busywait duration, etc.
17 * We use eqr_ as prefix, as-in "EyeQ Reset", but way shorter.
67 * 4. UART1 5. I2C0 6. I2C1 7. -hole-
115 * - PMA: Programmable Macro Array
116 * - MPC: Multi-threaded Processing Clusters
117 * - VMP: Vector Microcode Processors
138 #include <linux/reset-controller.h>
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/bios/
H A Dinit.c42 nvkm_printk(init->subdev, lvl, info, "0x%08x[%c]: "fmt, \
43 init->offset, init_exec(init) ? \
44 '0' + (init->nested - 1) : ' ', ##args); \
47 if (init->subdev->debug >= NV_DBG_TRACE) \
61 return (init->execute == 1) || ((init->execute & 5) == 5); in init_exec()
67 if (exec) init->execute &= 0xfd; in init_exec_set()
68 else init->execute |= 0x02; in init_exec_set()
74 init->execute ^= 0x02; in init_exec_inv()
80 if (exec) init->execute |= 0x04; in init_exec_force()
81 else init->execute &= 0xfb; in init_exec_force()
[all …]
/linux/drivers/gpu/drm/amd/include/
H A Dcgs_common.h32 * enum cgs_ind_reg - Indirect register spaces
45 * enum cgs_ucode_id - Firmware types for different IPs
65 * struct cgs_firmware_info - Firmware information
84 * cgs_read_register() - Read an MMIO register
86 * @offset: register offset
90 typedef uint32_t (*cgs_read_register_t)(struct cgs_device *cgs_device, unsigned offset);
93 * cgs_write_register() - Write an MMIO register
95 * @offset: register offset
98 typedef void (*cgs_write_register_t)(struct cgs_device *cgs_device, unsigned offset,
102 * cgs_read_ind_register() - Read an indirect register
[all …]
/linux/drivers/net/ethernet/stmicro/stmmac/
H A Dstmmac_fpe.c1 // SPDX-License-Identifier: GPL-2.0-only
31 const u32 mac_fpe_reg; /* offset of MAC_FPE_CTRL_STS */
32 const u32 mtl_fpe_reg; /* offset of MTL_FPE_CTRL_STS */
33 const u32 rxq_ctrl1_reg; /* offset of MAC_RxQ_Ctrl1 */
35 const u32 int_en_reg; /* offset of MAC_Interrupt_Enable */
41 return priv->dma_cap.fpesel && priv->fpe_cfg.reg && in stmmac_fpe_supported()
42 priv->hw->mac->fpe_map_preemption_class; in stmmac_fpe_supported()
49 const struct stmmac_fpe_reg *reg = cfg->reg; in stmmac_fpe_configure_tx() local
50 u32 num_rxq = priv->plat->rx_queues_to_use; in stmmac_fpe_configure_tx()
51 void __iomem *ioaddr = priv->ioaddr; in stmmac_fpe_configure_tx()
[all …]
/linux/arch/mips/boot/dts/mti/
H A Dsead3.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/mips-gic.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
13 compatible = "mti,sead-3";
14 model = "MIPS SEAD-3";
17 stdout-path = "serial1:115200";
33 reg = <0x0 0x08000000>;
36 cpu_intc: interrupt-controller {
[all …]
/linux/drivers/net/dsa/
H A Dbcm_sf2_cfp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
45 /* End of L2, byte offset 12, src IP[0:15] */
47 /* End of L2, byte offset 14, src IP[16:31] */
49 /* End of L2, byte offset 16, dst IP[0:15] */
51 /* End of L2, byte offset 18, dst IP[16:31] */
53 /* End of L3, byte offset
161 u32 offset = layout->udfs[slice_num].base_offset; bcm_sf2_cfp_udf_set() local
172 u32 reg; bcm_sf2_cfp_op() local
196 u32 reg; bcm_sf2_cfp_rule_addr_set() local
220 u32 reg; bcm_sf2_cfp_act_pol_set() local
270 u32 reg, offset; bcm_sf2_cfp_slice_ipv4() local
361 u32 reg; bcm_sf2_cfp_ipv4_rule_set() local
488 u32 reg, tmp, val, offset; bcm_sf2_cfp_slice_ipv6() local
642 u32 reg; bcm_sf2_cfp_ipv6_rule_set() local
974 u32 reg; bcm_sf2_cfp_rule_del_one() local
1192 u32 reg; bcm_sf2_cfp_rst() local
1229 u32 reg; bcm_sf2_cfp_resume() local
1261 unsigned int offset; global() member
[all...]
/linux/drivers/pinctrl/
H A Dpinctrl-stmfx.c1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for STMicroelectronics Multi-Function eXpander (STMFX) GPIO expander
20 #include "pinctrl-utils.h"
48 #define get_reg(offset) ((offset) / NR_GPIOS_PER_REG) argument
49 #define get_shift(offset) ((offset) % NR_GPIOS_PER_REG) argument
50 #define get_mask(offset) (BIT(get_shift(offset))) argument
54 * Pins availability is managed thanks to gpio-ranges property.
105 static int stmfx_gpio_get(struct gpio_chip *gc, unsigned int offset) in stmfx_gpio_get() argument
108 u32 reg = STMFX_REG_GPIO_STATE + get_reg(offset); in stmfx_gpio_get() local
109 u32 mask = get_mask(offset); in stmfx_gpio_get()
[all …]
/linux/drivers/net/wireless/ralink/rt2x00/
H A Drt2x00usb.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
62 * enum rt2x00usb_mode_offset: Device modes offset.
76 * rt2x00usb_vendor_request - Send register command to device
80 * @offset: Register offset to perform action on
93 const u16 offset, const u16 value,
98 * rt2x00usb_vendor_request_buff - Send register command to device (buffered)
102 * @offset: Register offset to perform action on
116 const u16 offset, void *buffer,
120 * rt2x00usb_vendor_request_buff - Send register command to device (buffered)
[all …]
/linux/drivers/net/dsa/mv88e6xxx/
H A Dglobal2.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
19 int mv88e6xxx_g2_read(struct mv88e6xxx_chip *chip, int reg, u16 *val) in mv88e6xxx_g2_read() argument
21 return mv88e6xxx_read(chip, chip->info->global2_addr, reg, val); in mv88e6xxx_g2_read()
24 int mv88e6xxx_g2_write(struct mv88e6xxx_chip *chip, int reg, u16 val) in mv88e6xxx_g2_write() argument
26 return mv88e6xxx_write(chip, chip->info->global2_addr, reg, val); in mv88e6xxx_g2_write()
29 int mv88e6xxx_g2_wait_bit(struct mv88e6xxx_chip *chip, int reg, int in mv88e6xxx_g2_wait_bit() argument
32 return mv88e6xxx_wait_bit(chip, chip->info->global2_addr, reg, in mv88e6xxx_g2_wait_bit()
36 /* Offset 0x00: Interrupt Source Register */
44 /* Offset 0x01: Interrupt Mask Register */
[all …]
/linux/io_uring/
H A Dtctx.c1 // SPDX-License-Identifier: GPL-2.0
23 mutex_lock(&ctx->uring_lock); in io_init_wq_offload()
24 hash = ctx->hash_map; in io_init_wq_offload()
28 mutex_unlock(&ctx->uring_lock); in io_init_wq_offload()
29 return ERR_PTR(-ENOMEM); in io_init_wq_offload()
31 refcount_set(&hash->refs, 1); in io_init_wq_offload()
32 init_waitqueue_head(&hash->wait); in io_init_wq_offload()
33 ctx->hash_map = hash; in io_init_wq_offload()
35 mutex_unlock(&ctx->uring_lock); in io_init_wq_offload()
41 concurrency = min(ctx->sq_entries, 4 * num_online_cpus()); in io_init_wq_offload()
[all …]
/linux/tools/perf/util/annotate-arch/
H A Dannotate-x86.c1 // SPDX-License-Identifier: GPL-2.0
7 #include "../annotate-data.h"
17 * This table is searched twice - one for exact match and another for
142 if (arch->family >= 0x15 && (strstarts(ins1, "test") || in amd__ins_is_fused()
148 if (arch->family >= 0x19 && (strstarts(ins1, "add") || in amd__ins_is_fused()
161 if (arch->family != 6 || arch->model < 0x1e || strstr(ins2, "jmp")) in intel__ins_is_fused()
164 if (arch->mode in intel__ins_is_fused()
258 int offset; update_insn_state_x86() local
373 int offset = src->offset - fboff; update_insn_state_x86() local
477 int offset; update_insn_state_x86() local
559 int offset = src->offset - fboff; update_insn_state_x86() local
624 int offset; update_insn_state_x86() local
649 int offset; update_insn_state_x86() local
706 int offset; update_insn_state_x86() local
736 int offset = dst->offset - fboff; update_insn_state_x86() local
[all...]
/linux/drivers/pinctrl/sunplus/
H A Dsppctl.c1 // SPDX-License-Identifier: GPL-2.0
21 #include <linux/pinctrl/pinconf-generic.h>
24 #include <dt-bindings/pinctrl/sppctl-sp7021.h>
27 #include "../pinctrl-utils.h"
41 return readl(spp_gchip->first_base + SPPCTL_GPIO_OFF_FIRST + off); in sppctl_first_readl()
46 writel(val, spp_gchip->first_base + SPPCTL_GPIO_OFF_FIRST + off); in sppctl_first_writel()
51 return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_MASTER + off); in sppctl_gpio_master_readl()
57 writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_MASTER + off); in sppctl_gpio_master_writel()
62 return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OE + off); in sppctl_gpio_oe_readl()
67 writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OE + off); in sppctl_gpio_oe_writel()
[all …]
/linux/drivers/net/ethernet/intel/i40e/
H A Di40e_dcb.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2013 - 2021 Intel Corporation. */
19 u32 reg; in i40e_get_dcbx_status() local
22 return -EINVAL; in i40e_get_dcbx_status()
24 reg = rd32(hw, I40E_PRTDCB_GENS); in i40e_get_dcbx_status()
25 *status = FIELD_GET(I40E_PRTDCB_GENS_DCBX_STATUS_MASK, reg); in i40e_get_dcbx_status()
41 u8 *buf = tlv->tlvinfo; in i40e_parse_ieee_etscfg_tlv()
42 u16 offset = 0; in i40e_parse_ieee_etscfg_tlv() local
47 * -------------------------- in i40e_parse_ieee_etscfg_tlv()
48 * |will-|CBS | Re- | Max | in i40e_parse_ieee_etscfg_tlv()
[all …]
/linux/Documentation/devicetree/bindings/arm/hisilicon/controller/
H A Dsysctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wei Xu <xuwei5@hisilicon.com>
19 offset. In addition, the HiP01 system controller has some specific control
23 Hisilicon system controller --> hisilicon,sysctrl
24 HiP01 system controller --> hisilicon,hip01-sysctrl
25 Hi6220 system controller --> hisilicon,hi6220-sysctrl
26 Hi3519 system controller --> hisilicon,hi3519-sysctrl
29 - if:
[all …]
/linux/drivers/pinctrl/spear/
H A Dpinctrl-plgpio.c28 #define REG_OFFSET(base, reg, pin) (base + reg + (pin / MAX_GPIO_PER_REG) \ argument
59 * p2o: function ptr for pin to offset conversion. This is required only for
60 * machines where mapping b/w pin and offset is not 1-to-1.
61 * o2p: function ptr for offset to pin conversion. This is required only for
62 * machines where mapping b/w pin and offset is not 1-to-1.
73 int (*o2p)(int offset); /* offset_to_pin */
82 static inline u32 is_plgpio_set(struct regmap *regmap, u32 pin, u32 reg) in is_plgpio_set() argument
84 u32 offset = PIN_OFFSET(pin); in is_plgpio_set() local
85 u32 reg_off = REG_OFFSET(0, reg, pin); in is_plgpio_set()
90 return !!(val & (1 << offset)); in is_plgpio_set()
[all …]
/linux/drivers/pinctrl/microchip/
H A Dpinctrl-mpfs-mssio.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/pinctrl/pinconf-generic.h>
17 #include "../pinctrl-utils.h"
100 return -EINVAL; in mpfs_pinctrl_get_drive_strength_ma()
108 return -EINVAL; in mpfs_pinctrl_get_drive_strength_val()
114 return mpfs_pinctrl_drive_strengths[num - 1].val; in mpfs_pinctrl_get_drive_strength_val()
125 return -EINVAL; in mpfs_pinctrl_get_bank_voltage_uv()
136 return -EINVAL; in mpfs_pinctrl_get_bank_voltage_val()
144 regmap_read(pctrl->sysreg_regmap, MPFS_PINCTRL_MSSIO_BANK4_CFG_CR, &val); in mpfs_pinctrl_pin_to_bank_voltage()
146 regmap_read(pctrl->sysreg_regmap, MPFS_PINCTRL_MSSIO_BANK2_CFG_CR, &val); in mpfs_pinctrl_pin_to_bank_voltage()
[all …]

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