1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
13 int __ocelot_bulk_read_ix(struct ocelot *ocelot, enum ocelot_reg reg,  in __ocelot_bulk_read_ix()  argument
14 			  u32 offset, void *buf, int count)  in __ocelot_bulk_read_ix()  argument
19 	ocelot_reg_to_target_addr(ocelot, reg, &target, &addr);  in __ocelot_bulk_read_ix()
22 	return regmap_bulk_read(ocelot->targets[target], addr + offset,  in __ocelot_bulk_read_ix()
27 u32 __ocelot_read_ix(struct ocelot *ocelot, enum ocelot_reg reg, u32 offset)  in __ocelot_read_ix()  argument
32 	ocelot_reg_to_target_addr(ocelot, reg, &target, &addr);  in __ocelot_read_ix()
35 	regmap_read(ocelot->targets[target], addr + offset, &val);  in __ocelot_read_ix()
40 void __ocelot_write_ix(struct ocelot *ocelot, u32 val, enum ocelot_reg reg,  in __ocelot_write_ix()  argument
41 		       u32 offset)  in __ocelot_write_ix()  argument
46 	ocelot_reg_to_target_addr(ocelot, reg, &target, &addr);  in __ocelot_write_ix()
49 	regmap_write(ocelot->targets[target], addr + offset, val);  in __ocelot_write_ix()
54 		     enum ocelot_reg reg, u32 offset)  in __ocelot_rmw_ix()  argument
59 	ocelot_reg_to_target_addr(ocelot, reg, &target, &addr);  in __ocelot_rmw_ix()
62 	regmap_update_bits(ocelot->targets[target], addr + offset, mask, val);  in __ocelot_rmw_ix()
66 u32 ocelot_port_readl(struct ocelot_port *port, enum ocelot_reg reg)  in ocelot_port_readl()  argument
68 	struct ocelot *ocelot = port->ocelot;  in ocelot_port_readl()
69 	u16 target = reg >> TARGET_OFFSET;  in ocelot_port_readl()
74 	regmap_read(port->target, ocelot->map[target][reg & REG_MASK], &val);  in ocelot_port_readl()
79 void ocelot_port_writel(struct ocelot_port *port, u32 val, enum ocelot_reg reg)  in ocelot_port_writel()  argument
81 	struct ocelot *ocelot = port->ocelot;  in ocelot_port_writel()
82 	u16 target = reg >> TARGET_OFFSET;  in ocelot_port_writel()
86 	regmap_write(port->target, ocelot->map[target][reg & REG_MASK], val);  in ocelot_port_writel()
91 		      enum ocelot_reg reg)  in ocelot_port_rmwl()  argument
93 	u32 cur = ocelot_port_readl(port, reg);  in ocelot_port_rmwl()
95 	ocelot_port_writel(port, (cur & (~mask)) | val, reg);  in ocelot_port_rmwl()
100 			    u32 reg, u32 offset)  in __ocelot_target_read_ix()  argument
104 	regmap_read(ocelot->targets[target],  in __ocelot_target_read_ix()
105 		    ocelot->map[target][reg] + offset, &val);  in __ocelot_target_read_ix()
110 			      u32 val, u32 reg, u32 offset)  in __ocelot_target_write_ix()  argument
112 	regmap_write(ocelot->targets[target],  in __ocelot_target_write_ix()
113 		     ocelot->map[target][reg] + offset, val);  in __ocelot_target_write_ix()
124 		u32 reg = regfields[i].reg;  in ocelot_regfields_init()  local
126 		if (!reg)  in ocelot_regfields_init()
129 		target = regfields[i].reg >> TARGET_OFFSET;  in ocelot_regfields_init()
131 		regfield.reg = ocelot->map[target][reg & REG_MASK];  in ocelot_regfields_init()
137 		ocelot->regfields[i] =  in ocelot_regfields_init()
138 		devm_regmap_field_alloc(ocelot->dev,  in ocelot_regfields_init()
139 					ocelot->targets[target],  in ocelot_regfields_init()
142 		if (IS_ERR(ocelot->regfields[i]))  in ocelot_regfields_init()
143 			return PTR_ERR(ocelot->regfields[i]);  in ocelot_regfields_init()
160 	regs = devm_ioremap_resource(ocelot->dev, res);  in ocelot_regmap_init()
164 	ocelot_regmap_config.name = res->name;  in ocelot_regmap_init()
166 	return devm_regmap_init_mmio(ocelot->dev, regs, &ocelot_regmap_config);  in ocelot_regmap_init()