1 // SPDX-License-Identifier: GPL-2.0
33 #define SPRD_PMIC_EIC_BIT(x)		((x) & (SPRD_PMIC_EIC_PER_BANK_NR - 1))
48  * struct sprd_pmic_eic - PMIC EIC controller
51  * @offset: the EIC controller's offset address of the PMIC.
52  * @reg: the array to cache the EIC registers.
59 	u32 offset;  member
60 	u8 reg[CACHE_NR_REGS];  member
65 static void sprd_pmic_eic_update(struct gpio_chip *chip, unsigned int offset,  in sprd_pmic_eic_update()  argument
66 				 u16 reg, unsigned int val)  in sprd_pmic_eic_update()  argument
69 	u32 shift = SPRD_PMIC_EIC_BIT(offset);  in sprd_pmic_eic_update()
71 	regmap_update_bits(pmic_eic->map, pmic_eic->offset + reg,  in sprd_pmic_eic_update()
75 static int sprd_pmic_eic_read(struct gpio_chip *chip, unsigned int offset,  in sprd_pmic_eic_read()  argument
76 			      u16 reg)  in sprd_pmic_eic_read()  argument
82 	ret = regmap_read(pmic_eic->map, pmic_eic->offset + reg, &value);  in sprd_pmic_eic_read()
86 	return !!(value & BIT(SPRD_PMIC_EIC_BIT(offset)));  in sprd_pmic_eic_read()
89 static int sprd_pmic_eic_request(struct gpio_chip *chip, unsigned int offset)  in sprd_pmic_eic_request()  argument
91 	sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_DMSK, 1);  in sprd_pmic_eic_request()
95 static void sprd_pmic_eic_free(struct gpio_chip *chip, unsigned int offset)  in sprd_pmic_eic_free()  argument
97 	sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_DMSK, 0);  in sprd_pmic_eic_free()
100 static int sprd_pmic_eic_get(struct gpio_chip *chip, unsigned int offset)  in sprd_pmic_eic_get()  argument
102 	return sprd_pmic_eic_read(chip, offset, SPRD_PMIC_EIC_DATA);  in sprd_pmic_eic_get()
106 					 unsigned int offset)  in sprd_pmic_eic_direction_input()  argument
112 static void sprd_pmic_eic_set(struct gpio_chip *chip, unsigned int offset,  in sprd_pmic_eic_set()  argument
119 				      unsigned int offset,  in sprd_pmic_eic_set_debounce()  argument
123 	u32 reg, value;  in sprd_pmic_eic_set_debounce()  local
126 	reg = SPRD_PMIC_EIC_CTRL0 + SPRD_PMIC_EIC_BIT(offset) * 0x4;  in sprd_pmic_eic_set_debounce()
127 	ret = regmap_read(pmic_eic->map, pmic_eic->offset + reg, &value);  in sprd_pmic_eic_set_debounce()
133 	return regmap_write(pmic_eic->map, pmic_eic->offset + reg, value);  in sprd_pmic_eic_set_debounce()
136 static int sprd_pmic_eic_set_config(struct gpio_chip *chip, unsigned int offset,  in sprd_pmic_eic_set_config()  argument
143 		return sprd_pmic_eic_set_debounce(chip, offset, arg);  in sprd_pmic_eic_set_config()
145 	return -ENOTSUPP;  in sprd_pmic_eic_set_config()
152 	u32 offset = irqd_to_hwirq(data);  in sprd_pmic_eic_irq_mask()  local
154 	pmic_eic->reg[REG_IE] &= ~BIT(offset);  in sprd_pmic_eic_irq_mask()
155 	pmic_eic->reg[REG_TRIG] &= ~BIT(offset);  in sprd_pmic_eic_irq_mask()
157 	gpiochip_disable_irq(chip, offset);  in sprd_pmic_eic_irq_mask()
164 	u32 offset = irqd_to_hwirq(data);  in sprd_pmic_eic_irq_unmask()  local
166 	gpiochip_enable_irq(chip, offset);  in sprd_pmic_eic_irq_unmask()
168 	pmic_eic->reg[REG_IE] |= BIT(offset);  in sprd_pmic_eic_irq_unmask()
169 	pmic_eic->reg[REG_TRIG] |= BIT(offset);  in sprd_pmic_eic_irq_unmask()
177 	u32 offset = irqd_to_hwirq(data);  in sprd_pmic_eic_irq_set_type()  local
181 		pmic_eic->reg[REG_IEV] |= BIT(offset);  in sprd_pmic_eic_irq_set_type()
184 		pmic_eic->reg[REG_IEV] &= ~BIT(offset);  in sprd_pmic_eic_irq_set_type()
195 		return -ENOTSUPP;  in sprd_pmic_eic_irq_set_type()
206 	mutex_lock(&pmic_eic->buslock);  in sprd_pmic_eic_bus_lock()
214 	u32 offset = irqd_to_hwirq(data);  in sprd_pmic_eic_bus_sync_unlock()  local
219 		state = sprd_pmic_eic_get(chip, offset);  in sprd_pmic_eic_bus_sync_unlock()
221 			sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 0);  in sprd_pmic_eic_bus_sync_unlock()
223 			sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 1);  in sprd_pmic_eic_bus_sync_unlock()
225 		sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV,  in sprd_pmic_eic_bus_sync_unlock()
226 				     !!(pmic_eic->reg[REG_IEV] & BIT(offset)));  in sprd_pmic_eic_bus_sync_unlock()
230 	sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IE,  in sprd_pmic_eic_bus_sync_unlock()
231 			     !!(pmic_eic->reg[REG_IE] & BIT(offset)));  in sprd_pmic_eic_bus_sync_unlock()
233 	sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_TRIG,  in sprd_pmic_eic_bus_sync_unlock()
234 			     !!(pmic_eic->reg[REG_TRIG] & BIT(offset)));  in sprd_pmic_eic_bus_sync_unlock()
236 	mutex_unlock(&pmic_eic->buslock);  in sprd_pmic_eic_bus_sync_unlock()
240 					 unsigned int irq, unsigned int offset)  in sprd_pmic_eic_toggle_trigger()  argument
248 	state = sprd_pmic_eic_get(chip, offset);  in sprd_pmic_eic_toggle_trigger()
251 		sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 0);  in sprd_pmic_eic_toggle_trigger()
253 		sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 1);  in sprd_pmic_eic_toggle_trigger()
255 	post_state = sprd_pmic_eic_get(chip, offset);  in sprd_pmic_eic_toggle_trigger()
257 		dev_warn(chip->parent, "PMIC EIC level was changed.\n");  in sprd_pmic_eic_toggle_trigger()
263 	sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IE, 1);  in sprd_pmic_eic_toggle_trigger()
265 	sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_TRIG, 1);  in sprd_pmic_eic_toggle_trigger()
271 	struct gpio_chip *chip = &pmic_eic->chip;  in sprd_pmic_eic_irq_handler()
276 	ret = regmap_read(pmic_eic->map, pmic_eic->offset + SPRD_PMIC_EIC_MIS,  in sprd_pmic_eic_irq_handler()
283 	for_each_set_bit(n, &status, chip->ngpio) {  in sprd_pmic_eic_irq_handler()
287 		girq = irq_find_mapping(chip->irq.domain, n);  in sprd_pmic_eic_irq_handler()
301 	.name			= "sprd-pmic-eic",
317 	pmic_eic = devm_kzalloc(&pdev->dev, sizeof(*pmic_eic), GFP_KERNEL);  in sprd_pmic_eic_probe()
319 		return -ENOMEM;  in sprd_pmic_eic_probe()
321 	mutex_init(&pmic_eic->buslock);  in sprd_pmic_eic_probe()
323 	pmic_eic->irq = platform_get_irq(pdev, 0);  in sprd_pmic_eic_probe()
324 	if (pmic_eic->irq < 0)  in sprd_pmic_eic_probe()
325 		return pmic_eic->irq;  in sprd_pmic_eic_probe()
327 	pmic_eic->map = dev_get_regmap(pdev->dev.parent, NULL);  in sprd_pmic_eic_probe()
328 	if (!pmic_eic->map)  in sprd_pmic_eic_probe()
329 		return -ENODEV;  in sprd_pmic_eic_probe()
331 	ret = of_property_read_u32(pdev->dev.of_node, "reg", &pmic_eic->offset);  in sprd_pmic_eic_probe()
333 		dev_err(&pdev->dev, "Failed to get PMIC EIC base address.\n");  in sprd_pmic_eic_probe()
337 	ret = devm_request_threaded_irq(&pdev->dev, pmic_eic->irq, NULL,  in sprd_pmic_eic_probe()
340 					dev_name(&pdev->dev), pmic_eic);  in sprd_pmic_eic_probe()
342 		dev_err(&pdev->dev, "Failed to request PMIC EIC IRQ.\n");  in sprd_pmic_eic_probe()
346 	pmic_eic->chip.label = dev_name(&pdev->dev);  in sprd_pmic_eic_probe()
347 	pmic_eic->chip.ngpio = SPRD_PMIC_EIC_NR;  in sprd_pmic_eic_probe()
348 	pmic_eic->chip.base = -1;  in sprd_pmic_eic_probe()
349 	pmic_eic->chip.parent = &pdev->dev;  in sprd_pmic_eic_probe()
350 	pmic_eic->chip.direction_input = sprd_pmic_eic_direction_input;  in sprd_pmic_eic_probe()
351 	pmic_eic->chip.request = sprd_pmic_eic_request;  in sprd_pmic_eic_probe()
352 	pmic_eic->chip.free = sprd_pmic_eic_free;  in sprd_pmic_eic_probe()
353 	pmic_eic->chip.set_config = sprd_pmic_eic_set_config;  in sprd_pmic_eic_probe()
354 	pmic_eic->chip.set = sprd_pmic_eic_set;  in sprd_pmic_eic_probe()
355 	pmic_eic->chip.get = sprd_pmic_eic_get;  in sprd_pmic_eic_probe()
356 	pmic_eic->chip.can_sleep = true;  in sprd_pmic_eic_probe()
358 	irq = &pmic_eic->chip.irq;  in sprd_pmic_eic_probe()
360 	irq->threaded = true;  in sprd_pmic_eic_probe()
362 	ret = devm_gpiochip_add_data(&pdev->dev, &pmic_eic->chip, pmic_eic);  in sprd_pmic_eic_probe()
364 		dev_err(&pdev->dev, "Could not register gpiochip %d.\n", ret);  in sprd_pmic_eic_probe()
372 	{ .compatible = "sprd,sc2731-eic", },
380 		.name = "sprd-pmic-eic",