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/freebsd/sys/contrib/device-tree/src/arm/st/
H A Dstm32f746.dtsi45 #include <dt-bindings/mfd/stm32f7-rcc.h>
84 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
106 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
128 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
150 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
172 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
188 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
204 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
224 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
238 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
[all …]
H A Dstm32f429.dtsi50 #include <dt-bindings/mfd/stm32f4-rcc.h>
101 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
123 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
145 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
167 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
189 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
205 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
221 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
241 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
255 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
[all …]
H A Dstm32h743.dtsi45 #include <dt-bindings/mfd/stm32h7-rcc.h>
77 clocks = <&rcc TIM5_CK>;
85 clocks = <&rcc LPTIM1_CK>;
113 resets = <&rcc STM32H7_APB1L_RESET(SPI2)>;
114 clocks = <&rcc SPI2_CK>;
125 resets = <&rcc STM32H7_APB1L_RESET(SPI3)>;
126 clocks = <&rcc SPI3_CK>;
135 clocks = <&rcc USART2_CK>;
143 clocks = <&rcc USART3_CK>;
151 clocks = <&rcc UART4_CK>;
[all …]
H A Dstm32mp151.dtsi135 clocks = <&rcc IPCC>;
140 rcc: rcc@50000000 { label
141 compatible = "st,stm32mp1-rcc", "syscon";
260 clocks = <&rcc SYSCFG>;
267 clocks = <&rcc TMPSENS>;
277 clocks = <&rcc MDMA>;
278 resets = <&rcc MDMA_R>;
289 clocks = <&rcc SDMMC1_K>;
291 resets = <&rcc SDMMC1_R>;
303 clocks = <&rcc SDMMC2_K>;
[all …]
H A Dstm32mp131.dtsi142 clocks = <&rcc TIM2_K>;
177 clocks = <&rcc TIM3_K>;
213 clocks = <&rcc TIM4_K>;
247 clocks = <&rcc TIM5_K>;
283 clocks = <&rcc TIM6_K>;
308 clocks = <&rcc TIM7_K>;
332 clocks = <&rcc LPTIM1_K>;
375 clocks = <&rcc SPI2_K>;
376 resets = <&rcc SPI2_R>;
400 clocks = <&rcc SPI3_K>;
[all …]
H A Dstm32mp133.dtsi18 clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
31 clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
44 clocks = <&rcc ADC1>, <&rcc ADC1_K>;
85 clocks = <&rcc ETH2MAC>,
86 <&rcc ETH2TX>,
87 <&rcc ETH2RX>,
88 <&rcc ETH2STP>,
89 <&rcc ETH2CK_K>;
H A Dstm32mp157.dtsi15 clocks = <&rcc GPU>, <&rcc GPU_K>;
17 resets = <&rcc GPU_R>;
23 clocks = <&rcc DSI>, <&clk_hse>, <&rcc DSI_PX>;
26 resets = <&rcc DSI_R>;
H A Dstm32mp157c-ev1-scmi.dts39 clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
57 clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
61 clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
80 &rcc {
81 compatible = "st,stm32mp1-rcc-secure", "syscon";
H A Dstm32f769.dtsi15 resets = <&rcc STM32F7_APB1_RESET(CAN3)>;
16 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
24 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
30 clocks = <&rcc 1 CLK_F769_DSI>, <&clk_hse>;
32 resets = <&rcc STM32F7_APB2_RESET(DSI)>;
H A Dstm32mp157a-dk1-scmi.dts33 clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
51 clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
70 &rcc {
71 compatible = "st,stm32mp1-rcc-secure", "syscon";
H A Dstm32f7-pinctrl.dtsi8 #include <dt-bindings/mfd/stm32f7-rcc.h>
25 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
35 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
45 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
55 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
65 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
75 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
85 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
95 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
105 clocks = <&rcc
[all...]
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dst,stm32-rcc.yaml4 $id: http://devicetree.org/schemas/clock/st,stm32-rcc.yaml#
13 The RCC IP is both a reset and a clock controller.
14 The reset phandle argument is the bit number within the RCC registers bank,
15 starting from RCC base address.
22 - st,stm32f42xx-rcc
23 - st,stm32f746-rcc
24 - st,stm32h743-rcc
25 - const: st,stm32-rcc
28 - st,stm32f469-rcc
29 - const: st,stm32f42xx-rcc
[all …]
H A Dst,stm32-rcc.txt4 The RCC IP is both a reset and a clock controller.
11 "st,stm32f42xx-rcc"
12 "st,stm32f469-rcc"
13 "st,stm32f746-rcc"
14 "st,stm32f769-rcc"
29 rcc: rcc@40023800 {
32 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
42 The secondary index is the bit number within the RCC register bank, starting
43 from the first RCC clock enable register (RCC_AHB1ENR, address offset 0x30).
49 drivers of the RCC IP, macros are available to generate the index in
[all …]
H A Dst,stm32mp1-rcc.yaml4 $id: http://devicetree.org/schemas/clock/st,stm32mp1-rcc.yaml#
13 The RCC IP is both a reset and a clock controller.
14 RCC makes also power management (resume/supend and wakeup interrupt).
33 The index is the bit number within the RCC registers bank, starting from RCC
59 - st,stm32mp1-rcc-secure
60 - st,stm32mp1-rcc
61 - st,stm32mp13-rcc
86 - st,stm32mp1-rcc-secure
87 - st,stm32mp13-rcc
119 rcc: rcc@50000000 {
[all …]
H A Dst,stm32h7-rcc.txt4 The RCC IP is both a reset and a clock controller.
11 "st,stm32h743-rcc"
31 rcc: reset-clock-controller@58024400 {
32 compatible = "st,stm32h743-rcc", "st,stm32-rcc";
50 clocks = <&rcc TIM5_CK>;
59 The index is the bit number within the RCC registers bank, starting from RCC
70 resets = <&rcc STM32H7_APB1L_RESET(TIM2)>;
H A Dst,stm32mp25-rcc.yaml4 $id: http://devicetree.org/schemas/clock/st,stm32mp25-rcc.yaml#
13 The RCC hardware block is both a reset and a clock controller.
14 RCC makes also power management (resume/supend).
17 include/dt-bindings/clock/st,stm32mp25-rcc.h
18 include/dt-bindings/reset/st,stm32mp25-rcc.h
23 - st,stm32mp25-rcc
132 #include <dt-bindings/clock/st,stm32mp25-rcc.h>
134 rcc: clock-controller@44200000 {
135 compatible = "st,stm32mp25-rcc";
/freebsd/sys/contrib/device-tree/src/arm64/st/
H A Dstm32mp231.dtsi6 #include <dt-bindings/clock/st,stm32mp25-rcc.h>
9 #include <dt-bindings/reset/st,stm32mp25-rcc.h>
232 clocks = <&rcc CK_BUS_SPI2>, <&rcc CK_KER_SPI2>;
234 resets = <&rcc SPI2_R>;
248 clocks = <&rcc CK_KER_SPI2>;
249 resets = <&rcc SPI2_R>;
262 clocks = <&rcc CK_BUS_SPI3>, <&rcc CK_KER_SPI3>;
264 resets = <&rcc SPI3_R>;
278 clocks = <&rcc CK_KER_SPI3>;
279 resets = <&rcc SPI3_R>;
[all …]
H A Dstm32mp251.dtsi6 #include <dt-bindings/clock/st,stm32mp25-rcc.h>
8 #include <dt-bindings/reset/st,stm32mp25-rcc.h>
238 clocks = <&rcc CK_BUS_OSPIIOM>,
242 resets = <&rcc OSPIIOM_R>,
299 clocks = <&rcc CK_KER_TIM2>;
330 clocks = <&rcc CK_KER_TIM3>;
361 clocks = <&rcc CK_KER_TIM4>;
392 clocks = <&rcc CK_KER_TIM5>;
423 clocks = <&rcc CK_KER_TIM6>;
448 clocks = <&rcc CK_KER_TIM7>;
[all …]
H A Dstm32mp253.dtsi58 clocks = <&rcc CK_ETH2_MAC>,
59 <&rcc CK_ETH2_TX>,
60 <&rcc CK_ETH2_RX>,
61 <&rcc CK_KER_ETH2PTP>,
62 <&rcc CK_ETH2_STP>,
63 <&rcc CK_KER_ETH2>;
H A Dstm32mp233.dtsi58 clocks = <&rcc CK_ETH2_MAC>,
59 <&rcc CK_ETH2_TX>,
60 <&rcc CK_ETH2_RX>,
61 <&rcc CK_KER_ETH2PTP>,
62 <&rcc CK_ETH2_STP>,
63 <&rcc CK_KER_ETH2>;
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dstm32-dwmac.yaml105 select RCC clock instead of ETH_REF_CLK. OR in RGMII mode when you want to select
106 RCC clock instead of ETH_CLK125.
111 set this property in RGMII PHY when you want to select RCC clock instead of ETH_CLK125.
117 select RCC clock instead of ETH_REF_CLK.
178 clocks = <&rcc ETHMAC>,
179 <&rcc ETHTX>,
180 <&rcc ETHRX>,
181 <&rcc ETHSTP>,
182 <&rcc ETHCK_K>;
199 clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>;
[all …]
/freebsd/contrib/sqlite3/
H A DMakefile.msc551 RCC = $(RC) -DSQLITE_OS_WIN=1 -I. -I$(TOP) $(RCOPTS) $(RCCOPTS)
675 RCC = $(RCC) -DSQLITE_OS_WINRT=1
677 RCC = $(RCC) -DWINAPI_FAMILY=WINAPI_FAMILY_APP
718 RCC = $(RCC) -DNDEBUG
723 RCC = $(RCC) -DSQLITE_ENABLE_API_ARMOR=1
728 RCC = $(RCC) -DSQLITE_DEBUG=1
731 RCC = $(RCC) -DSQLITE_ENABLE_WHERETRACE -DSQLITE_ENABLE_SELECTTRACE
737 RCC = $(RCC) -DSQLITE_FORCE_OS_TRACE=1 -DSQLITE_DEBUG_OS_TRACE=1
742 RCC = $(RCC) -DSQLITE_ENABLE_IOTRACE=1
750 RCC = $(RCC) -D_CRT_SECURE_NO_DEPRECATE -D_CRT_SECURE_NO_WARNINGS
[all …]
/freebsd/sys/contrib/device-tree/Bindings/i2c/
H A Dst,stm32-i2c.yaml145 #include <dt-bindings/mfd/stm32f7-rcc.h>
153 resets = <&rcc 277>;
154 clocks = <&rcc 0 149>;
160 #include <dt-bindings/mfd/stm32f7-rcc.h>
168 resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
169 clocks = <&rcc 1 CLK_I2C1>;
175 #include <dt-bindings/mfd/stm32f7-rcc.h>
186 clocks = <&rcc I2C2_K>;
187 resets = <&rcc I2C2_R>;
/freebsd/sys/contrib/device-tree/Bindings/media/
H A Dst,stm32mp25-csi.yaml92 #include <dt-bindings/clock/st,stm32mp25-rcc.h>
95 #include <dt-bindings/reset/st,stm32mp25-rcc.h>
100 resets = <&rcc CSI_R>;
101 clocks = <&rcc CK_KER_CSI>, <&rcc CK_KER_CSITXESC>, <&rcc CK_KER_CSIPHY>;
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dst,stm32mp25-combophy.yaml30 - description: ker Internal RCC reference clock for USB3 or PCIe
103 #include <dt-bindings/clock/st,stm32mp25-rcc.h>
105 #include <dt-bindings/reset/st,stm32mp25-rcc.h>
111 clocks = <&rcc CK_BUS_USB3PCIEPHY>, <&rcc CK_KER_USB3PCIEPHY>;
113 resets = <&rcc USB3PCIEPHY_R>;

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