101950c46SEmmanuel Vadot// SPDX-License-Identifier: GPL-2.0 201950c46SEmmanuel Vadot/* 301950c46SEmmanuel Vadot * Copyright (c) 2023 Dario Binacchi <dario.binacchi@amarulasolutions.com> 401950c46SEmmanuel Vadot */ 501950c46SEmmanuel Vadot 601950c46SEmmanuel Vadot#include "stm32f746.dtsi" 701950c46SEmmanuel Vadot 801950c46SEmmanuel Vadot/ { 901950c46SEmmanuel Vadot soc { 10*7d0873ebSEmmanuel Vadot can3: can@40003400 { 11*7d0873ebSEmmanuel Vadot compatible = "st,stm32f4-bxcan"; 12*7d0873ebSEmmanuel Vadot reg = <0x40003400 0x200>; 13*7d0873ebSEmmanuel Vadot interrupts = <104>, <105>, <106>, <107>; 14*7d0873ebSEmmanuel Vadot interrupt-names = "tx", "rx0", "rx1", "sce"; 15*7d0873ebSEmmanuel Vadot resets = <&rcc STM32F7_APB1_RESET(CAN3)>; 16*7d0873ebSEmmanuel Vadot clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>; 17*7d0873ebSEmmanuel Vadot st,gcan = <&gcan3>; 18*7d0873ebSEmmanuel Vadot status = "disabled"; 19*7d0873ebSEmmanuel Vadot }; 20*7d0873ebSEmmanuel Vadot 21*7d0873ebSEmmanuel Vadot gcan3: gcan@40003600 { 22*7d0873ebSEmmanuel Vadot compatible = "st,stm32f4-gcan", "syscon"; 23*7d0873ebSEmmanuel Vadot reg = <0x40003600 0x200>; 24*7d0873ebSEmmanuel Vadot clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>; 25*7d0873ebSEmmanuel Vadot }; 26*7d0873ebSEmmanuel Vadot 2701950c46SEmmanuel Vadot dsi: dsi@40016c00 { 2801950c46SEmmanuel Vadot compatible = "st,stm32-dsi"; 2901950c46SEmmanuel Vadot reg = <0x40016c00 0x800>; 3001950c46SEmmanuel Vadot clocks = <&rcc 1 CLK_F769_DSI>, <&clk_hse>; 3101950c46SEmmanuel Vadot clock-names = "pclk", "ref"; 3201950c46SEmmanuel Vadot resets = <&rcc STM32F7_APB2_RESET(DSI)>; 3301950c46SEmmanuel Vadot reset-names = "apb"; 3401950c46SEmmanuel Vadot status = "disabled"; 3501950c46SEmmanuel Vadot }; 3601950c46SEmmanuel Vadot }; 3701950c46SEmmanuel Vadot}; 38