Searched +full:r8a73a4 +full:- +full:mstp +full:- +full:clocks (Results 1 – 3 of 3) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/clock/renesas,cpg-mstp-clocks.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Renesas Clock Pulse Generator (CPG) Module Stop (MSTP) Clocks10 - Geert Uytterhoeven <geert+renesas@glider.be>13 The Clock Pulse Generator (CPG) can gate SoC device clocks. The gates are16 This device tree binding describes a single 32 gate clocks group per node.17 Clocks are referenced by user nodes by the Module Stop (MSTP) node phandle23 - enum:[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/clock/renesas,cpg-clocks.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Geert Uytterhoeven <geert+renesas@glider.be>13 The Clock Pulse Generator (CPG) generates core clocks for the SoC. It17 the CPG Module Stop (MSTP) Clocks.22 - const: renesas,r8a73a4-cpg-clocks # R-Mobile APE623 - const: renesas,r8a7740-cpg-clocks # R-Mobile A124 - const: renesas,r8a7778-cpg-clocks # R-Car M1[all …]
1 // SPDX-License-Identifier: GPL-2.03 * R-Car MSTP clocks12 #include <linux/clk-provider.h>25 * MSTP clocks. We can't use standard gate clocks as we need to poll on the32 * struct mstp_clock_group - MSTP gating clocks group34 * @data: clock specifier translation for clocks in this group38 * @width_8bit: registers are 8-bit, not 32-bit39 * @clks: clocks in this group51 * struct mstp_clock - MSTP gating clock52 * @hw: handle between common and hardware-specific interfaces[all …]