1 // SPDX-License-Identifier: GPL-2.0
3  * R-Car MSTP clocks
12 #include <linux/clk-provider.h>
25  * MSTP clocks. We can't use standard gate clocks as we need to poll on the
32  * struct mstp_clock_group - MSTP gating clocks group
34  * @data: clock specifier translation for clocks in this group
38  * @width_8bit: registers are 8-bit, not 32-bit
39  * @clks: clocks in this group
51  * struct mstp_clock - MSTP gating clock
52  * @hw: handle between common and hardware-specific interfaces
54  * @group: MSTP clocks group
67 	return group->width_8bit ? readb(reg) : readl(reg);  in cpg_mstp_read()
73 	group->width_8bit ? writeb(val, reg) : writel(val, reg);  in cpg_mstp_write()
79 	struct mstp_clock_group *group = clock->group;  in cpg_mstp_clock_endisable()
80 	u32 bitmask = BIT(clock->bit_index);  in cpg_mstp_clock_endisable()
85 	spin_lock_irqsave(&group->lock, flags);  in cpg_mstp_clock_endisable()
87 	value = cpg_mstp_read(group, group->smstpcr);  in cpg_mstp_clock_endisable()
92 	cpg_mstp_write(group, value, group->smstpcr);  in cpg_mstp_clock_endisable()
94 	if (!group->mstpsr) {  in cpg_mstp_clock_endisable()
96 		cpg_mstp_read(group, group->smstpcr);  in cpg_mstp_clock_endisable()
97 		barrier_data(group->smstpcr);  in cpg_mstp_clock_endisable()
100 	spin_unlock_irqrestore(&group->lock, flags);  in cpg_mstp_clock_endisable()
102 	if (!enable || !group->mstpsr)  in cpg_mstp_clock_endisable()
105 	/* group->width_8bit is always false if group->mstpsr is present */  in cpg_mstp_clock_endisable()
106 	ret = readl_poll_timeout_atomic(group->mstpsr, value,  in cpg_mstp_clock_endisable()
110 		       group->smstpcr, clock->bit_index);  in cpg_mstp_clock_endisable()
128 	struct mstp_clock_group *group = clock->group;  in cpg_mstp_clock_is_enabled()
131 	if (group->mstpsr)  in cpg_mstp_clock_is_enabled()
132 		value = cpg_mstp_read(group, group->mstpsr);  in cpg_mstp_clock_is_enabled()
134 		value = cpg_mstp_read(group, group->smstpcr);  in cpg_mstp_clock_is_enabled()
136 	return !(value & BIT(clock->bit_index));  in cpg_mstp_clock_is_enabled()
155 		return ERR_PTR(-ENOMEM);  in cpg_mstp_clock_register()
160 	/* INTC-SYS is the module clock of the GIC, and must not be disabled */  in cpg_mstp_clock_register()
161 	if (!strcmp(name, "intc-sys")) {  in cpg_mstp_clock_register()
162 		pr_debug("MSTP %s setting CLK_IS_CRITICAL\n", name);  in cpg_mstp_clock_register()
168 	clock->bit_index = index;  in cpg_mstp_clock_register()
169 	clock->group = group;  in cpg_mstp_clock_register()
170 	clock->hw.init = &init;  in cpg_mstp_clock_register()
172 	clk = clk_register(NULL, &clock->hw);  in cpg_mstp_clock_register()
191 	clks = group->clks;  in cpg_mstp_clocks_init()
192 	spin_lock_init(&group->lock);  in cpg_mstp_clocks_init()
193 	group->data.clks = clks;  in cpg_mstp_clocks_init()
195 	group->smstpcr = of_iomap(np, 0);  in cpg_mstp_clocks_init()
196 	group->mstpsr = of_iomap(np, 1);  in cpg_mstp_clocks_init()
198 	if (group->smstpcr == NULL) {  in cpg_mstp_clocks_init()
204 	if (of_device_is_compatible(np, "renesas,r7s72100-mstp-clocks"))  in cpg_mstp_clocks_init()
205 		group->width_8bit = true;  in cpg_mstp_clocks_init()
208 		clks[i] = ERR_PTR(-ENOENT);  in cpg_mstp_clocks_init()
210 	if (of_property_present(np, "clock-indices"))  in cpg_mstp_clocks_init()
211 		idxname = "clock-indices";  in cpg_mstp_clocks_init()
213 		idxname = "renesas,clock-indices";  in cpg_mstp_clocks_init()
221 		/* Skip clocks with no name. */  in cpg_mstp_clocks_init()
222 		ret = of_property_read_string_index(np, "clock-output-names",  in cpg_mstp_clocks_init()
241 			group->data.clk_num = max(group->data.clk_num,  in cpg_mstp_clocks_init()
248 	of_clk_add_provider(np, of_clk_src_onecell_get, &group->data);  in cpg_mstp_clocks_init()
250 CLK_OF_DECLARE(cpg_mstp_clks, "renesas,cpg-mstp-clocks", cpg_mstp_clocks_init);
254 	struct device_node *np = dev->of_node;  in cpg_mstp_attach_dev()
260 	while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,  in cpg_mstp_attach_dev()
263 					    "renesas,cpg-mstp-clocks"))  in cpg_mstp_attach_dev()
266 		/* BSC on r8a73a4/sh73a0 uses zb_clk instead of an mstp clock */  in cpg_mstp_attach_dev()
311 	if (of_property_read_u32(np, "#power-domain-cells", &ncells)) {  in cpg_mstp_add_clk_domain()
312 		pr_warn("%pOF lacks #power-domain-cells\n", np);  in cpg_mstp_add_clk_domain()
320 	pd->name = np->name;  in cpg_mstp_add_clk_domain()
321 	pd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |  in cpg_mstp_add_clk_domain()
323 	pd->attach_dev = cpg_mstp_attach_dev;  in cpg_mstp_add_clk_domain()
324 	pd->detach_dev = cpg_mstp_detach_dev;  in cpg_mstp_add_clk_domain()