Lines Matching +full:r8a73a4 +full:- +full:mstp +full:- +full:clocks
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,cpg-mstp-clocks.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas Clock Pulse Generator (CPG) Module Stop (MSTP) Clocks
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 The Clock Pulse Generator (CPG) can gate SoC device clocks. The gates are
16 This device tree binding describes a single 32 gate clocks group per node.
17 Clocks are referenced by user nodes by the Module Stop (MSTP) node phandle
23 - enum:
24 - renesas,r7s72100-mstp-clocks # RZ/A1
25 - renesas,r8a73a4-mstp-clocks # R-Mobile APE6
26 - renesas,r8a7740-mstp-clocks # R-Mobile A1
27 - renesas,r8a7778-mstp-clocks # R-Car M1
28 - renesas,r8a7779-mstp-clocks # R-Car H1
29 - renesas,sh73a0-mstp-clocks # SH-Mobile AG5
30 - const: renesas,cpg-mstp-clocks
35 - description: Module Stop Control Register (MSTPCR)
36 - description: Module Stop Status Register (MSTPSR)
38 clocks:
42 '#clock-cells':
45 clock-indices:
49 clock-output-names:
54 - compatible
55 - reg
56 - clocks
57 - '#clock-cells'
58 - clock-indices
59 - clock-output-names
64 - |
65 #include <dt-bindings/clock/r8a73a4-clock.h>
67 compatible = "renesas,r8a73a4-mstp-clocks",
68 "renesas,cpg-mstp-clocks";
70 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
72 #clock-cells = <1>;
73 clock-indices = <
79 clock-output-names =