Lines Matching +full:r8a73a4 +full:- +full:mstp +full:- +full:clocks
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,cpg-clocks.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 The Clock Pulse Generator (CPG) generates core clocks for the SoC. It
17 the CPG Module Stop (MSTP) Clocks.
22 - const: renesas,r8a73a4-cpg-clocks # R-Mobile APE6
23 - const: renesas,r8a7740-cpg-clocks # R-Mobile A1
24 - const: renesas,r8a7778-cpg-clocks # R-Car M1
25 - const: renesas,r8a7779-cpg-clocks # R-Car H1
26 - items:
27 - enum:
28 - renesas,r7s72100-cpg-clocks # RZ/A1H
29 - const: renesas,rz-cpg-clocks # RZ/A1
30 - const: renesas,sh73a0-cpg-clocks # SH-Mobile AG5
35 clocks:
39 '#clock-cells':
42 clock-output-names:
47 description: Board-specific settings of the MD_CK* bits on R-Mobile A1
52 '#power-domain-cells':
56 - compatible
57 - reg
58 - clocks
59 - '#clock-cells'
60 - clock-output-names
63 - if:
67 const: renesas,r8a73a4-cpg-clocks
70 clocks:
72 - description: extal1
73 - description: extal2
75 clock-output-names:
77 - const: main
78 - const: pll0
79 - const: pll1
80 - const: pll2
81 - const: pll2s
82 - const: pll2h
83 - const: z
84 - const: z2
85 - const: i
86 - const: m3
87 - const: b
88 - const: m1
89 - const: m2
90 - const: zx
91 - const: zs
92 - const: hp
94 - if:
98 const: renesas,r8a7740-cpg-clocks
101 clocks:
103 - description: extal1
104 - description: extal2
105 - description: extalr
107 clock-output-names:
109 - const: system
110 - const: pllc0
111 - const: pllc1
112 - const: pllc2
113 - const: r
114 - const: usb24s
115 - const: i
116 - const: zg
117 - const: b
118 - const: m1
119 - const: hp
120 - const: hpp
121 - const: usbp
122 - const: s
123 - const: zb
124 - const: m3
125 - const: cp
128 - renesas,mode
130 - if:
134 const: renesas,r8a7778-cpg-clocks
137 clocks:
140 clock-output-names:
142 - const: plla
143 - const: pllb
144 - const: b
145 - const: out
146 - const: p
147 - const: s
148 - const: s1
150 - if:
154 const: renesas,r8a7779-cpg-clocks
157 clocks:
160 clock-output-names:
162 - const: plla
163 - const: z
164 - const: zs
165 - const: s
166 - const: s1
167 - const: p
168 - const: b
169 - const: out
171 - if:
175 const: renesas,r7s72100-cpg-clocks
178 clocks:
180 - description: extal1
181 - description: usb_x1
183 clock-output-names:
185 - const: pll
186 - const: i
187 - const: g
189 - if:
193 const: renesas,sh73a0-cpg-clocks
196 clocks:
198 - description: extal1
199 - description: extal2
201 clock-output-names:
203 - const: main
204 - const: pll0
205 - const: pll1
206 - const: pll2
207 - const: pll3
208 - const: dsi0phy
209 - const: dsi1phy
210 - const: zg
211 - const: m3
212 - const: b
213 - const: m1
214 - const: m2
215 - const: z
216 - const: zx
217 - const: hp
219 - if:
224 - renesas,r8a7778-cpg-clocks
225 - renesas,r8a7779-cpg-clocks
226 - renesas,rz-cpg-clocks
229 - '#power-domain-cells'
234 - |
235 #include <dt-bindings/clock/r8a7740-clock.h>
237 compatible = "renesas,r8a7740-cpg-clocks";
239 clocks = <&extal1_clk>, <&extal2_clk>, <&extalr_clk>;
240 #clock-cells = <1>;
241 clock-output-names = "system", "pllc0", "pllc1", "pllc2", "r",