| /freebsd/sys/contrib/alpine-hal/ |
| H A D | al_hal_udma_regs_gen.h | 9 found at http://www.gnu.org/licenses/gpl-2.0.html
100 /* [0x0] Target-ID control */
102 /* [0x4] TX queue 0/1 Target-ID */
104 /* [0x8] TX queue 2/3 Target-ID */
106 /* [0xc] RX queue 0/1 Target-ID */
108 /* [0x10] RX queue 2/3 Target-ID */
112 /* [0x0] TX queue 0/1 Target-Address */
114 /* [0x4] TX queue 2/3 Target-Address */
116 /* [0x8] RX queue 0/1 Target-Address */
118 /* [0xc] RX queue 2/3 Target-Address */
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| /freebsd/share/man/man4/ |
| H A D | gve.4 | 1 .\" SPDX-License-Identifier: BSD-3-Clause
3 .\" Copyright (c) 2023-2024 Google LLC
39 .Bd -ragged -offset indent
46 .Bd -literal -offset indent
51 It is required to support per-VM Tier-1 networking performance, and for using certain VM shapes on …
57 .Bl -bullet -compact
78 .Bl -bullet -compact
84 Change the TX queue count to 4 for the gve0 interface:
87 Change the RX queue count to 4 for the gve0 interface:
93 Change the RX ring size to 512 for the gve0 interface:
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| H A D | ena.4 | 1 .\" SPDX-License-Identifier: BSD-2-Clause
3 .\" Copyright (c) 2015-2024 Amazon.com, Inc. or its affiliates.
40 .Bd -ragged -offset indent
47 .Bd -literal -offset indent
56 through an Admin Queue.
58 The driver supports a range of ENA devices, is link-speed independent
62 Some ENA devices support SR-IOV.
63 This driver is used for both the SR-IOV Physical Function (PF) and Virtual
67 processing by providing multiple Tx/Rx queue pairs (the maximum number
68 is advertised by the device via the Admin Queue), a dedicated MSI-X
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| H A D | iflib.4 | 28 .Bl -tag -width indent
30 Override the number of RX descriptors for each queue.
37 Override the number of TX descriptors for each queue.
45 If not set, the lower of the number of TX or RX queues will be used for both.
47 Set the number of RX queues.
48 If zero, the number of RX queues is derived from the number of cores on the
56 Disables MSI-X interrupts for the device.
62 Requests that RX and TX queues not be paired on the same core.
63 If this is zero or not set, an RX and TX queue pair will be assigned to each
65 When set to a non-zero value, TX queues are assigned to cores following the
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| /freebsd/sys/dev/vge/ |
| H A D | if_vgereg.h | 1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
18 * 4. Neither the name of the author nor the names of any co-contributors
37 * Definitions for the built-in copper PHY can be found in vgphy.h.
41 * using 32-bit I/O cycles, but some of them are less than 32 bits
54 #define VGE_RXCTL 0x06 /* RX control register */
82 #define VGE_RXHOSTERR 0x23 /* RX host error status */
86 #define VGE_TXQCSRS 0x30 /* TX queue ctl/status set */
87 #define VGE_RXQCSRS 0x32 /* RX queue ctl/status set */
88 #define VGE_TXQCSRC 0x34 /* TX queue ctl/status clear */
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| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | keystone-netcp.txt | 6 switch sub-module to send and receive packets. NetCP also includes a packet
13 includes a 3-port Ethernet switch sub-module capable of 10Gb/s and 1Gb/s rates
16 Keystone NetCP driver has a plug-in module architecture where each of the NetCP
17 sub-modules exist as a loadable kernel module which plug in to the netcp core.
18 These sub-modules are represented as "netcp-devices" in the dts bindings. It is
19 mandatory to have the ethernet switch sub-module for the ethernet interface to
20 be operational. Any other sub-module like the PA is optional.
24 -----------------------------
26 -----------------------------
28 |-> NetCP Devices -> |
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| H A D | intel,ixp4xx-ethernet.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/intel,ixp4xx-ethernet.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-controller.yaml#
14 - Linus Walleij <linus.walleij@linaro.org>
18 Processing Engine) and the IXP4xx Queue Manager to process
24 const: intel,ixp4xx-ethernet
30 queue-rx:
31 $ref: /schemas/types.yaml#/definitions/phandle-array
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| H A D | intel,ixp4xx-hss.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/intel,ixp4xx-hss.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Linus Walleij <linus.walleij@linaro.org>
15 Processing Engine) and the IXP4xx Queue Manager to process
20 const: intel,ixp4xx-hss
26 intel,npe-handle:
27 $ref: /schemas/types.yaml#/definitions/phandle-array
30 - description: phandle to the NPE this HSS instance is using
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| H A D | snps,dwmac.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Torgue <alexandre.torgue@foss.st.com>
11 - Giuseppe Cavallaro <peppe.cavallaro@st.com>
12 - Jose Abreu <joabreu@synopsys.com>
23 - snps,dwmac
24 - snps,dwmac-3.40a
25 - snps,dwmac-3.50a
26 - snps,dwmac-3.610
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| /freebsd/sys/dev/bxe/ |
| H A D | ecore_mfw_req.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2007-2017 QLogic Corporation. All rights reserved.
115 uint32_t promiscuous_mode; /* Promiscuous Mode. non-zero true */
116 uint32_t txq_size; /* TX Descriptors Queue Size */
117 uint32_t rxq_size; /* RX Descriptors Queue Size */
118 /* TX Descriptor Queue Avg Depth. % Avg Queue Depth since last poll */
120 /* RX Descriptors Queue Avg Depth. % Avg Queue Depth since last poll */
135 /* QoS Priority (per 802.1p). 0-7255 */
137 uint32_t txq_size; /* FCoE TX Descriptors Queue Size. */
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| /freebsd/sys/contrib/dev/iwlwifi/mld/ |
| H A D | rx.h | 1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2024-2025 Intel Corporation
11 * enum iwl_mld_internal_rxq_notif_type - RX queue sync notif types
22 * struct iwl_mld_internal_rxq_notif - @iwl_rxq_sync_cmd internal data.
29 * @payload: data to send to RX queues based on the type (may be empty)
39 * struct iwl_mld_rx_queues_sync - RX queues sync data
41 * @waitq: wait queue for RX queues sync completion
43 * @state: bitmask representing the sync state of RX queues
44 * all RX queues bits are set before sending the command, and the
45 * corresponding queue bit cleared upon handling the notification
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| /freebsd/sys/contrib/device-tree/Bindings/crypto/ |
| H A D | intel,ixp4xx-crypto.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/crypto/intel,ixp4xx-crypto.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Linus Walleij <linus.walleij@linaro.org>
21 const: intel,ixp4xx-crypto
23 intel,npe-handle:
24 $ref: /schemas/types.yaml#/definitions/phandle-array
26 - items:
27 - description: phandle to the NPE this crypto engine
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| /freebsd/sys/contrib/device-tree/src/arm/ti/keystone/ |
| H A D | keystone-k2e-netcp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
9 compatible = "ti,keystone-navigator-qmss";
10 dma-coherent;
11 #address-cells = <1>;
12 #size-cells = <1>;
15 queue-range = <0 0x2000>;
20 #address-cells = <1>;
21 #size-cells = <1>;
24 managed-queues = <0 0x2000>;
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| H A D | keystone-k2l-netcp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
9 compatible = "ti,keystone-navigator-qmss";
10 dma-coherent;
11 #address-cells = <1>;
12 #size-cells = <1>;
15 queue-range = <0 0x2000>;
20 #address-cells = <1>;
21 #size-cells = <1>;
24 managed-queues = <0 0x2000>;
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| H A D | keystone-k2hk-netcp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
9 compatible = "ti,keystone-navigator-qmss";
10 dma-coherent;
11 #address-cells = <1>;
12 #size-cells = <1>;
15 queue-range = <0 0x4000>;
20 #address-cells = <1>;
21 #size-cells = <1>;
24 managed-queues = <0 0x2000>;
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| H A D | keystone-k2g-netcp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
9 compatible = "ti,66ak2g-navss-qm";
10 dma-coherent;
11 #address-cells = <1>;
12 #size-cells = <1>;
13 power-domains = <&k2g_pds 0x0018>;
15 clock-names = "nss_vclk";
17 queue-range = <0 0x80>;
22 #address-cells = <1>;
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| /freebsd/sys/contrib/dev/mediatek/mt76/mt7996/ |
| H A D | dma.c | 1 // SPDX-License-Identifier: ISC
16 struct mt7996_dev *dev = phy->dev; in mt7996_init_tx_queues()
21 idx -= MT_TXQ_ID(0); in mt7996_init_tx_queues()
23 if (phy->mt76->band_idx == MT_BAND2) in mt7996_init_tx_queues()
29 return mt76_connac_init_tx_queues(phy->mt76, idx, n_desc, in mt7996_init_tx_queues()
39 mt76_connac_tx_cleanup(&dev->mt76); in mt7996_poll_tx()
50 dev->q_wfdma_mask |= (1 << (q)); \ in mt7996_dma_config()
51 dev->q_int_mask[(q)] = int; \ in mt7996_dma_config()
52 dev->q_id[(q)] = id; \ in mt7996_dma_config()
59 /* rx queue */ in mt7996_dma_config()
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| /freebsd/sys/contrib/alpine-hal/eth/ |
| H A D | al_hal_eth.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
61 /* *INDENT-OFF* */
65 /* *INDENT-ON* */
97 #define AL_ETH_TSO_MSS_MAX_VAL (AL_ETH_MAX_FRAME_LEN - 200)
174 /** Tx to Rx switching decision type */
182 /** Tx to Rx VLAN ID selection type */
192 /** Rx descriptor configurations */
193 /* Note: when selecting rx descriptor field to inner packet, then that field
194 * will be set according to inner packet when packet is tunneled, for non-tunneled
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| /freebsd/sys/dev/e1000/ |
| H A D | e1000_defines.h | 2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
94 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
122 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
132 #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
172 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
173 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
198 #define E1000_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min thresh size */
205 #define E1000_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */
206 #define E1000_RCTL_SZ_1024 0x00010000 /* Rx buffer size 1024 */
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| /freebsd/sys/contrib/ncsw/inc/flib/ |
| H A D | fsl_fman_port.h | 2 * Copyright 2008-2013 Freescale Semiconductor Inc.
150 /** @Description BMI Rx port register map */
152 uint32_t fmbm_rcfg; /**< Rx Configuration */
153 uint32_t fmbm_rst; /**< Rx Status */
154 uint32_t fmbm_rda; /**< Rx DMA attributes*/
155 uint32_t fmbm_rfp; /**< Rx FIFO Parameters*/
156 uint32_t fmbm_rfed; /**< Rx Frame End Data*/
157 uint32_t fmbm_ricp; /**< Rx Internal Context Parameters*/
158 uint32_t fmbm_rim; /**< Rx Internal Buffer Margins*/
159 uint32_t fmbm_rebm; /**< Rx External Buffer Margins*/
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| /freebsd/sys/arm/ti/cpsw/ |
| H A D | if_cpsw.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
39 * a 3-port store-and-forward switch connected to two independent
252 { -1, 0 }
331 if ((_sc)->debug) { \
341 mtx_assert(&(sc)->rx.lock, MA_NOTOWNED); \
342 mtx_lock(&(sc)->tx.lock); \
345 #define CPSW_TX_UNLOCK(sc) mtx_unlock(&(sc)->tx.lock)
346 #define CPSW_TX_LOCK_ASSERT(sc) mtx_assert(&(sc)->tx.lock, MA_OWNED)
349 mtx_assert(&(sc)->tx.lock, MA_NOTOWNED); \
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| /freebsd/sys/dev/qcom_ess_edma/ |
| H A D | qcom_ess_edma_hw.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
66 * for the ESS core - and that includes both the EDMA (ethernet)
69 * AND, it's a placeholder for what the linux ess-edma driver
72 * ess-switch won't be initialised. In that case it defaults
77 * So, for now this is a big no-op, at least until everything
79 * this EDMA driver code to co-exist.
87 device_printf(sc->sc_dev, "%s: called, TODO!\n", __func__); in qcom_ess_edma_hw_reset()
90 * This is where the linux ess-edma driver would reset the in qcom_ess_edma_hw_reset()
95 * and here's where the linux ess-edma driver would program in qcom_ess_edma_hw_reset()
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| /freebsd/sys/contrib/dev/iwlwifi/pcie/gen1_2/ |
| H A D | rx.c | 1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2003-2014, 2018-2024 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
11 #include "iwl-prph.h"
12 #include "iwl-io.h"
14 #include "iwl-op-mode.h"
15 #include "pcie/iwl-context-info-v2.h"
20 * RX path functions
25 * Rx theory of operation
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| /freebsd/sys/dev/ice/ |
| H A D | ice_iflib.h | 1 /* SPDX-License-Identifier: BSD-3-Clause */
37 * implementation, including the Tx and Rx queue structures and the ice_softc
65 * ASSERT_CTX_LOCKED - Assert that the iflib context lock is held
71 #define ASSERT_CTX_LOCKED(sc) sx_assert((sc)->iflib_ctx_lock, SA_XLOCKED)
74 * IFLIB_CTX_LOCK - lock the iflib context lock
79 #define IFLIB_CTX_LOCK(sc) sx_xlock((sc)->iflib_ctx_lock)
82 * IFLIB_CTX_UNLOCK - unlock the iflib context lock
87 #define IFLIB_CTX_UNLOCK(sc) sx_xunlock((sc)->iflib_ctx_lock)
90 * ASSERT_CFG_LOCKED - Assert that a configuration lock is held
100 * ICE_IFLIB_MAX_DESC_COUNT - Maximum ring size for iflib
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| /freebsd/sys/dev/qlnx/qlnxe/ |
| H A D | ecore_l2_api.h | 2 * Copyright (c) 2017-2018 Cavium, Inc.
107 /* Indirection table consist of rx queue handles */
204 /* Add / remove / move / remove-all unicast MAC-VLAN filters.
236 * @brief ecore_eth_rx_queue_start - RX Queue Start Ramrod
238 * This ramrod initializes an RX Queue for a VPort. An Assert is generated if
263 * @brief ecore_eth_rx_queue_stop - This ramrod closes an Rx queue
266 * @param p_rxq Handler of queue to close
283 * @brief - TX Queue Start Ramrod
285 * This ramrod initializes a TX Queue for a VPort. An Assert is generated if
308 * @brief ecore_eth_tx_queue_stop - closes a Tx queue
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