Lines Matching +full:queue +full:- +full:rx
2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
94 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
122 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
132 #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
173 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
174 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
199 #define E1000_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min thresh size */
206 #define E1000_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */
207 #define E1000_RCTL_SZ_1024 0x00010000 /* Rx buffer size 1024 */
208 #define E1000_RCTL_SZ_512 0x00020000 /* Rx buffer size 512 */
209 #define E1000_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */
211 #define E1000_RCTL_SZ_16384 0x00010000 /* Rx buffer size 16384 */
212 #define E1000_RCTL_SZ_8192 0x00020000 /* Rx buffer size 8192 */
213 #define E1000_RCTL_SZ_4096 0x00030000 /* Rx buffer size 4096 */
259 #define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
262 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
264 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
341 #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
342 #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
344 /* Constants used to interpret the masked PCI-X bus speed. */
345 #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus spd 50-66MHz */
346 #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus spd 66-100MHz */
347 #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus spd 100-133MHz*/
366 /* 1000/H is not supported, nor spec-compliant. */
421 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
425 #define E1000_TARC0_ENABLE 0x00000400 /* Enable Tx Queue 0 */
475 /* The datasheet maximum supported RX size is 9.5KB (9728 bytes) */
545 #define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */
547 #define E1000_ICR_RXSEQ 0x00000008 /* Rx sequence error */
548 #define E1000_ICR_RXDMT0 0x00000010 /* Rx desc min. threshold (0) */
549 #define E1000_ICR_RXO 0x00000040 /* Rx overrun */
550 #define E1000_ICR_RXT0 0x00000080 /* Rx timer intr (ring 0) */
552 #define E1000_ICR_RXCFG 0x00000400 /* Rx /c/ ordered set */
565 #define E1000_ICR_RXQ0 0x00100000 /* Rx Queue 0 Interrupt */
566 #define E1000_ICR_RXQ1 0x00200000 /* Rx Queue 1 Interrupt */
567 #define E1000_ICR_TXQ0 0x00400000 /* Tx Queue 0 Interrupt */
568 #define E1000_ICR_TXQ1 0x00800000 /* Tx Queue 1 Interrupt */
586 #define E1000_EICR_RX_QUEUE0 0x00000001 /* Rx Queue 0 Interrupt */
587 #define E1000_EICR_RX_QUEUE1 0x00000002 /* Rx Queue 1 Interrupt */
588 #define E1000_EICR_RX_QUEUE2 0x00000004 /* Rx Queue 2 Interrupt */
589 #define E1000_EICR_RX_QUEUE3 0x00000008 /* Rx Queue 3 Interrupt */
590 #define E1000_EICR_TX_QUEUE0 0x00000100 /* Tx Queue 0 Interrupt */
591 #define E1000_EICR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */
592 #define E1000_EICR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */
593 #define E1000_EICR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */
619 #define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
622 #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */
623 #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */
624 #define E1000_IMS_RXO E1000_ICR_RXO /* Rx overrun */
625 #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* Rx timer intr */
631 #define E1000_IMS_RXQ0 E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */
632 #define E1000_IMS_RXQ1 E1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */
633 #define E1000_IMS_TXQ0 E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */
634 #define E1000_IMS_TXQ1 E1000_ICR_TXQ1 /* Tx Queue 1 Interrupt */
641 #define E1000_EIMS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */
642 #define E1000_EIMS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */
643 #define E1000_EIMS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */
644 #define E1000_EIMS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */
645 #define E1000_EIMS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
646 #define E1000_EIMS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */
647 #define E1000_EIMS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */
648 #define E1000_EIMS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */
654 #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */
655 #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */
658 #define E1000_EICS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */
659 #define E1000_EICS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */
660 #define E1000_EICS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */
661 #define E1000_EICS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */
662 #define E1000_EICS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
663 #define E1000_EICS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */
664 #define E1000_EICS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */
665 #define E1000_EICS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */
728 /* Loop limit on how long we wait for auto-negotiation to complete */
752 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
769 #define E1000_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */
770 #define E1000_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */
776 #define E1000_TSYNCRXCTL_ENABLED 0x00000010 /* enable Rx timestamping */
814 /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
823 #define E1000_TTQF_QUEUE_ENABLE 0x100 /* TTQF Queue Enable Bit */
832 #define E1000_TTQF_QUEUE_SHIFT 16 /* TTQF Queue Shfit */
833 #define E1000_TTQF_RX_QUEUE_MASK 0x70000 /* TTQF Queue Mask */
866 #define E1000_EEER_RX_LPI_EN 0x00020000 /* EEER Rx LPI Enable */
870 #define E1000_EEER_RX_LPI_STATUS 0x40000000 /* Rx in LPI state */
977 #define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP rx'd link code word */
987 /* 1000BASE-T Control Register */
1003 /* 1000BASE-T Status Register */
1026 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
1027 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
1047 #define E1000_EECD_TYPE 0x00002000 /* NVM Type (1-SPI, 0-Microwire) */
1193 /* NVM Commands - Microwire */
1200 /* NVM Commands - SPI */
1204 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
1232 /* PCI/PCI-X/PCI-EX Config space */
1256 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1307 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
1318 * 1 = 50-80M
1319 * 2 = 80-110M
1320 * 3 = 110-140M
1383 * 15-5: page
1384 * 4-0: register offset
1402 /* Page 193 - Port Control Registers */
1407 /* Page 194 - KMRN Registers */
1451 /* Tx Rate-Scheduler Config fields */
1461 /* DMA Coalescing Rx Threshold */
1468 /* DMA Coalescing BMC-to-OS Watchdog Enable */
1476 /* Rx Traffic Rate Threshold */
1478 /* Rx packet rate in current window */
1481 /* DMA Coal Rx Traffic Current Count */
1484 /* Flow ctrl Rx Threshold High val */
1490 #define E1000_RXPBS_CFG_TS_EN 0x80000000 /* Timestamp in Rx buffer */
1491 #define E1000_RXPBS_SIZE_I210_MASK 0x0000003F /* Rx packet buffer size */