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/linux/tools/perf/pmu-events/arch/powerpc/power10/
H A Dfloating_point.json30 "BriefDescription": "Single Precision floating point instruction completed."
40 …"BriefDescription": "Double Precision vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres,…
45 "BriefDescription": "Four Double Precision vector instruction completed."
65 "BriefDescription": "Double-Precision or Quad-Precision instruction completed."
/linux/arch/parisc/math-emu/
H A Dfpudispatch.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Linux/PA-RISC Project (http://www.parisc-linux.org/)
5 * Floating-point emulation code
6 * Copyright (C) 2001 Hewlett-Packard (Paul Bame) <bame@debian.org>
52 #define extru(r,pos,len) (((r) >> (31-(pos))) & (( 1 << (len)) - 1))
73 * the following are for the multi-ops
106 * positions 21-22
111 * located at bit positions 16-18
116 * at bit positions 15-16 (PA1.1) or 14-16 (PA2.0)
160 /* on pa-linux the fpu type is not filled in by the in parisc_linux_get_fpu_type()
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H A Dfloat.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Linux/PA-RISC Project (http://www.parisc-linux.org/)
5 * Floating-point emulation code
6 * Copyright (C) 2001 Hewlett-Packard (Paul Bame) <bame@debian.org>
26 PA header file -- do not include this header file for non-PA builds.
41 * floating-point precisions.
44 * +-------+-------+-------+-------+-------+-------+-------+-------+
46 * +-------+-------+-------+-------+-------+-------+-------+-------+
97 * +-------+-------+-------+-------+-------+-------+-------+-------+
99 * +-------+-------+-------+-------+-------+-------+-------+-------+
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/linux/arch/powerpc/kernel/
H A Dvector.S1 /* SPDX-License-Identifier: GPL-2.0 */
7 #include <asm/asm-offsets.h>
12 #include <asm/asm-compat.h>
47 * Note that on 32-bit this can only use registers that will be
48 * restored by fast_exception_return, i.e. r3 - r6, r10 and r11.
69 li r4,-1
119 #error This asm code isn't ready for 32-bit kernels
158 * usage of floating-point registers. These routines must be called
166 .long 0x3f800000 /* 1.0 in single-precision FP */
168 .long 0x3f000000 /* 0.5 in single-precision FP */
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/linux/Documentation/arch/powerpc/
H A Delf_hwcaps.rst11 ---------------
46 -------------
56 -------------
65 -------------------
67 HWCAPs are allocated as described in Power Architecture 64-Bit ELF V2 ABI
71 ---------------------------------
74 32-bit CPU
77 64-bit CPU (userspace may be running in 32-bit mode).
105 Embedded Floating Point single precision operations are available.
108 Embedded Floating Point double precision operations are available.
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/linux/tools/perf/pmu-events/arch/powerpc/power9/
H A Dtranslation.json20 "BriefDescription": "Double-Precion or Quad-Precision instruction completed"
115 …cause the NTF instruction was a vector instruction issued to the Double Precision execution pipe a…
130 "BriefDescription": "Demand LD - L2 Miss (not L2 hit)"
140 …"BriefDescription": "The number a times the core transitioned from a stall to ICT-empty for this t…
170 "BriefDescription": "Stores completed from S2Q (2nd-level store queue)."
220 …stall because the NTF instruction was a scalar multi-cycle instruction issued to the Double Precis…
/linux/drivers/net/ethernet/intel/ice/
H A Dice_ptp_hw.c1 // SPDX-License-Identifier: GPL-2.0
24 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR,
26 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR,
28 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, 0, },
29 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, 0, },
34 { "GNSS-1PPS", ZL_REF4P, DPLL_PIN_TYPE_GNSS,
39 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR,
41 { "CVL-SDP2
2709 ice_fill_quad_msg_e82x(struct ice_hw * hw,struct ice_sbq_msg_input * msg,u8 quad,u16 offset) ice_fill_quad_msg_e82x() argument
2741 ice_read_quad_reg_e82x(struct ice_hw * hw,u8 quad,u16 offset,u32 * val) ice_read_quad_reg_e82x() argument
2775 ice_write_quad_reg_e82x(struct ice_hw * hw,u8 quad,u16 offset,u32 val) ice_write_quad_reg_e82x() argument
2809 ice_read_phy_tstamp_e82x(struct ice_hw * hw,u8 quad,u8 idx,u64 * tstamp) ice_read_phy_tstamp_e82x() argument
2865 ice_clear_phy_tstamp_e82x(struct ice_hw * hw,u8 quad,u8 idx) ice_clear_phy_tstamp_e82x() argument
2888 ice_ptp_reset_ts_memory_quad_e82x(struct ice_hw * hw,u8 quad) ice_ptp_reset_ts_memory_quad_e82x() argument
2900 unsigned int quad; ice_ptp_reset_ts_memory_e82x() local
3294 u8 quad; ice_phy_cfg_lane_e82x() local
4343 ice_get_phy_tx_tstamp_ready_e82x(struct ice_hw * hw,u8 quad,u64 * tstamp_ready) ice_get_phy_tx_tstamp_ready_e82x() argument
4379 int quad; ice_check_phy_tx_tstamp_ready_e82x() local
4408 ice_phy_cfg_intr_e82x(struct ice_hw * hw,u8 quad,bool ena,u8 threshold) ice_phy_cfg_intr_e82x() argument
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/linux/include/math-emu/
H A Dquad.h1 /* Software floating-point emulation.
2 Definitions for IEEE Quad Precision.
23 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
39 #define _FP_FRACXBITS_Q (_FP_FRACTBITS_Q - _FP_FRACBITS_Q)
41 #define _FP_WFRACXBITS_Q (_FP_FRACTBITS_Q - _FP_WFRACBITS_Q)
47 ((_FP_W_TYPE)1 << (_FP_FRACBITS_Q-2) % _FP_W_TYPE_SIZE)
49 ((_FP_W_TYPE)1 << (_FP_FRACBITS_Q-1) % _FP_W_TYPE_SIZE)
63 unsigned long frac3 : _FP_FRACBITS_Q - (_FP_IMPLBIT_Q != 0)-(_FP_W_TYPE_SIZE * 3);
71 unsigned long frac3 : _FP_FRACBITS_Q - (_FP_IMPLBIT_Q != 0)-(_FP_W_TYPE_SIZE * 3);
141 unsigned long frac1 : _FP_FRACBITS_Q-(_FP_IMPLBIT_Q != 0)-_FP_W_TYPE_SIZE;
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/linux/drivers/net/ethernet/intel/iavf/
H A Diavf_txrx.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
14 * iavf_is_descriptor_done - tests DD bit in Rx descriptor
15 * @qw1: quad word 1 from descriptor to get Descriptor Done field from
45 * iavf_unmap_and_free_tx_resource - Release a Tx buffer
52 if (tx_buffer->skb) { in iavf_unmap_and_free_tx_resource()
53 if (tx_buffer->tx_flags & IAVF_TX_FLAGS_FD_SB) in iavf_unmap_and_free_tx_resource()
54 kfree(tx_buffer->raw_buf); in iavf_unmap_and_free_tx_resource()
56 dev_kfree_skb_any(tx_buffer->skb); in iavf_unmap_and_free_tx_resource()
58 dma_unmap_single(ring->dev, in iavf_unmap_and_free_tx_resource()
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/linux/sound/hda/codecs/realtek/
H A Dalc269.c1 // SPDX-License-Identifier: GPL-2.0-or-later
21 /* different alc269-variants */
55 struct alc_spec *spec = codec->spec; in alc269_parse_auto_config()
58 switch (spec->codec_variant) { in alc269_parse_auto_config()
106 if (jack->unsol_res & (7 << 13)) in alc_headset_btn_callback()
109 if (jack->unsol_re in alc_headset_btn_callback()
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/linux/tools/arch/x86/include/asm/
H A Dcpufeatures.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 #define NCAPINTS 22 /* N 32-bit words worth of info */
9 #define NBUGINTS 2 /* N 32-bit bug flags */
17 * please update the table in kernel/cpu/cpuid-deps.c as well.
20 /* Intel-defined CPU features, CPUID level 0x00000001 (EDX), word 0 */
26 #define X86_FEATURE_MSR ( 0*32+ 5) /* "msr" Model-Specific Registers */
37 #define X86_FEATURE_PSE36 ( 0*32+17) /* "pse36" 36-bit PSEs */
47 #define X86_FEATURE_HT ( 0*32+28) /* "ht" Hyper-Threading */
49 #define X86_FEATURE_IA64 ( 0*32+30) /* "ia64" IA-64 processor */
52 /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
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/linux/drivers/net/ethernet/qlogic/qed/
H A Dqed_debug.c1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
4 * Copyright (c) 2019-2021 Marvell International Ltd.
157 return r[0] < (r[1] - imm[0]); in cond8()
235 /* Debug bus pre-trigger recording types */
242 /* Debug bus post-trigger recording types */
290 * Addresses are in bytes, sizes are in quad-regs.
398 (((1 << FIELD_BIT_SIZE(type, field)) - 1) << \
420 (GET_FIELD((block)->flags, DBG_BLOCK_CHIP_HAS_LATENCY_EVENTS) ? 2 : 1)
422 ((block)->num_of_dbg_bus_lines + NUM_EXTRA_DBG_LINES(block))
913 struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; in qed_grc_set_param()
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/linux/drivers/gpu/drm/msm/registers/adreno/
H A Da5xx.xml1 <?xml version="1.0" encoding="UTF-8"?>
3 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4 xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
32 <value value="0x37" name="RB5_R10G10B10A2_UNORM"/> <!-- GL_RGB10_A2 -->
33 <value value="0x3a" name="RB5_R10G10B10A2_UINT"/> <!-- GL_RGB10_A2UI -
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/linux/arch/powerpc/xmon/
H A Dppc-opc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* ppc-opc.c -- PowerPC opcode list
3 Copyright (C) 1994-2016 Free Software Foundation, Inc.
27 inserting operands into instructions and vice-versa is kept in this
173 /* The BD field in a B form instruction when the - modifier is used.
179 /* The BD field in a B form instruction when the - modifier is used
224 /* The BO field in a B form instruction when the + or - modifier is
254 { 0x1fe, -1, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
411 /* If the FXM4 operand is omitted, use the sentinel value -1. */
412 { -1, -1, NULL, NULL, 0},
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/linux/
H A DMAINTAINERS5 ----------
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