quad\-precision (full) in projects: linux

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Searched +full:quad +full:- +full:precision (Results 1 – 20 of 20) sorted by relevance

/linux/tools/perf/pmu-events/arch/powerpc/power10/
H A D	floating_point.json	`30 "BriefDescription": "Single Precision floating point instruction completed." 40 …"BriefDescription": "Double Precision vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres,… 45 "BriefDescription": "Four Double Precision vector instruction completed." 65 "BriefDescription": "Double-Precision or Quad-Precision instruction completed."`
/linux/arch/parisc/math-emu/
H A D	fpudispatch.c	1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * Linux/PA-RISC Project (http://www.parisc-linux.org/) 5 * Floating-point emulation code 6 * Copyright (C) 2001 Hewlett-Packard (Paul Bame) <bame@debian.org> 52 #define extru(r,pos,len) (((r) >> (31-(pos))) & (( 1 << (len)) - 1)) 73 * the following are for the multi-ops 106 * positions 21-22 111 * located at bit positions 16-18 116 * at bit positions 15-16 (PA1.1) or 14-16 (PA2.0) 160 /* on pa-linux the fpu type is not filled in by the in parisc_linux_get_fpu_type() [all …]
H A D	float.h	1 /* SPDX-License-Identifier: GPL-2.0-or-later / 3 Linux/PA-RISC Project (http://www.parisc-linux.org/) 5 * Floating-point emulation code 6 * Copyright (C) 2001 Hewlett-Packard (Paul Bame) <bame@debian.org> 26 PA header file -- do not include this header file for non-PA builds. 41 * floating-point precisions. 44 * +-------+-------+-------+-------+-------+-------+-------+-------+ 46 * +-------+-------+-------+-------+-------+-------+-------+-------+ 97 * +-------+-------+-------+-------+-------+-------+-------+-------+ 99 * +-------+-------+-------+-------+-------+-------+-------+-------+ [all …]
/linux/arch/powerpc/kernel/
H A D	vector.S	`1 /* SPDX-License-Identifier: GPL-2.0 / 7 #include <asm/asm-offsets.h> 12 #include <asm/asm-compat.h> 47 Note that on 32-bit this can only use registers that will be 48 * restored by fast_exception_return, i.e. r3 - r6, r10 and r11. 69 li r4,-1 119 #error This asm code isn't ready for 32-bit kernels 158 * usage of floating-point registers. These routines must be called 166 .long 0x3f800000 /* 1.0 in single-precision FP / 168 .long 0x3f000000 / 0.5 in single-precision FP */ [all …]`
/linux/Documentation/arch/powerpc/
H A D	elf_hwcaps.rst	`11 --------------- 46 ------------- 56 ------------- 65 ------------------- 67 HWCAPs are allocated as described in Power Architecture 64-Bit ELF V2 ABI 71 --------------------------------- 74 32-bit CPU 77 64-bit CPU (userspace may be running in 32-bit mode). 105 Embedded Floating Point single precision operations are available. 108 Embedded Floating Point double precision operations are available. [all …]`
/linux/tools/perf/pmu-events/arch/powerpc/power9/
H A D	translation.json	20 "BriefDescription": "Double-Precion or Quad-Precision instruction completed" 115 …cause the NTF instruction was a vector instruction issued to the Double Precision execution pipe a… 130 "BriefDescription": "Demand LD - L2 Miss (not L2 hit)" 140 …"BriefDescription": "The number a times the core transitioned from a stall to ICT-empty for this t… 170 "BriefDescription": "Stores completed from S2Q (2nd-level store queue)." 220 …stall because the NTF instruction was a scalar multi-cycle instruction issued to the Double Precis…
/linux/Documentation/devicetree/bindings/riscv/
H A D	extensions.yaml	`1 # SPDX-License-Identifier: (GPL-2.0 OR MIT) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: RISC-V ISA extensions 10 - Paul Walmsley <paul.walmsley@sifive.com> 11 - Palmer Dabbelt <palmer@sifive.com> 12 - Conor Dooley <conor@kernel.org> 15 RISC-V has a large number of extensions, some of which are "standard" 16 extensions, meaning they are ratified by RISC-V International, and others 36 Identifies the specific RISC-V instruction set architecture [all …]`
/linux/drivers/net/ethernet/intel/ice/
H A D	ice_ptp_hw.c	1 // SPDX-License-Identifier: GPL-2.0 25 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR, 27 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR, 29 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, 0, }, 30 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, 0, }, 35 { "GNSS-1PPS", ZL_REF4P, DPLL_PIN_TYPE_GNSS, 40 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR, 42 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR, 44 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, }, 45 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, }, [all …]
/linux/include/math-emu/
H A D	quad.h	1 /* Software floating-point emulation. 2 Definitions for IEEE Quad Precision. 23 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. / 39 #define _FP_FRACXBITS_Q (_FP_FRACTBITS_Q - _FP_FRACBITS_Q) 41 #define _FP_WFRACXBITS_Q (_FP_FRACTBITS_Q - _FP_WFRACBITS_Q) 47 ((_FP_W_TYPE)1 << (_FP_FRACBITS_Q-2) % _FP_W_TYPE_SIZE) 49 ((_FP_W_TYPE)1 << (_FP_FRACBITS_Q-1) % _FP_W_TYPE_SIZE) 63 unsigned long frac3 : _FP_FRACBITS_Q - (_FP_IMPLBIT_Q != 0)-(_FP_W_TYPE_SIZE 3); 71 unsigned long frac3 : _FP_FRACBITS_Q - (_FP_IMPLBIT_Q != 0)-(_FP_W_TYPE_SIZE * 3); 141 unsigned long frac1 : _FP_FRACBITS_Q-(_FP_IMPLBIT_Q != 0)-_FP_W_TYPE_SIZE; [all …]
/linux/drivers/staging/media/ipu3/include/uapi/
H A D	intel-ipu3.h	1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note / 2 / Copyright (C) 2017 - 2018 Intel Corporation / 11 / Vendor specific - used for IPU3 camera sub-system / 17 / from include/uapi/linux/v4l2-controls.h / 26 #define IPU3_UAPI_GRID_START_MASK ((1 << 12) - 1) 34 struct ipu3_uapi_grid_config - Grid plane config 56 * create a grid-based output, and the data is then divided into "slices". 71 * struct ipu3_uapi_awb_set_item - Memory layout for each cell in AWB 108 * struct ipu3_uapi_awb_raw_buffer - AWB raw buffer 119 * struct ipu3_uapi_awb_config_s - AWB config [all …]
/linux/lib/
H A D	vsprintf.c	1 // SPDX-License-Identifier: GPL-2.0-only 8 /* vsprintf.c -- Lars Wirzenius & Linus Torvalds. / 10 Wirzenius wrote this portably, Torvalds fucked it up :-) 15 * - changed to provide snprintf and vsnprintf functions 17 * - scnprintf and vscnprintf 23 #include <linux/clk-provider.h> 72 prefix_chars = cp - startp; in simple_strntoull() 74 rv = _parse_integer_limit(cp, base, &result, max_chars - prefix_chars); in simple_strntoull() 89 * simple_strtoull - convert a string to an unsigned long long 104 * simple_strtoul - convert a string to an unsigned long [all …]
/linux/Documentation/networking/
H A D	phy.rst	26 #. Increase code-reuse 27 #. Increase overall code-maintainability 67 for one of the users. (e.g. "git grep fsl,.-mdio arch/powerpc/boot/dts/") 72 The Reduced Gigabit Medium Independent Interface (RGMII) is a 12-pin 84 or the PCB traces insert the correct 1.5-2ns delay 97 PHY devices may offer sub-nanosecond granularity in how they allow a 99 precision may be required to account for differences in PCB trace lengths 115 PHY_INTERFACE_MODE_RGMII, it should make sure that the MAC-level delays are 130 ----------------------------------------- 197 PHY-specific flags should be set in phydev->dev_flags prior to the call [all …]
/linux/sound/pci/hda/
H A D	patch_realtek.c	1 // SPDX-License-Identifier: GPL-2.0-or-later 38 /* extra amp-initialization sequence types / 147 struct alc_spec spec = codec->spec; in coef_mutex_lock() 150 mutex_lock(&spec->coef_mutex); in coef_mutex_lock() 155 struct alc_spec spec = codec->spec; in coef_mutex_unlock() 157 mutex_unlock(&spec->coef_mutex); in coef_mutex_unlock() 209 if (val != -1) in __alc_update_coefex_idx() 229 struct alc_spec spec = codec->spec; in alc_get_coef0() 231 if (!spec->coef0) in alc_get_coef0() 232 spec->coef0 = alc_read_coef_idx(codec, 0); in alc_get_coef0() [all …]
/linux/tools/arch/x86/include/asm/
H A D	cpufeatures.h	1 /* SPDX-License-Identifier: GPL-2.0 / 6 #include <asm/required-features.h> 10 #include <asm/disabled-features.h> 16 #define NCAPINTS 22 / N 32-bit words worth of info / 17 #define NBUGINTS 2 / N 32-bit bug flags / 25 please update the table in kernel/cpu/cpuid-deps.c as well. 28 /* Intel-defined CPU features, CPUID level 0x00000001 (EDX), word 0 / 34 #define X86_FEATURE_MSR ( 032+ 5) /* "msr" Model-Specific Registers / 45 #define X86_FEATURE_PSE36 ( 032+17) /* "pse36" 36-bit PSEs / 55 #define X86_FEATURE_HT ( 032+28) /* "ht" Hyper-Threading */ [all …]
/linux/arch/x86/include/asm/
H A D	cpufeatures.h	1 /* SPDX-License-Identifier: GPL-2.0 / 6 #include <asm/required-features.h> 10 #include <asm/disabled-features.h> 16 #define NCAPINTS 22 / N 32-bit words worth of info / 17 #define NBUGINTS 2 / N 32-bit bug flags / 25 please update the table in kernel/cpu/cpuid-deps.c as well. 28 /* Intel-defined CPU features, CPUID level 0x00000001 (EDX), word 0 / 34 #define X86_FEATURE_MSR ( 032+ 5) /* "msr" Model-Specific Registers / 45 #define X86_FEATURE_PSE36 ( 032+17) /* "pse36" 36-bit PSEs / 55 #define X86_FEATURE_HT ( 032+28) /* "ht" Hyper-Threading */ [all …]
/linux/drivers/net/ethernet/qlogic/qed/
H A D	qed_debug.c	1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 4 * Copyright (c) 2019-2021 Marvell International Ltd. 157 return r[0] < (r[1] - imm[0]); in cond8() 235 /* Debug bus pre-trigger recording types / 242 / Debug bus post-trigger recording types / 290 Addresses are in bytes, sizes are in quad-regs. 398 (((1 << FIELD_BIT_SIZE(type, field)) - 1) << \ 420 (GET_FIELD((block)->flags, DBG_BLOCK_CHIP_HAS_LATENCY_EVENTS) ? 2 : 1) 422 ((block)->num_of_dbg_bus_lines + NUM_EXTRA_DBG_LINES(block)) 913 struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; in qed_grc_set_param() [all …]
/linux/drivers/gpu/drm/msm/registers/adreno/
H A D	a6xx.xml	1 <?xml version="1.0" encoding="UTF-8"?> 3 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" 4 xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> 9 <!-- 12 - "cmd" - the register is used outside of renderpass and blits, 14 - "rp_blit" - the register is used inside renderpass or blits 21 --> 23 <!-- these might be same as a5xx --> 39 <value value="0x0c" name="FMT6_1_5_5_5_UNORM"/> <!-- read only --> 60 <value value="0x31" name="FMT6_8_8_8_X8_UNORM"/> <!-- samples 1 for alpha --> [all …]
H A D	a5xx.xml	1 <?xml version="1.0" encoding="UTF-8"?> 3 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" 4 xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> 32 <value value="0x37" name="RB5_R10G10B10A2_UNORM"/> <!-- GL_RGB10_A2 --> 33 <value value="0x3a" name="RB5_R10G10B10A2_UINT"/> <!-- GL_RGB10_A2UI --> 34 <value value="0x42" name="RB5_R11G11B10_FLOAT"/> <!-- GL_R11F_G11F_B10F --> 251 <value value="8" name="BLIT_ZS"/> <!-- depth or combined depth+stencil --> 252 <value value="9" name="BLIT_S"/> <!-- separate stencil --> 255 <!-- see comment in a4xx.xml about script to extract countables from test-perf output --> 851 <!-- CP Interrupt bits --> [all …]
/linux/
H A D	MAINTAINERS	`5 --------------------------------------------------- 21 W: Web-page with status/info 23 B: URI for where to file bugs. A web-page with detailed bug 28 patches to the given subsystem. This is either an in-tree file, 29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst 46 N: [^a-z]tegra all files whose path contains tegra 64 ---------------- 83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS) 85 L: linux-scsi@vger.kernel.org 88 F: drivers/scsi/3w-* [all …]`
/linux/arch/powerpc/xmon/
H A D	ppc-opc.c	1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* ppc-opc.c -- PowerPC opcode list 3 Copyright (C) 1994-2016 Free Software Foundation, Inc. 27 inserting operands into instructions and vice-versa is kept in this 173 /* The BD field in a B form instruction when the - modifier is used. 179 /* The BD field in a B form instruction when the - modifier is used 224 /* The BO field in a B form instruction when the + or - modifier is 254 { 0x1fe, -1, NULL, NULL, PPC_OPERAND_RELATIVE \| PPC_OPERAND_SIGNED }, 411 /* If the FXM4 operand is omitted, use the sentinel value -1. */ 412 { -1, -1, NULL, NULL, 0}, [all …]