1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (C) 2021, Intel Corporation. */
3
4 #include <linux/delay.h>
5 #include <linux/iopoll.h>
6 #include "ice_common.h"
7 #include "ice_ptp_hw.h"
8 #include "ice_ptp_consts.h"
9 #include "ice_cgu_regs.h"
10
11 static struct dpll_pin_frequency ice_cgu_pin_freq_common[] = {
12 DPLL_PIN_FREQUENCY_1PPS,
13 DPLL_PIN_FREQUENCY_10MHZ,
14 };
15
16 static struct dpll_pin_frequency ice_cgu_pin_freq_1_hz[] = {
17 DPLL_PIN_FREQUENCY_1PPS,
18 };
19
20 static struct dpll_pin_frequency ice_cgu_pin_freq_10_mhz[] = {
21 DPLL_PIN_FREQUENCY_10MHZ,
22 };
23
24 static const struct ice_cgu_pin_desc ice_e810t_sfp_cgu_inputs[] = {
25 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR,
26 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
27 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR,
28 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
29 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, 0, },
30 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, 0, },
31 { "SMA1", ZL_REF3P, DPLL_PIN_TYPE_EXT,
32 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
33 { "SMA2/U.FL2", ZL_REF3N, DPLL_PIN_TYPE_EXT,
34 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
35 { "GNSS-1PPS", ZL_REF4P, DPLL_PIN_TYPE_GNSS,
36 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
37 { "OCXO", ZL_REF4N, DPLL_PIN_TYPE_INT_OSCILLATOR, 0, },
38 };
39
40 static const struct ice_cgu_pin_desc ice_e810t_qsfp_cgu_inputs[] = {
41 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR,
42 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
43 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR,
44 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
45 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, },
46 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, },
47 { "C827_1-RCLKA", ZL_REF2P, DPLL_PIN_TYPE_MUX, },
48 { "C827_1-RCLKB", ZL_REF2N, DPLL_PIN_TYPE_MUX, },
49 { "SMA1", ZL_REF3P, DPLL_PIN_TYPE_EXT,
50 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
51 { "SMA2/U.FL2", ZL_REF3N, DPLL_PIN_TYPE_EXT,
52 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
53 { "GNSS-1PPS", ZL_REF4P, DPLL_PIN_TYPE_GNSS,
54 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
55 { "OCXO", ZL_REF4N, DPLL_PIN_TYPE_INT_OSCILLATOR, },
56 };
57
58 static const struct ice_cgu_pin_desc ice_e810t_sfp_cgu_outputs[] = {
59 { "REF-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT,
60 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
61 { "REF-SMA2/U.FL2", ZL_OUT1, DPLL_PIN_TYPE_EXT,
62 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
63 { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, },
64 { "MAC-CLK", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, },
65 { "CVL-SDP21", ZL_OUT4, DPLL_PIN_TYPE_EXT,
66 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
67 { "CVL-SDP23", ZL_OUT5, DPLL_PIN_TYPE_EXT,
68 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
69 };
70
71 static const struct ice_cgu_pin_desc ice_e810t_qsfp_cgu_outputs[] = {
72 { "REF-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT,
73 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
74 { "REF-SMA2/U.FL2", ZL_OUT1, DPLL_PIN_TYPE_EXT,
75 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
76 { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
77 { "PHY2-CLK", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
78 { "MAC-CLK", ZL_OUT4, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
79 { "CVL-SDP21", ZL_OUT5, DPLL_PIN_TYPE_EXT,
80 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
81 { "CVL-SDP23", ZL_OUT6, DPLL_PIN_TYPE_EXT,
82 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
83 };
84
85 static const struct ice_cgu_pin_desc ice_e823_si_cgu_inputs[] = {
86 { "NONE", SI_REF0P, 0, 0 },
87 { "NONE", SI_REF0N, 0, 0 },
88 { "SYNCE0_DP", SI_REF1P, DPLL_PIN_TYPE_MUX, 0 },
89 { "SYNCE0_DN", SI_REF1N, DPLL_PIN_TYPE_MUX, 0 },
90 { "EXT_CLK_SYNC", SI_REF2P, DPLL_PIN_TYPE_EXT,
91 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
92 { "NONE", SI_REF2N, 0, 0 },
93 { "EXT_PPS_OUT", SI_REF3, DPLL_PIN_TYPE_EXT,
94 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
95 { "INT_PPS_OUT", SI_REF4, DPLL_PIN_TYPE_EXT,
96 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
97 };
98
99 static const struct ice_cgu_pin_desc ice_e823_si_cgu_outputs[] = {
100 { "1588-TIME_SYNC", SI_OUT0, DPLL_PIN_TYPE_EXT,
101 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
102 { "PHY-CLK", SI_OUT1, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
103 { "10MHZ-SMA2", SI_OUT2, DPLL_PIN_TYPE_EXT,
104 ARRAY_SIZE(ice_cgu_pin_freq_10_mhz), ice_cgu_pin_freq_10_mhz },
105 { "PPS-SMA1", SI_OUT3, DPLL_PIN_TYPE_EXT,
106 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
107 };
108
109 static const struct ice_cgu_pin_desc ice_e823_zl_cgu_inputs[] = {
110 { "NONE", ZL_REF0P, 0, 0 },
111 { "INT_PPS_OUT", ZL_REF0N, DPLL_PIN_TYPE_EXT,
112 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
113 { "SYNCE0_DP", ZL_REF1P, DPLL_PIN_TYPE_MUX, 0 },
114 { "SYNCE0_DN", ZL_REF1N, DPLL_PIN_TYPE_MUX, 0 },
115 { "NONE", ZL_REF2P, 0, 0 },
116 { "NONE", ZL_REF2N, 0, 0 },
117 { "EXT_CLK_SYNC", ZL_REF3P, DPLL_PIN_TYPE_EXT,
118 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
119 { "NONE", ZL_REF3N, 0, 0 },
120 { "EXT_PPS_OUT", ZL_REF4P, DPLL_PIN_TYPE_EXT,
121 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
122 { "OCXO", ZL_REF4N, DPLL_PIN_TYPE_INT_OSCILLATOR, 0 },
123 };
124
125 static const struct ice_cgu_pin_desc ice_e823_zl_cgu_outputs[] = {
126 { "PPS-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT,
127 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
128 { "10MHZ-SMA2", ZL_OUT1, DPLL_PIN_TYPE_EXT,
129 ARRAY_SIZE(ice_cgu_pin_freq_10_mhz), ice_cgu_pin_freq_10_mhz },
130 { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
131 { "1588-TIME_REF", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
132 { "CPK-TIME_SYNC", ZL_OUT4, DPLL_PIN_TYPE_EXT,
133 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
134 { "NONE", ZL_OUT5, 0, 0 },
135 };
136
137 /* Low level functions for interacting with and managing the device clock used
138 * for the Precision Time Protocol.
139 *
140 * The ice hardware represents the current time using three registers:
141 *
142 * GLTSYN_TIME_H GLTSYN_TIME_L GLTSYN_TIME_R
143 * +---------------+ +---------------+ +---------------+
144 * | 32 bits | | 32 bits | | 32 bits |
145 * +---------------+ +---------------+ +---------------+
146 *
147 * The registers are incremented every clock tick using a 40bit increment
148 * value defined over two registers:
149 *
150 * GLTSYN_INCVAL_H GLTSYN_INCVAL_L
151 * +---------------+ +---------------+
152 * | 8 bit s | | 32 bits |
153 * +---------------+ +---------------+
154 *
155 * The increment value is added to the GLSTYN_TIME_R and GLSTYN_TIME_L
156 * registers every clock source tick. Depending on the specific device
157 * configuration, the clock source frequency could be one of a number of
158 * values.
159 *
160 * For E810 devices, the increment frequency is 812.5 MHz
161 *
162 * For E822 devices the clock can be derived from different sources, and the
163 * increment has an effective frequency of one of the following:
164 * - 823.4375 MHz
165 * - 783.36 MHz
166 * - 796.875 MHz
167 * - 816 MHz
168 * - 830.078125 MHz
169 * - 783.36 MHz
170 *
171 * The hardware captures timestamps in the PHY for incoming packets, and for
172 * outgoing packets on request. To support this, the PHY maintains a timer
173 * that matches the lower 64 bits of the global source timer.
174 *
175 * In order to ensure that the PHY timers and the source timer are equivalent,
176 * shadow registers are used to prepare the desired initial values. A special
177 * sync command is issued to trigger copying from the shadow registers into
178 * the appropriate source and PHY registers simultaneously.
179 *
180 * The driver supports devices which have different PHYs with subtly different
181 * mechanisms to program and control the timers. We divide the devices into
182 * families named after the first major device, E810 and similar devices, and
183 * E822 and similar devices.
184 *
185 * - E822 based devices have additional support for fine grained Vernier
186 * calibration which requires significant setup
187 * - The layout of timestamp data in the PHY register blocks is different
188 * - The way timer synchronization commands are issued is different.
189 *
190 * To support this, very low level functions have an e810 or e822 suffix
191 * indicating what type of device they work on. Higher level abstractions for
192 * tasks that can be done on both devices do not have the suffix and will
193 * correctly look up the appropriate low level function when running.
194 *
195 * Functions which only make sense on a single device family may not have
196 * a suitable generic implementation
197 */
198
199 /**
200 * ice_get_ptp_src_clock_index - determine source clock index
201 * @hw: pointer to HW struct
202 *
203 * Determine the source clock index currently in use, based on device
204 * capabilities reported during initialization.
205 */
ice_get_ptp_src_clock_index(struct ice_hw * hw)206 u8 ice_get_ptp_src_clock_index(struct ice_hw *hw)
207 {
208 return hw->func_caps.ts_func_info.tmr_index_assoc;
209 }
210
211 /**
212 * ice_ptp_read_src_incval - Read source timer increment value
213 * @hw: pointer to HW struct
214 *
215 * Read the increment value of the source timer and return it.
216 */
ice_ptp_read_src_incval(struct ice_hw * hw)217 static u64 ice_ptp_read_src_incval(struct ice_hw *hw)
218 {
219 u32 lo, hi;
220 u8 tmr_idx;
221
222 tmr_idx = ice_get_ptp_src_clock_index(hw);
223
224 lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx));
225 hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx));
226
227 return ((u64)(hi & INCVAL_HIGH_M) << 32) | lo;
228 }
229
230 /**
231 * ice_read_cgu_reg_e82x - Read a CGU register
232 * @hw: pointer to the HW struct
233 * @addr: Register address to read
234 * @val: storage for register value read
235 *
236 * Read the contents of a register of the Clock Generation Unit. Only
237 * applicable to E822 devices.
238 *
239 * Return: 0 on success, other error codes when failed to read from CGU
240 */
ice_read_cgu_reg_e82x(struct ice_hw * hw,u32 addr,u32 * val)241 static int ice_read_cgu_reg_e82x(struct ice_hw *hw, u32 addr, u32 *val)
242 {
243 struct ice_sbq_msg_input cgu_msg = {
244 .opcode = ice_sbq_msg_rd,
245 .dest_dev = cgu,
246 .msg_addr_low = addr
247 };
248 int err;
249
250 err = ice_sbq_rw_reg(hw, &cgu_msg, ICE_AQ_FLAG_RD);
251 if (err) {
252 ice_debug(hw, ICE_DBG_PTP, "Failed to read CGU register 0x%04x, err %d\n",
253 addr, err);
254 return err;
255 }
256
257 *val = cgu_msg.data;
258
259 return 0;
260 }
261
262 /**
263 * ice_write_cgu_reg_e82x - Write a CGU register
264 * @hw: pointer to the HW struct
265 * @addr: Register address to write
266 * @val: value to write into the register
267 *
268 * Write the specified value to a register of the Clock Generation Unit. Only
269 * applicable to E822 devices.
270 *
271 * Return: 0 on success, other error codes when failed to write to CGU
272 */
ice_write_cgu_reg_e82x(struct ice_hw * hw,u32 addr,u32 val)273 static int ice_write_cgu_reg_e82x(struct ice_hw *hw, u32 addr, u32 val)
274 {
275 struct ice_sbq_msg_input cgu_msg = {
276 .opcode = ice_sbq_msg_wr,
277 .dest_dev = cgu,
278 .msg_addr_low = addr,
279 .data = val
280 };
281 int err;
282
283 err = ice_sbq_rw_reg(hw, &cgu_msg, ICE_AQ_FLAG_RD);
284 if (err) {
285 ice_debug(hw, ICE_DBG_PTP, "Failed to write CGU register 0x%04x, err %d\n",
286 addr, err);
287 return err;
288 }
289
290 return err;
291 }
292
293 /**
294 * ice_clk_freq_str - Convert time_ref_freq to string
295 * @clk_freq: Clock frequency
296 *
297 * Return: specified TIME_REF clock frequency converted to a string
298 */
ice_clk_freq_str(enum ice_time_ref_freq clk_freq)299 static const char *ice_clk_freq_str(enum ice_time_ref_freq clk_freq)
300 {
301 switch (clk_freq) {
302 case ICE_TIME_REF_FREQ_25_000:
303 return "25 MHz";
304 case ICE_TIME_REF_FREQ_122_880:
305 return "122.88 MHz";
306 case ICE_TIME_REF_FREQ_125_000:
307 return "125 MHz";
308 case ICE_TIME_REF_FREQ_153_600:
309 return "153.6 MHz";
310 case ICE_TIME_REF_FREQ_156_250:
311 return "156.25 MHz";
312 case ICE_TIME_REF_FREQ_245_760:
313 return "245.76 MHz";
314 default:
315 return "Unknown";
316 }
317 }
318
319 /**
320 * ice_clk_src_str - Convert time_ref_src to string
321 * @clk_src: Clock source
322 *
323 * Return: specified clock source converted to its string name
324 */
ice_clk_src_str(enum ice_clk_src clk_src)325 static const char *ice_clk_src_str(enum ice_clk_src clk_src)
326 {
327 switch (clk_src) {
328 case ICE_CLK_SRC_TCXO:
329 return "TCXO";
330 case ICE_CLK_SRC_TIME_REF:
331 return "TIME_REF";
332 default:
333 return "Unknown";
334 }
335 }
336
337 /**
338 * ice_cfg_cgu_pll_e82x - Configure the Clock Generation Unit
339 * @hw: pointer to the HW struct
340 * @clk_freq: Clock frequency to program
341 * @clk_src: Clock source to select (TIME_REF, or TCXO)
342 *
343 * Configure the Clock Generation Unit with the desired clock frequency and
344 * time reference, enabling the PLL which drives the PTP hardware clock.
345 *
346 * Return:
347 * * %0 - success
348 * * %-EINVAL - input parameters are incorrect
349 * * %-EBUSY - failed to lock TS PLL
350 * * %other - CGU read/write failure
351 */
ice_cfg_cgu_pll_e82x(struct ice_hw * hw,enum ice_time_ref_freq clk_freq,enum ice_clk_src clk_src)352 static int ice_cfg_cgu_pll_e82x(struct ice_hw *hw,
353 enum ice_time_ref_freq clk_freq,
354 enum ice_clk_src clk_src)
355 {
356 union tspll_ro_bwm_lf bwm_lf;
357 union nac_cgu_dword19 dw19;
358 union nac_cgu_dword22 dw22;
359 union nac_cgu_dword24 dw24;
360 union nac_cgu_dword9 dw9;
361 int err;
362
363 if (clk_freq >= NUM_ICE_TIME_REF_FREQ) {
364 dev_warn(ice_hw_to_dev(hw), "Invalid TIME_REF frequency %u\n",
365 clk_freq);
366 return -EINVAL;
367 }
368
369 if (clk_src >= NUM_ICE_CLK_SRC) {
370 dev_warn(ice_hw_to_dev(hw), "Invalid clock source %u\n",
371 clk_src);
372 return -EINVAL;
373 }
374
375 if (clk_src == ICE_CLK_SRC_TCXO &&
376 clk_freq != ICE_TIME_REF_FREQ_25_000) {
377 dev_warn(ice_hw_to_dev(hw),
378 "TCXO only supports 25 MHz frequency\n");
379 return -EINVAL;
380 }
381
382 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD9, &dw9.val);
383 if (err)
384 return err;
385
386 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD24, &dw24.val);
387 if (err)
388 return err;
389
390 err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_BWM_LF, &bwm_lf.val);
391 if (err)
392 return err;
393
394 /* Log the current clock configuration */
395 ice_debug(hw, ICE_DBG_PTP, "Current CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
396 dw24.ts_pll_enable ? "enabled" : "disabled",
397 ice_clk_src_str(dw24.time_ref_sel),
398 ice_clk_freq_str(dw9.time_ref_freq_sel),
399 bwm_lf.plllock_true_lock_cri ? "locked" : "unlocked");
400
401 /* Disable the PLL before changing the clock source or frequency */
402 if (dw24.ts_pll_enable) {
403 dw24.ts_pll_enable = 0;
404
405 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val);
406 if (err)
407 return err;
408 }
409
410 /* Set the frequency */
411 dw9.time_ref_freq_sel = clk_freq;
412 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD9, dw9.val);
413 if (err)
414 return err;
415
416 /* Configure the TS PLL feedback divisor */
417 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD19, &dw19.val);
418 if (err)
419 return err;
420
421 dw19.tspll_fbdiv_intgr = e822_cgu_params[clk_freq].feedback_div;
422 dw19.tspll_ndivratio = 1;
423
424 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD19, dw19.val);
425 if (err)
426 return err;
427
428 /* Configure the TS PLL post divisor */
429 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD22, &dw22.val);
430 if (err)
431 return err;
432
433 dw22.time1588clk_div = e822_cgu_params[clk_freq].post_pll_div;
434 dw22.time1588clk_sel_div2 = 0;
435
436 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD22, dw22.val);
437 if (err)
438 return err;
439
440 /* Configure the TS PLL pre divisor and clock source */
441 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD24, &dw24.val);
442 if (err)
443 return err;
444
445 dw24.ref1588_ck_div = e822_cgu_params[clk_freq].refclk_pre_div;
446 dw24.tspll_fbdiv_frac = e822_cgu_params[clk_freq].frac_n_div;
447 dw24.time_ref_sel = clk_src;
448
449 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val);
450 if (err)
451 return err;
452
453 /* Finally, enable the PLL */
454 dw24.ts_pll_enable = 1;
455
456 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val);
457 if (err)
458 return err;
459
460 /* Wait to verify if the PLL locks */
461 usleep_range(1000, 5000);
462
463 err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_BWM_LF, &bwm_lf.val);
464 if (err)
465 return err;
466
467 if (!bwm_lf.plllock_true_lock_cri) {
468 dev_warn(ice_hw_to_dev(hw), "CGU PLL failed to lock\n");
469 return -EBUSY;
470 }
471
472 /* Log the current clock configuration */
473 ice_debug(hw, ICE_DBG_PTP, "New CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
474 dw24.ts_pll_enable ? "enabled" : "disabled",
475 ice_clk_src_str(dw24.time_ref_sel),
476 ice_clk_freq_str(dw9.time_ref_freq_sel),
477 bwm_lf.plllock_true_lock_cri ? "locked" : "unlocked");
478
479 return 0;
480 }
481
482 /**
483 * ice_cfg_cgu_pll_e825c - Configure the Clock Generation Unit for E825-C
484 * @hw: pointer to the HW struct
485 * @clk_freq: Clock frequency to program
486 * @clk_src: Clock source to select (TIME_REF, or TCXO)
487 *
488 * Configure the Clock Generation Unit with the desired clock frequency and
489 * time reference, enabling the PLL which drives the PTP hardware clock.
490 *
491 * Return:
492 * * %0 - success
493 * * %-EINVAL - input parameters are incorrect
494 * * %-EBUSY - failed to lock TS PLL
495 * * %other - CGU read/write failure
496 */
ice_cfg_cgu_pll_e825c(struct ice_hw * hw,enum ice_time_ref_freq clk_freq,enum ice_clk_src clk_src)497 static int ice_cfg_cgu_pll_e825c(struct ice_hw *hw,
498 enum ice_time_ref_freq clk_freq,
499 enum ice_clk_src clk_src)
500 {
501 union tspll_ro_lock_e825c ro_lock;
502 union nac_cgu_dword16_e825c dw16;
503 union nac_cgu_dword23_e825c dw23;
504 union nac_cgu_dword19 dw19;
505 union nac_cgu_dword22 dw22;
506 union nac_cgu_dword24 dw24;
507 union nac_cgu_dword9 dw9;
508 int err;
509
510 if (clk_freq >= NUM_ICE_TIME_REF_FREQ) {
511 dev_warn(ice_hw_to_dev(hw), "Invalid TIME_REF frequency %u\n",
512 clk_freq);
513 return -EINVAL;
514 }
515
516 if (clk_src >= NUM_ICE_CLK_SRC) {
517 dev_warn(ice_hw_to_dev(hw), "Invalid clock source %u\n",
518 clk_src);
519 return -EINVAL;
520 }
521
522 if (clk_src == ICE_CLK_SRC_TCXO &&
523 clk_freq != ICE_TIME_REF_FREQ_156_250) {
524 dev_warn(ice_hw_to_dev(hw),
525 "TCXO only supports 156.25 MHz frequency\n");
526 return -EINVAL;
527 }
528
529 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD9, &dw9.val);
530 if (err)
531 return err;
532
533 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD24, &dw24.val);
534 if (err)
535 return err;
536
537 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD16_E825C, &dw16.val);
538 if (err)
539 return err;
540
541 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, &dw23.val);
542 if (err)
543 return err;
544
545 err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_LOCK_E825C, &ro_lock.val);
546 if (err)
547 return err;
548
549 /* Log the current clock configuration */
550 ice_debug(hw, ICE_DBG_PTP, "Current CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
551 dw24.ts_pll_enable ? "enabled" : "disabled",
552 ice_clk_src_str(dw23.time_ref_sel),
553 ice_clk_freq_str(dw9.time_ref_freq_sel),
554 ro_lock.plllock_true_lock_cri ? "locked" : "unlocked");
555
556 /* Disable the PLL before changing the clock source or frequency */
557 if (dw23.ts_pll_enable) {
558 dw23.ts_pll_enable = 0;
559
560 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C,
561 dw23.val);
562 if (err)
563 return err;
564 }
565
566 /* Set the frequency */
567 dw9.time_ref_freq_sel = clk_freq;
568
569 /* Enable the correct receiver */
570 if (clk_src == ICE_CLK_SRC_TCXO) {
571 dw9.time_ref_en = 0;
572 dw9.clk_eref0_en = 1;
573 } else {
574 dw9.time_ref_en = 1;
575 dw9.clk_eref0_en = 0;
576 }
577 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD9, dw9.val);
578 if (err)
579 return err;
580
581 /* Choose the referenced frequency */
582 dw16.tspll_ck_refclkfreq =
583 e825c_cgu_params[clk_freq].tspll_ck_refclkfreq;
584 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD16_E825C, dw16.val);
585 if (err)
586 return err;
587
588 /* Configure the TS PLL feedback divisor */
589 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD19, &dw19.val);
590 if (err)
591 return err;
592
593 dw19.tspll_fbdiv_intgr =
594 e825c_cgu_params[clk_freq].tspll_fbdiv_intgr;
595 dw19.tspll_ndivratio =
596 e825c_cgu_params[clk_freq].tspll_ndivratio;
597
598 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD19, dw19.val);
599 if (err)
600 return err;
601
602 /* Configure the TS PLL post divisor */
603 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD22, &dw22.val);
604 if (err)
605 return err;
606
607 /* These two are constant for E825C */
608 dw22.time1588clk_div = 5;
609 dw22.time1588clk_sel_div2 = 0;
610
611 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD22, dw22.val);
612 if (err)
613 return err;
614
615 /* Configure the TS PLL pre divisor and clock source */
616 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, &dw23.val);
617 if (err)
618 return err;
619
620 dw23.ref1588_ck_div =
621 e825c_cgu_params[clk_freq].ref1588_ck_div;
622 dw23.time_ref_sel = clk_src;
623
624 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, dw23.val);
625 if (err)
626 return err;
627
628 dw24.tspll_fbdiv_frac =
629 e825c_cgu_params[clk_freq].tspll_fbdiv_frac;
630
631 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val);
632 if (err)
633 return err;
634
635 /* Finally, enable the PLL */
636 dw23.ts_pll_enable = 1;
637
638 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, dw23.val);
639 if (err)
640 return err;
641
642 /* Wait to verify if the PLL locks */
643 usleep_range(1000, 5000);
644
645 err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_LOCK_E825C, &ro_lock.val);
646 if (err)
647 return err;
648
649 if (!ro_lock.plllock_true_lock_cri) {
650 dev_warn(ice_hw_to_dev(hw), "CGU PLL failed to lock\n");
651 return -EBUSY;
652 }
653
654 /* Log the current clock configuration */
655 ice_debug(hw, ICE_DBG_PTP, "New CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n",
656 dw24.ts_pll_enable ? "enabled" : "disabled",
657 ice_clk_src_str(dw23.time_ref_sel),
658 ice_clk_freq_str(dw9.time_ref_freq_sel),
659 ro_lock.plllock_true_lock_cri ? "locked" : "unlocked");
660
661 return 0;
662 }
663
664 /**
665 * ice_cfg_cgu_pll_dis_sticky_bits_e82x - disable TS PLL sticky bits
666 * @hw: pointer to the HW struct
667 *
668 * Configure the Clock Generation Unit TS PLL sticky bits so they don't latch on
669 * losing TS PLL lock, but always show current state.
670 *
671 * Return: 0 on success, other error codes when failed to read/write CGU
672 */
ice_cfg_cgu_pll_dis_sticky_bits_e82x(struct ice_hw * hw)673 static int ice_cfg_cgu_pll_dis_sticky_bits_e82x(struct ice_hw *hw)
674 {
675 union tspll_cntr_bist_settings cntr_bist;
676 int err;
677
678 err = ice_read_cgu_reg_e82x(hw, TSPLL_CNTR_BIST_SETTINGS,
679 &cntr_bist.val);
680 if (err)
681 return err;
682
683 /* Disable sticky lock detection so lock err reported is accurate */
684 cntr_bist.i_plllock_sel_0 = 0;
685 cntr_bist.i_plllock_sel_1 = 0;
686
687 return ice_write_cgu_reg_e82x(hw, TSPLL_CNTR_BIST_SETTINGS,
688 cntr_bist.val);
689 }
690
691 /**
692 * ice_cfg_cgu_pll_dis_sticky_bits_e825c - disable TS PLL sticky bits for E825-C
693 * @hw: pointer to the HW struct
694 *
695 * Configure the Clock Generation Unit TS PLL sticky bits so they don't latch on
696 * losing TS PLL lock, but always show current state.
697 *
698 * Return: 0 on success, other error codes when failed to read/write CGU
699 */
ice_cfg_cgu_pll_dis_sticky_bits_e825c(struct ice_hw * hw)700 static int ice_cfg_cgu_pll_dis_sticky_bits_e825c(struct ice_hw *hw)
701 {
702 union tspll_bw_tdc_e825c bw_tdc;
703 int err;
704
705 err = ice_read_cgu_reg_e82x(hw, TSPLL_BW_TDC_E825C, &bw_tdc.val);
706 if (err)
707 return err;
708
709 bw_tdc.i_plllock_sel_1_0 = 0;
710
711 return ice_write_cgu_reg_e82x(hw, TSPLL_BW_TDC_E825C, bw_tdc.val);
712 }
713
714 /**
715 * ice_init_cgu_e82x - Initialize CGU with settings from firmware
716 * @hw: pointer to the HW structure
717 *
718 * Initialize the Clock Generation Unit of the E822 device.
719 *
720 * Return: 0 on success, other error codes when failed to read/write/cfg CGU
721 */
ice_init_cgu_e82x(struct ice_hw * hw)722 static int ice_init_cgu_e82x(struct ice_hw *hw)
723 {
724 struct ice_ts_func_info *ts_info = &hw->func_caps.ts_func_info;
725 int err;
726
727 /* Disable sticky lock detection so lock err reported is accurate */
728 if (ice_is_e825c(hw))
729 err = ice_cfg_cgu_pll_dis_sticky_bits_e825c(hw);
730 else
731 err = ice_cfg_cgu_pll_dis_sticky_bits_e82x(hw);
732 if (err)
733 return err;
734
735 /* Configure the CGU PLL using the parameters from the function
736 * capabilities.
737 */
738 if (ice_is_e825c(hw))
739 err = ice_cfg_cgu_pll_e825c(hw, ts_info->time_ref,
740 (enum ice_clk_src)ts_info->clk_src);
741 else
742 err = ice_cfg_cgu_pll_e82x(hw, ts_info->time_ref,
743 (enum ice_clk_src)ts_info->clk_src);
744
745 return err;
746 }
747
748 /**
749 * ice_ptp_tmr_cmd_to_src_reg - Convert to source timer command value
750 * @hw: pointer to HW struct
751 * @cmd: Timer command
752 *
753 * Return: the source timer command register value for the given PTP timer
754 * command.
755 */
ice_ptp_tmr_cmd_to_src_reg(struct ice_hw * hw,enum ice_ptp_tmr_cmd cmd)756 static u32 ice_ptp_tmr_cmd_to_src_reg(struct ice_hw *hw,
757 enum ice_ptp_tmr_cmd cmd)
758 {
759 u32 cmd_val, tmr_idx;
760
761 switch (cmd) {
762 case ICE_PTP_INIT_TIME:
763 cmd_val = GLTSYN_CMD_INIT_TIME;
764 break;
765 case ICE_PTP_INIT_INCVAL:
766 cmd_val = GLTSYN_CMD_INIT_INCVAL;
767 break;
768 case ICE_PTP_ADJ_TIME:
769 cmd_val = GLTSYN_CMD_ADJ_TIME;
770 break;
771 case ICE_PTP_ADJ_TIME_AT_TIME:
772 cmd_val = GLTSYN_CMD_ADJ_INIT_TIME;
773 break;
774 case ICE_PTP_NOP:
775 case ICE_PTP_READ_TIME:
776 cmd_val = GLTSYN_CMD_READ_TIME;
777 break;
778 default:
779 dev_warn(ice_hw_to_dev(hw),
780 "Ignoring unrecognized timer command %u\n", cmd);
781 cmd_val = 0;
782 }
783
784 tmr_idx = ice_get_ptp_src_clock_index(hw);
785
786 return tmr_idx << SEL_CPK_SRC | cmd_val;
787 }
788
789 /**
790 * ice_ptp_tmr_cmd_to_port_reg- Convert to port timer command value
791 * @hw: pointer to HW struct
792 * @cmd: Timer command
793 *
794 * Note that some hardware families use a different command register value for
795 * the PHY ports, while other hardware families use the same register values
796 * as the source timer.
797 *
798 * Return: the PHY port timer command register value for the given PTP timer
799 * command.
800 */
ice_ptp_tmr_cmd_to_port_reg(struct ice_hw * hw,enum ice_ptp_tmr_cmd cmd)801 static u32 ice_ptp_tmr_cmd_to_port_reg(struct ice_hw *hw,
802 enum ice_ptp_tmr_cmd cmd)
803 {
804 u32 cmd_val, tmr_idx;
805
806 /* Certain hardware families share the same register values for the
807 * port register and source timer register.
808 */
809 switch (hw->ptp.phy_model) {
810 case ICE_PHY_E810:
811 return ice_ptp_tmr_cmd_to_src_reg(hw, cmd) & TS_CMD_MASK_E810;
812 default:
813 break;
814 }
815
816 switch (cmd) {
817 case ICE_PTP_INIT_TIME:
818 cmd_val = PHY_CMD_INIT_TIME;
819 break;
820 case ICE_PTP_INIT_INCVAL:
821 cmd_val = PHY_CMD_INIT_INCVAL;
822 break;
823 case ICE_PTP_ADJ_TIME:
824 cmd_val = PHY_CMD_ADJ_TIME;
825 break;
826 case ICE_PTP_ADJ_TIME_AT_TIME:
827 cmd_val = PHY_CMD_ADJ_TIME_AT_TIME;
828 break;
829 case ICE_PTP_READ_TIME:
830 cmd_val = PHY_CMD_READ_TIME;
831 break;
832 case ICE_PTP_NOP:
833 cmd_val = 0;
834 break;
835 default:
836 dev_warn(ice_hw_to_dev(hw),
837 "Ignoring unrecognized timer command %u\n", cmd);
838 cmd_val = 0;
839 }
840
841 tmr_idx = ice_get_ptp_src_clock_index(hw);
842
843 return tmr_idx << SEL_PHY_SRC | cmd_val;
844 }
845
846 /**
847 * ice_ptp_src_cmd - Prepare source timer for a timer command
848 * @hw: pointer to HW structure
849 * @cmd: Timer command
850 *
851 * Prepare the source timer for an upcoming timer sync command.
852 */
ice_ptp_src_cmd(struct ice_hw * hw,enum ice_ptp_tmr_cmd cmd)853 void ice_ptp_src_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd)
854 {
855 u32 cmd_val = ice_ptp_tmr_cmd_to_src_reg(hw, cmd);
856
857 wr32(hw, GLTSYN_CMD, cmd_val);
858 }
859
860 /**
861 * ice_ptp_exec_tmr_cmd - Execute all prepared timer commands
862 * @hw: pointer to HW struct
863 *
864 * Write the SYNC_EXEC_CMD bit to the GLTSYN_CMD_SYNC register, and flush the
865 * write immediately. This triggers the hardware to begin executing all of the
866 * source and PHY timer commands synchronously.
867 */
ice_ptp_exec_tmr_cmd(struct ice_hw * hw)868 static void ice_ptp_exec_tmr_cmd(struct ice_hw *hw)
869 {
870 struct ice_pf *pf = container_of(hw, struct ice_pf, hw);
871
872 guard(spinlock)(&pf->adapter->ptp_gltsyn_time_lock);
873 wr32(hw, GLTSYN_CMD_SYNC, SYNC_EXEC_CMD);
874 ice_flush(hw);
875 }
876
877 /* 56G PHY device functions
878 *
879 * The following functions operate on devices with the ETH 56G PHY.
880 */
881
882 /**
883 * ice_write_phy_eth56g - Write a PHY port register
884 * @hw: pointer to the HW struct
885 * @phy_idx: PHY index
886 * @addr: PHY register address
887 * @val: Value to write
888 *
889 * Return: 0 on success, other error codes when failed to write to PHY
890 */
ice_write_phy_eth56g(struct ice_hw * hw,u8 phy_idx,u32 addr,u32 val)891 static int ice_write_phy_eth56g(struct ice_hw *hw, u8 phy_idx, u32 addr,
892 u32 val)
893 {
894 struct ice_sbq_msg_input phy_msg;
895 int err;
896
897 phy_msg.opcode = ice_sbq_msg_wr;
898
899 phy_msg.msg_addr_low = lower_16_bits(addr);
900 phy_msg.msg_addr_high = upper_16_bits(addr);
901
902 phy_msg.data = val;
903 phy_msg.dest_dev = hw->ptp.phy.eth56g.phy_addr[phy_idx];
904
905 err = ice_sbq_rw_reg(hw, &phy_msg, ICE_AQ_FLAG_RD);
906
907 if (err)
908 ice_debug(hw, ICE_DBG_PTP, "PTP failed to send msg to phy %d\n",
909 err);
910
911 return err;
912 }
913
914 /**
915 * ice_read_phy_eth56g - Read a PHY port register
916 * @hw: pointer to the HW struct
917 * @phy_idx: PHY index
918 * @addr: PHY register address
919 * @val: Value to write
920 *
921 * Return: 0 on success, other error codes when failed to read from PHY
922 */
ice_read_phy_eth56g(struct ice_hw * hw,u8 phy_idx,u32 addr,u32 * val)923 static int ice_read_phy_eth56g(struct ice_hw *hw, u8 phy_idx, u32 addr,
924 u32 *val)
925 {
926 struct ice_sbq_msg_input phy_msg;
927 int err;
928
929 phy_msg.opcode = ice_sbq_msg_rd;
930
931 phy_msg.msg_addr_low = lower_16_bits(addr);
932 phy_msg.msg_addr_high = upper_16_bits(addr);
933
934 phy_msg.data = 0;
935 phy_msg.dest_dev = hw->ptp.phy.eth56g.phy_addr[phy_idx];
936
937 err = ice_sbq_rw_reg(hw, &phy_msg, ICE_AQ_FLAG_RD);
938 if (err) {
939 ice_debug(hw, ICE_DBG_PTP, "PTP failed to send msg to phy %d\n",
940 err);
941 return err;
942 }
943
944 *val = phy_msg.data;
945
946 return 0;
947 }
948
949 /**
950 * ice_phy_res_address_eth56g - Calculate a PHY port register address
951 * @port: Port number to be written
952 * @res_type: resource type (register/memory)
953 * @offset: Offset from PHY port register base
954 * @addr: The result address
955 *
956 * Return:
957 * * %0 - success
958 * * %EINVAL - invalid port number or resource type
959 */
ice_phy_res_address_eth56g(u8 port,enum eth56g_res_type res_type,u32 offset,u32 * addr)960 static int ice_phy_res_address_eth56g(u8 port, enum eth56g_res_type res_type,
961 u32 offset, u32 *addr)
962 {
963 u8 lane = port % ICE_PORTS_PER_QUAD;
964 u8 phy = ICE_GET_QUAD_NUM(port);
965
966 if (res_type >= NUM_ETH56G_PHY_RES)
967 return -EINVAL;
968
969 *addr = eth56g_phy_res[res_type].base[phy] +
970 lane * eth56g_phy_res[res_type].step + offset;
971 return 0;
972 }
973
974 /**
975 * ice_write_port_eth56g - Write a PHY port register
976 * @hw: pointer to the HW struct
977 * @offset: PHY register offset
978 * @port: Port number
979 * @val: Value to write
980 * @res_type: resource type (register/memory)
981 *
982 * Return:
983 * * %0 - success
984 * * %EINVAL - invalid port number or resource type
985 * * %other - failed to write to PHY
986 */
ice_write_port_eth56g(struct ice_hw * hw,u8 port,u32 offset,u32 val,enum eth56g_res_type res_type)987 static int ice_write_port_eth56g(struct ice_hw *hw, u8 port, u32 offset,
988 u32 val, enum eth56g_res_type res_type)
989 {
990 u8 phy_port = port % hw->ptp.ports_per_phy;
991 u8 phy_idx = port / hw->ptp.ports_per_phy;
992 u32 addr;
993 int err;
994
995 if (port >= hw->ptp.num_lports)
996 return -EINVAL;
997
998 err = ice_phy_res_address_eth56g(phy_port, res_type, offset, &addr);
999 if (err)
1000 return err;
1001
1002 return ice_write_phy_eth56g(hw, phy_idx, addr, val);
1003 }
1004
1005 /**
1006 * ice_read_port_eth56g - Read a PHY port register
1007 * @hw: pointer to the HW struct
1008 * @offset: PHY register offset
1009 * @port: Port number
1010 * @val: Value to write
1011 * @res_type: resource type (register/memory)
1012 *
1013 * Return:
1014 * * %0 - success
1015 * * %EINVAL - invalid port number or resource type
1016 * * %other - failed to read from PHY
1017 */
ice_read_port_eth56g(struct ice_hw * hw,u8 port,u32 offset,u32 * val,enum eth56g_res_type res_type)1018 static int ice_read_port_eth56g(struct ice_hw *hw, u8 port, u32 offset,
1019 u32 *val, enum eth56g_res_type res_type)
1020 {
1021 u8 phy_port = port % hw->ptp.ports_per_phy;
1022 u8 phy_idx = port / hw->ptp.ports_per_phy;
1023 u32 addr;
1024 int err;
1025
1026 if (port >= hw->ptp.num_lports)
1027 return -EINVAL;
1028
1029 err = ice_phy_res_address_eth56g(phy_port, res_type, offset, &addr);
1030 if (err)
1031 return err;
1032
1033 return ice_read_phy_eth56g(hw, phy_idx, addr, val);
1034 }
1035
1036 /**
1037 * ice_write_ptp_reg_eth56g - Write a PHY port register
1038 * @hw: pointer to the HW struct
1039 * @port: Port number to be written
1040 * @offset: Offset from PHY port register base
1041 * @val: Value to write
1042 *
1043 * Return:
1044 * * %0 - success
1045 * * %EINVAL - invalid port number or resource type
1046 * * %other - failed to write to PHY
1047 */
ice_write_ptp_reg_eth56g(struct ice_hw * hw,u8 port,u16 offset,u32 val)1048 static int ice_write_ptp_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset,
1049 u32 val)
1050 {
1051 return ice_write_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_PTP);
1052 }
1053
1054 /**
1055 * ice_write_mac_reg_eth56g - Write a MAC PHY port register
1056 * parameter
1057 * @hw: pointer to the HW struct
1058 * @port: Port number to be written
1059 * @offset: Offset from PHY port register base
1060 * @val: Value to write
1061 *
1062 * Return:
1063 * * %0 - success
1064 * * %EINVAL - invalid port number or resource type
1065 * * %other - failed to write to PHY
1066 */
ice_write_mac_reg_eth56g(struct ice_hw * hw,u8 port,u32 offset,u32 val)1067 static int ice_write_mac_reg_eth56g(struct ice_hw *hw, u8 port, u32 offset,
1068 u32 val)
1069 {
1070 return ice_write_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_MAC);
1071 }
1072
1073 /**
1074 * ice_write_xpcs_reg_eth56g - Write a PHY port register
1075 * @hw: pointer to the HW struct
1076 * @port: Port number to be written
1077 * @offset: Offset from PHY port register base
1078 * @val: Value to write
1079 *
1080 * Return:
1081 * * %0 - success
1082 * * %EINVAL - invalid port number or resource type
1083 * * %other - failed to write to PHY
1084 */
ice_write_xpcs_reg_eth56g(struct ice_hw * hw,u8 port,u32 offset,u32 val)1085 static int ice_write_xpcs_reg_eth56g(struct ice_hw *hw, u8 port, u32 offset,
1086 u32 val)
1087 {
1088 return ice_write_port_eth56g(hw, port, offset, val,
1089 ETH56G_PHY_REG_XPCS);
1090 }
1091
1092 /**
1093 * ice_read_ptp_reg_eth56g - Read a PHY port register
1094 * @hw: pointer to the HW struct
1095 * @port: Port number to be read
1096 * @offset: Offset from PHY port register base
1097 * @val: Pointer to the value to read (out param)
1098 *
1099 * Return:
1100 * * %0 - success
1101 * * %EINVAL - invalid port number or resource type
1102 * * %other - failed to read from PHY
1103 */
ice_read_ptp_reg_eth56g(struct ice_hw * hw,u8 port,u16 offset,u32 * val)1104 static int ice_read_ptp_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset,
1105 u32 *val)
1106 {
1107 return ice_read_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_PTP);
1108 }
1109
1110 /**
1111 * ice_read_mac_reg_eth56g - Read a PHY port register
1112 * @hw: pointer to the HW struct
1113 * @port: Port number to be read
1114 * @offset: Offset from PHY port register base
1115 * @val: Pointer to the value to read (out param)
1116 *
1117 * Return:
1118 * * %0 - success
1119 * * %EINVAL - invalid port number or resource type
1120 * * %other - failed to read from PHY
1121 */
ice_read_mac_reg_eth56g(struct ice_hw * hw,u8 port,u16 offset,u32 * val)1122 static int ice_read_mac_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset,
1123 u32 *val)
1124 {
1125 return ice_read_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_MAC);
1126 }
1127
1128 /**
1129 * ice_read_gpcs_reg_eth56g - Read a PHY port register
1130 * @hw: pointer to the HW struct
1131 * @port: Port number to be read
1132 * @offset: Offset from PHY port register base
1133 * @val: Pointer to the value to read (out param)
1134 *
1135 * Return:
1136 * * %0 - success
1137 * * %EINVAL - invalid port number or resource type
1138 * * %other - failed to read from PHY
1139 */
ice_read_gpcs_reg_eth56g(struct ice_hw * hw,u8 port,u16 offset,u32 * val)1140 static int ice_read_gpcs_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset,
1141 u32 *val)
1142 {
1143 return ice_read_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_GPCS);
1144 }
1145
1146 /**
1147 * ice_read_port_mem_eth56g - Read a PHY port memory location
1148 * @hw: pointer to the HW struct
1149 * @port: Port number to be read
1150 * @offset: Offset from PHY port register base
1151 * @val: Pointer to the value to read (out param)
1152 *
1153 * Return:
1154 * * %0 - success
1155 * * %EINVAL - invalid port number or resource type
1156 * * %other - failed to read from PHY
1157 */
ice_read_port_mem_eth56g(struct ice_hw * hw,u8 port,u16 offset,u32 * val)1158 static int ice_read_port_mem_eth56g(struct ice_hw *hw, u8 port, u16 offset,
1159 u32 *val)
1160 {
1161 return ice_read_port_eth56g(hw, port, offset, val, ETH56G_PHY_MEM_PTP);
1162 }
1163
1164 /**
1165 * ice_write_port_mem_eth56g - Write a PHY port memory location
1166 * @hw: pointer to the HW struct
1167 * @port: Port number to be read
1168 * @offset: Offset from PHY port register base
1169 * @val: Pointer to the value to read (out param)
1170 *
1171 * Return:
1172 * * %0 - success
1173 * * %EINVAL - invalid port number or resource type
1174 * * %other - failed to write to PHY
1175 */
ice_write_port_mem_eth56g(struct ice_hw * hw,u8 port,u16 offset,u32 val)1176 static int ice_write_port_mem_eth56g(struct ice_hw *hw, u8 port, u16 offset,
1177 u32 val)
1178 {
1179 return ice_write_port_eth56g(hw, port, offset, val, ETH56G_PHY_MEM_PTP);
1180 }
1181
1182 /**
1183 * ice_is_64b_phy_reg_eth56g - Check if this is a 64bit PHY register
1184 * @low_addr: the low address to check
1185 * @high_addr: on return, contains the high address of the 64bit register
1186 *
1187 * Write the appropriate high register offset to use.
1188 *
1189 * Return: true if the provided low address is one of the known 64bit PHY values
1190 * represented as two 32bit registers, false otherwise.
1191 */
ice_is_64b_phy_reg_eth56g(u16 low_addr,u16 * high_addr)1192 static bool ice_is_64b_phy_reg_eth56g(u16 low_addr, u16 *high_addr)
1193 {
1194 switch (low_addr) {
1195 case PHY_REG_TX_TIMER_INC_PRE_L:
1196 *high_addr = PHY_REG_TX_TIMER_INC_PRE_U;
1197 return true;
1198 case PHY_REG_RX_TIMER_INC_PRE_L:
1199 *high_addr = PHY_REG_RX_TIMER_INC_PRE_U;
1200 return true;
1201 case PHY_REG_TX_CAPTURE_L:
1202 *high_addr = PHY_REG_TX_CAPTURE_U;
1203 return true;
1204 case PHY_REG_RX_CAPTURE_L:
1205 *high_addr = PHY_REG_RX_CAPTURE_U;
1206 return true;
1207 case PHY_REG_TOTAL_TX_OFFSET_L:
1208 *high_addr = PHY_REG_TOTAL_TX_OFFSET_U;
1209 return true;
1210 case PHY_REG_TOTAL_RX_OFFSET_L:
1211 *high_addr = PHY_REG_TOTAL_RX_OFFSET_U;
1212 return true;
1213 case PHY_REG_TX_MEMORY_STATUS_L:
1214 *high_addr = PHY_REG_TX_MEMORY_STATUS_U;
1215 return true;
1216 default:
1217 return false;
1218 }
1219 }
1220
1221 /**
1222 * ice_is_40b_phy_reg_eth56g - Check if this is a 40bit PHY register
1223 * @low_addr: the low address to check
1224 * @high_addr: on return, contains the high address of the 40bit value
1225 *
1226 * Write the appropriate high register offset to use.
1227 *
1228 * Return: true if the provided low address is one of the known 40bit PHY
1229 * values split into two registers with the lower 8 bits in the low register and
1230 * the upper 32 bits in the high register, false otherwise.
1231 */
ice_is_40b_phy_reg_eth56g(u16 low_addr,u16 * high_addr)1232 static bool ice_is_40b_phy_reg_eth56g(u16 low_addr, u16 *high_addr)
1233 {
1234 switch (low_addr) {
1235 case PHY_REG_TIMETUS_L:
1236 *high_addr = PHY_REG_TIMETUS_U;
1237 return true;
1238 case PHY_PCS_REF_TUS_L:
1239 *high_addr = PHY_PCS_REF_TUS_U;
1240 return true;
1241 case PHY_PCS_REF_INC_L:
1242 *high_addr = PHY_PCS_REF_INC_U;
1243 return true;
1244 default:
1245 return false;
1246 }
1247 }
1248
1249 /**
1250 * ice_read_64b_phy_reg_eth56g - Read a 64bit value from PHY registers
1251 * @hw: pointer to the HW struct
1252 * @port: PHY port to read from
1253 * @low_addr: offset of the lower register to read from
1254 * @val: on return, the contents of the 64bit value from the PHY registers
1255 * @res_type: resource type
1256 *
1257 * Check if the caller has specified a known 40 bit register offset and read
1258 * the two registers associated with a 40bit value and return it in the val
1259 * pointer.
1260 *
1261 * Return:
1262 * * %0 - success
1263 * * %EINVAL - not a 64 bit register
1264 * * %other - failed to read from PHY
1265 */
ice_read_64b_phy_reg_eth56g(struct ice_hw * hw,u8 port,u16 low_addr,u64 * val,enum eth56g_res_type res_type)1266 static int ice_read_64b_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr,
1267 u64 *val, enum eth56g_res_type res_type)
1268 {
1269 u16 high_addr;
1270 u32 lo, hi;
1271 int err;
1272
1273 if (!ice_is_64b_phy_reg_eth56g(low_addr, &high_addr))
1274 return -EINVAL;
1275
1276 err = ice_read_port_eth56g(hw, port, low_addr, &lo, res_type);
1277 if (err) {
1278 ice_debug(hw, ICE_DBG_PTP, "Failed to read from low register %#08x\n, err %d",
1279 low_addr, err);
1280 return err;
1281 }
1282
1283 err = ice_read_port_eth56g(hw, port, high_addr, &hi, res_type);
1284 if (err) {
1285 ice_debug(hw, ICE_DBG_PTP, "Failed to read from high register %#08x\n, err %d",
1286 high_addr, err);
1287 return err;
1288 }
1289
1290 *val = ((u64)hi << 32) | lo;
1291
1292 return 0;
1293 }
1294
1295 /**
1296 * ice_read_64b_ptp_reg_eth56g - Read a 64bit value from PHY registers
1297 * @hw: pointer to the HW struct
1298 * @port: PHY port to read from
1299 * @low_addr: offset of the lower register to read from
1300 * @val: on return, the contents of the 64bit value from the PHY registers
1301 *
1302 * Check if the caller has specified a known 40 bit register offset and read
1303 * the two registers associated with a 40bit value and return it in the val
1304 * pointer.
1305 *
1306 * Return:
1307 * * %0 - success
1308 * * %EINVAL - not a 64 bit register
1309 * * %other - failed to read from PHY
1310 */
ice_read_64b_ptp_reg_eth56g(struct ice_hw * hw,u8 port,u16 low_addr,u64 * val)1311 static int ice_read_64b_ptp_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr,
1312 u64 *val)
1313 {
1314 return ice_read_64b_phy_reg_eth56g(hw, port, low_addr, val,
1315 ETH56G_PHY_REG_PTP);
1316 }
1317
1318 /**
1319 * ice_write_40b_phy_reg_eth56g - Write a 40b value to the PHY
1320 * @hw: pointer to the HW struct
1321 * @port: port to write to
1322 * @low_addr: offset of the low register
1323 * @val: 40b value to write
1324 * @res_type: resource type
1325 *
1326 * Check if the caller has specified a known 40 bit register offset and write
1327 * provided 40b value to the two associated registers by splitting it up into
1328 * two chunks, the lower 8 bits and the upper 32 bits.
1329 *
1330 * Return:
1331 * * %0 - success
1332 * * %EINVAL - not a 40 bit register
1333 * * %other - failed to write to PHY
1334 */
ice_write_40b_phy_reg_eth56g(struct ice_hw * hw,u8 port,u16 low_addr,u64 val,enum eth56g_res_type res_type)1335 static int ice_write_40b_phy_reg_eth56g(struct ice_hw *hw, u8 port,
1336 u16 low_addr, u64 val,
1337 enum eth56g_res_type res_type)
1338 {
1339 u16 high_addr;
1340 u32 lo, hi;
1341 int err;
1342
1343 if (!ice_is_40b_phy_reg_eth56g(low_addr, &high_addr))
1344 return -EINVAL;
1345
1346 lo = FIELD_GET(P_REG_40B_LOW_M, val);
1347 hi = (u32)(val >> P_REG_40B_HIGH_S);
1348
1349 err = ice_write_port_eth56g(hw, port, low_addr, lo, res_type);
1350 if (err) {
1351 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d",
1352 low_addr, err);
1353 return err;
1354 }
1355
1356 err = ice_write_port_eth56g(hw, port, high_addr, hi, res_type);
1357 if (err) {
1358 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d",
1359 high_addr, err);
1360 return err;
1361 }
1362
1363 return 0;
1364 }
1365
1366 /**
1367 * ice_write_40b_ptp_reg_eth56g - Write a 40b value to the PHY
1368 * @hw: pointer to the HW struct
1369 * @port: port to write to
1370 * @low_addr: offset of the low register
1371 * @val: 40b value to write
1372 *
1373 * Check if the caller has specified a known 40 bit register offset and write
1374 * provided 40b value to the two associated registers by splitting it up into
1375 * two chunks, the lower 8 bits and the upper 32 bits.
1376 *
1377 * Return:
1378 * * %0 - success
1379 * * %EINVAL - not a 40 bit register
1380 * * %other - failed to write to PHY
1381 */
ice_write_40b_ptp_reg_eth56g(struct ice_hw * hw,u8 port,u16 low_addr,u64 val)1382 static int ice_write_40b_ptp_reg_eth56g(struct ice_hw *hw, u8 port,
1383 u16 low_addr, u64 val)
1384 {
1385 return ice_write_40b_phy_reg_eth56g(hw, port, low_addr, val,
1386 ETH56G_PHY_REG_PTP);
1387 }
1388
1389 /**
1390 * ice_write_64b_phy_reg_eth56g - Write a 64bit value to PHY registers
1391 * @hw: pointer to the HW struct
1392 * @port: PHY port to read from
1393 * @low_addr: offset of the lower register to read from
1394 * @val: the contents of the 64bit value to write to PHY
1395 * @res_type: resource type
1396 *
1397 * Check if the caller has specified a known 64 bit register offset and write
1398 * the 64bit value to the two associated 32bit PHY registers.
1399 *
1400 * Return:
1401 * * %0 - success
1402 * * %EINVAL - not a 64 bit register
1403 * * %other - failed to write to PHY
1404 */
ice_write_64b_phy_reg_eth56g(struct ice_hw * hw,u8 port,u16 low_addr,u64 val,enum eth56g_res_type res_type)1405 static int ice_write_64b_phy_reg_eth56g(struct ice_hw *hw, u8 port,
1406 u16 low_addr, u64 val,
1407 enum eth56g_res_type res_type)
1408 {
1409 u16 high_addr;
1410 u32 lo, hi;
1411 int err;
1412
1413 if (!ice_is_64b_phy_reg_eth56g(low_addr, &high_addr))
1414 return -EINVAL;
1415
1416 lo = lower_32_bits(val);
1417 hi = upper_32_bits(val);
1418
1419 err = ice_write_port_eth56g(hw, port, low_addr, lo, res_type);
1420 if (err) {
1421 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d",
1422 low_addr, err);
1423 return err;
1424 }
1425
1426 err = ice_write_port_eth56g(hw, port, high_addr, hi, res_type);
1427 if (err) {
1428 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d",
1429 high_addr, err);
1430 return err;
1431 }
1432
1433 return 0;
1434 }
1435
1436 /**
1437 * ice_write_64b_ptp_reg_eth56g - Write a 64bit value to PHY registers
1438 * @hw: pointer to the HW struct
1439 * @port: PHY port to read from
1440 * @low_addr: offset of the lower register to read from
1441 * @val: the contents of the 64bit value to write to PHY
1442 *
1443 * Check if the caller has specified a known 64 bit register offset and write
1444 * the 64bit value to the two associated 32bit PHY registers.
1445 *
1446 * Return:
1447 * * %0 - success
1448 * * %EINVAL - not a 64 bit register
1449 * * %other - failed to write to PHY
1450 */
ice_write_64b_ptp_reg_eth56g(struct ice_hw * hw,u8 port,u16 low_addr,u64 val)1451 static int ice_write_64b_ptp_reg_eth56g(struct ice_hw *hw, u8 port,
1452 u16 low_addr, u64 val)
1453 {
1454 return ice_write_64b_phy_reg_eth56g(hw, port, low_addr, val,
1455 ETH56G_PHY_REG_PTP);
1456 }
1457
1458 /**
1459 * ice_read_ptp_tstamp_eth56g - Read a PHY timestamp out of the port memory
1460 * @hw: pointer to the HW struct
1461 * @port: the port to read from
1462 * @idx: the timestamp index to read
1463 * @tstamp: on return, the 40bit timestamp value
1464 *
1465 * Read a 40bit timestamp value out of the two associated entries in the
1466 * port memory block of the internal PHYs of the 56G devices.
1467 *
1468 * Return:
1469 * * %0 - success
1470 * * %other - failed to read from PHY
1471 */
ice_read_ptp_tstamp_eth56g(struct ice_hw * hw,u8 port,u8 idx,u64 * tstamp)1472 static int ice_read_ptp_tstamp_eth56g(struct ice_hw *hw, u8 port, u8 idx,
1473 u64 *tstamp)
1474 {
1475 u16 lo_addr, hi_addr;
1476 u32 lo, hi;
1477 int err;
1478
1479 lo_addr = (u16)PHY_TSTAMP_L(idx);
1480 hi_addr = (u16)PHY_TSTAMP_U(idx);
1481
1482 err = ice_read_port_mem_eth56g(hw, port, lo_addr, &lo);
1483 if (err) {
1484 ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n",
1485 err);
1486 return err;
1487 }
1488
1489 err = ice_read_port_mem_eth56g(hw, port, hi_addr, &hi);
1490 if (err) {
1491 ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n",
1492 err);
1493 return err;
1494 }
1495
1496 /* For 56G based internal PHYs, the timestamp is reported with the
1497 * lower 8 bits in the low register, and the upper 32 bits in the high
1498 * register.
1499 */
1500 *tstamp = ((u64)hi) << TS_PHY_HIGH_S | ((u64)lo & TS_PHY_LOW_M);
1501
1502 return 0;
1503 }
1504
1505 /**
1506 * ice_clear_ptp_tstamp_eth56g - Clear a timestamp from the quad block
1507 * @hw: pointer to the HW struct
1508 * @port: the quad to read from
1509 * @idx: the timestamp index to reset
1510 *
1511 * Read and then forcibly clear the timestamp index to ensure the valid bit is
1512 * cleared and the timestamp status bit is reset in the PHY port memory of
1513 * internal PHYs of the 56G devices.
1514 *
1515 * To directly clear the contents of the timestamp block entirely, discarding
1516 * all timestamp data at once, software should instead use
1517 * ice_ptp_reset_ts_memory_quad_eth56g().
1518 *
1519 * This function should only be called on an idx whose bit is set according to
1520 * ice_get_phy_tx_tstamp_ready().
1521 *
1522 * Return:
1523 * * %0 - success
1524 * * %other - failed to write to PHY
1525 */
ice_clear_ptp_tstamp_eth56g(struct ice_hw * hw,u8 port,u8 idx)1526 static int ice_clear_ptp_tstamp_eth56g(struct ice_hw *hw, u8 port, u8 idx)
1527 {
1528 u64 unused_tstamp;
1529 u16 lo_addr;
1530 int err;
1531
1532 /* Read the timestamp register to ensure the timestamp status bit is
1533 * cleared.
1534 */
1535 err = ice_read_ptp_tstamp_eth56g(hw, port, idx, &unused_tstamp);
1536 if (err) {
1537 ice_debug(hw, ICE_DBG_PTP, "Failed to read the PHY timestamp register for port %u, idx %u, err %d\n",
1538 port, idx, err);
1539 }
1540
1541 lo_addr = (u16)PHY_TSTAMP_L(idx);
1542
1543 err = ice_write_port_mem_eth56g(hw, port, lo_addr, 0);
1544 if (err) {
1545 ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register for port %u, idx %u, err %d\n",
1546 port, idx, err);
1547 return err;
1548 }
1549
1550 return 0;
1551 }
1552
1553 /**
1554 * ice_ptp_reset_ts_memory_eth56g - Clear all timestamps from the port block
1555 * @hw: pointer to the HW struct
1556 */
ice_ptp_reset_ts_memory_eth56g(struct ice_hw * hw)1557 static void ice_ptp_reset_ts_memory_eth56g(struct ice_hw *hw)
1558 {
1559 unsigned int port;
1560
1561 for (port = 0; port < hw->ptp.num_lports; port++) {
1562 ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_MEMORY_STATUS_L,
1563 0);
1564 ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_MEMORY_STATUS_U,
1565 0);
1566 }
1567 }
1568
1569 /**
1570 * ice_ptp_prep_port_time_eth56g - Prepare one PHY port with initial time
1571 * @hw: pointer to the HW struct
1572 * @port: port number
1573 * @time: time to initialize the PHY port clocks to
1574 *
1575 * Write a new initial time value into registers of a specific PHY port.
1576 *
1577 * Return:
1578 * * %0 - success
1579 * * %other - failed to write to PHY
1580 */
ice_ptp_prep_port_time_eth56g(struct ice_hw * hw,u8 port,u64 time)1581 static int ice_ptp_prep_port_time_eth56g(struct ice_hw *hw, u8 port,
1582 u64 time)
1583 {
1584 int err;
1585
1586 /* Tx case */
1587 err = ice_write_64b_ptp_reg_eth56g(hw, port, PHY_REG_TX_TIMER_INC_PRE_L,
1588 time);
1589 if (err)
1590 return err;
1591
1592 /* Rx case */
1593 return ice_write_64b_ptp_reg_eth56g(hw, port,
1594 PHY_REG_RX_TIMER_INC_PRE_L, time);
1595 }
1596
1597 /**
1598 * ice_ptp_prep_phy_time_eth56g - Prepare PHY port with initial time
1599 * @hw: pointer to the HW struct
1600 * @time: Time to initialize the PHY port clocks to
1601 *
1602 * Program the PHY port registers with a new initial time value. The port
1603 * clock will be initialized once the driver issues an ICE_PTP_INIT_TIME sync
1604 * command. The time value is the upper 32 bits of the PHY timer, usually in
1605 * units of nominal nanoseconds.
1606 *
1607 * Return:
1608 * * %0 - success
1609 * * %other - failed to write to PHY
1610 */
ice_ptp_prep_phy_time_eth56g(struct ice_hw * hw,u32 time)1611 static int ice_ptp_prep_phy_time_eth56g(struct ice_hw *hw, u32 time)
1612 {
1613 u64 phy_time;
1614 u8 port;
1615
1616 /* The time represents the upper 32 bits of the PHY timer, so we need
1617 * to shift to account for this when programming.
1618 */
1619 phy_time = (u64)time << 32;
1620
1621 for (port = 0; port < hw->ptp.num_lports; port++) {
1622 int err;
1623
1624 err = ice_ptp_prep_port_time_eth56g(hw, port, phy_time);
1625 if (err) {
1626 ice_debug(hw, ICE_DBG_PTP, "Failed to write init time for port %u, err %d\n",
1627 port, err);
1628 return err;
1629 }
1630 }
1631
1632 return 0;
1633 }
1634
1635 /**
1636 * ice_ptp_prep_port_adj_eth56g - Prepare a single port for time adjust
1637 * @hw: pointer to HW struct
1638 * @port: Port number to be programmed
1639 * @time: time in cycles to adjust the port clocks
1640 *
1641 * Program the port for an atomic adjustment by writing the Tx and Rx timer
1642 * registers. The atomic adjustment won't be completed until the driver issues
1643 * an ICE_PTP_ADJ_TIME command.
1644 *
1645 * Note that time is not in units of nanoseconds. It is in clock time
1646 * including the lower sub-nanosecond portion of the port timer.
1647 *
1648 * Negative adjustments are supported using 2s complement arithmetic.
1649 *
1650 * Return:
1651 * * %0 - success
1652 * * %other - failed to write to PHY
1653 */
ice_ptp_prep_port_adj_eth56g(struct ice_hw * hw,u8 port,s64 time)1654 static int ice_ptp_prep_port_adj_eth56g(struct ice_hw *hw, u8 port, s64 time)
1655 {
1656 u32 l_time, u_time;
1657 int err;
1658
1659 l_time = lower_32_bits(time);
1660 u_time = upper_32_bits(time);
1661
1662 /* Tx case */
1663 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_TIMER_INC_PRE_L,
1664 l_time);
1665 if (err)
1666 goto exit_err;
1667
1668 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_TIMER_INC_PRE_U,
1669 u_time);
1670 if (err)
1671 goto exit_err;
1672
1673 /* Rx case */
1674 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_TIMER_INC_PRE_L,
1675 l_time);
1676 if (err)
1677 goto exit_err;
1678
1679 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_TIMER_INC_PRE_U,
1680 u_time);
1681 if (err)
1682 goto exit_err;
1683
1684 return 0;
1685
1686 exit_err:
1687 ice_debug(hw, ICE_DBG_PTP, "Failed to write time adjust for port %u, err %d\n",
1688 port, err);
1689 return err;
1690 }
1691
1692 /**
1693 * ice_ptp_prep_phy_adj_eth56g - Prep PHY ports for a time adjustment
1694 * @hw: pointer to HW struct
1695 * @adj: adjustment in nanoseconds
1696 *
1697 * Prepare the PHY ports for an atomic time adjustment by programming the PHY
1698 * Tx and Rx port registers. The actual adjustment is completed by issuing an
1699 * ICE_PTP_ADJ_TIME or ICE_PTP_ADJ_TIME_AT_TIME sync command.
1700 *
1701 * Return:
1702 * * %0 - success
1703 * * %other - failed to write to PHY
1704 */
ice_ptp_prep_phy_adj_eth56g(struct ice_hw * hw,s32 adj)1705 static int ice_ptp_prep_phy_adj_eth56g(struct ice_hw *hw, s32 adj)
1706 {
1707 s64 cycles;
1708 u8 port;
1709
1710 /* The port clock supports adjustment of the sub-nanosecond portion of
1711 * the clock (lowest 32 bits). We shift the provided adjustment in
1712 * nanoseconds by 32 to calculate the appropriate adjustment to program
1713 * into the PHY ports.
1714 */
1715 cycles = (s64)adj << 32;
1716
1717 for (port = 0; port < hw->ptp.num_lports; port++) {
1718 int err;
1719
1720 err = ice_ptp_prep_port_adj_eth56g(hw, port, cycles);
1721 if (err)
1722 return err;
1723 }
1724
1725 return 0;
1726 }
1727
1728 /**
1729 * ice_ptp_prep_phy_incval_eth56g - Prepare PHY ports for time adjustment
1730 * @hw: pointer to HW struct
1731 * @incval: new increment value to prepare
1732 *
1733 * Prepare each of the PHY ports for a new increment value by programming the
1734 * port's TIMETUS registers. The new increment value will be updated after
1735 * issuing an ICE_PTP_INIT_INCVAL command.
1736 *
1737 * Return:
1738 * * %0 - success
1739 * * %other - failed to write to PHY
1740 */
ice_ptp_prep_phy_incval_eth56g(struct ice_hw * hw,u64 incval)1741 static int ice_ptp_prep_phy_incval_eth56g(struct ice_hw *hw, u64 incval)
1742 {
1743 u8 port;
1744
1745 for (port = 0; port < hw->ptp.num_lports; port++) {
1746 int err;
1747
1748 err = ice_write_40b_ptp_reg_eth56g(hw, port, PHY_REG_TIMETUS_L,
1749 incval);
1750 if (err) {
1751 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval for port %u, err %d\n",
1752 port, err);
1753 return err;
1754 }
1755 }
1756
1757 return 0;
1758 }
1759
1760 /**
1761 * ice_ptp_read_port_capture_eth56g - Read a port's local time capture
1762 * @hw: pointer to HW struct
1763 * @port: Port number to read
1764 * @tx_ts: on return, the Tx port time capture
1765 * @rx_ts: on return, the Rx port time capture
1766 *
1767 * Read the port's Tx and Rx local time capture values.
1768 *
1769 * Return:
1770 * * %0 - success
1771 * * %other - failed to read from PHY
1772 */
ice_ptp_read_port_capture_eth56g(struct ice_hw * hw,u8 port,u64 * tx_ts,u64 * rx_ts)1773 static int ice_ptp_read_port_capture_eth56g(struct ice_hw *hw, u8 port,
1774 u64 *tx_ts, u64 *rx_ts)
1775 {
1776 int err;
1777
1778 /* Tx case */
1779 err = ice_read_64b_ptp_reg_eth56g(hw, port, PHY_REG_TX_CAPTURE_L,
1780 tx_ts);
1781 if (err) {
1782 ice_debug(hw, ICE_DBG_PTP, "Failed to read REG_TX_CAPTURE, err %d\n",
1783 err);
1784 return err;
1785 }
1786
1787 ice_debug(hw, ICE_DBG_PTP, "tx_init = %#016llx\n", *tx_ts);
1788
1789 /* Rx case */
1790 err = ice_read_64b_ptp_reg_eth56g(hw, port, PHY_REG_RX_CAPTURE_L,
1791 rx_ts);
1792 if (err) {
1793 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_CAPTURE, err %d\n",
1794 err);
1795 return err;
1796 }
1797
1798 ice_debug(hw, ICE_DBG_PTP, "rx_init = %#016llx\n", *rx_ts);
1799
1800 return 0;
1801 }
1802
1803 /**
1804 * ice_ptp_write_port_cmd_eth56g - Prepare a single PHY port for a timer command
1805 * @hw: pointer to HW struct
1806 * @port: Port to which cmd has to be sent
1807 * @cmd: Command to be sent to the port
1808 *
1809 * Prepare the requested port for an upcoming timer sync command.
1810 *
1811 * Return:
1812 * * %0 - success
1813 * * %other - failed to write to PHY
1814 */
ice_ptp_write_port_cmd_eth56g(struct ice_hw * hw,u8 port,enum ice_ptp_tmr_cmd cmd)1815 static int ice_ptp_write_port_cmd_eth56g(struct ice_hw *hw, u8 port,
1816 enum ice_ptp_tmr_cmd cmd)
1817 {
1818 u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd);
1819 int err;
1820
1821 /* Tx case */
1822 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_TMR_CMD, val);
1823 if (err) {
1824 ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_TMR_CMD, err %d\n",
1825 err);
1826 return err;
1827 }
1828
1829 /* Rx case */
1830 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_TMR_CMD, val);
1831 if (err) {
1832 ice_debug(hw, ICE_DBG_PTP, "Failed to write back RX_TMR_CMD, err %d\n",
1833 err);
1834 return err;
1835 }
1836
1837 return 0;
1838 }
1839
1840 /**
1841 * ice_phy_get_speed_eth56g - Get link speed based on PHY link type
1842 * @li: pointer to link information struct
1843 *
1844 * Return: simplified ETH56G PHY speed
1845 */
1846 static enum ice_eth56g_link_spd
ice_phy_get_speed_eth56g(struct ice_link_status * li)1847 ice_phy_get_speed_eth56g(struct ice_link_status *li)
1848 {
1849 u16 speed = ice_get_link_speed_based_on_phy_type(li->phy_type_low,
1850 li->phy_type_high);
1851
1852 switch (speed) {
1853 case ICE_AQ_LINK_SPEED_1000MB:
1854 return ICE_ETH56G_LNK_SPD_1G;
1855 case ICE_AQ_LINK_SPEED_2500MB:
1856 return ICE_ETH56G_LNK_SPD_2_5G;
1857 case ICE_AQ_LINK_SPEED_10GB:
1858 return ICE_ETH56G_LNK_SPD_10G;
1859 case ICE_AQ_LINK_SPEED_25GB:
1860 return ICE_ETH56G_LNK_SPD_25G;
1861 case ICE_AQ_LINK_SPEED_40GB:
1862 return ICE_ETH56G_LNK_SPD_40G;
1863 case ICE_AQ_LINK_SPEED_50GB:
1864 switch (li->phy_type_low) {
1865 case ICE_PHY_TYPE_LOW_50GBASE_SR:
1866 case ICE_PHY_TYPE_LOW_50GBASE_FR:
1867 case ICE_PHY_TYPE_LOW_50GBASE_LR:
1868 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
1869 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
1870 case ICE_PHY_TYPE_LOW_50G_AUI1:
1871 return ICE_ETH56G_LNK_SPD_50G;
1872 default:
1873 return ICE_ETH56G_LNK_SPD_50G2;
1874 }
1875 case ICE_AQ_LINK_SPEED_100GB:
1876 if (li->phy_type_high ||
1877 li->phy_type_low == ICE_PHY_TYPE_LOW_100GBASE_SR2)
1878 return ICE_ETH56G_LNK_SPD_100G2;
1879 else
1880 return ICE_ETH56G_LNK_SPD_100G;
1881 default:
1882 return ICE_ETH56G_LNK_SPD_1G;
1883 }
1884 }
1885
1886 /**
1887 * ice_phy_cfg_parpcs_eth56g - Configure TUs per PAR/PCS clock cycle
1888 * @hw: pointer to the HW struct
1889 * @port: port to configure
1890 *
1891 * Configure the number of TUs for the PAR and PCS clocks used as part of the
1892 * timestamp calibration process.
1893 *
1894 * Return:
1895 * * %0 - success
1896 * * %other - PHY read/write failed
1897 */
ice_phy_cfg_parpcs_eth56g(struct ice_hw * hw,u8 port)1898 static int ice_phy_cfg_parpcs_eth56g(struct ice_hw *hw, u8 port)
1899 {
1900 u8 port_blk = port & ~(ICE_PORTS_PER_QUAD - 1);
1901 u32 val;
1902 int err;
1903
1904 err = ice_write_xpcs_reg_eth56g(hw, port, PHY_VENDOR_TXLANE_THRESH,
1905 ICE_ETH56G_NOMINAL_THRESH4);
1906 if (err) {
1907 ice_debug(hw, ICE_DBG_PTP, "Failed to read VENDOR_TXLANE_THRESH, status: %d",
1908 err);
1909 return err;
1910 }
1911
1912 switch (ice_phy_get_speed_eth56g(&hw->port_info->phy.link_info)) {
1913 case ICE_ETH56G_LNK_SPD_1G:
1914 case ICE_ETH56G_LNK_SPD_2_5G:
1915 err = ice_read_ptp_reg_eth56g(hw, port_blk,
1916 PHY_GPCS_CONFIG_REG0, &val);
1917 if (err) {
1918 ice_debug(hw, ICE_DBG_PTP, "Failed to read PHY_GPCS_CONFIG_REG0, status: %d",
1919 err);
1920 return err;
1921 }
1922
1923 val &= ~PHY_GPCS_CONFIG_REG0_TX_THR_M;
1924 val |= FIELD_PREP(PHY_GPCS_CONFIG_REG0_TX_THR_M,
1925 ICE_ETH56G_NOMINAL_TX_THRESH);
1926
1927 err = ice_write_ptp_reg_eth56g(hw, port_blk,
1928 PHY_GPCS_CONFIG_REG0, val);
1929 if (err) {
1930 ice_debug(hw, ICE_DBG_PTP, "Failed to write PHY_GPCS_CONFIG_REG0, status: %d",
1931 err);
1932 return err;
1933 }
1934 break;
1935 default:
1936 break;
1937 }
1938
1939 err = ice_write_40b_ptp_reg_eth56g(hw, port, PHY_PCS_REF_TUS_L,
1940 ICE_ETH56G_NOMINAL_PCS_REF_TUS);
1941 if (err) {
1942 ice_debug(hw, ICE_DBG_PTP, "Failed to write PHY_PCS_REF_TUS, status: %d",
1943 err);
1944 return err;
1945 }
1946
1947 err = ice_write_40b_ptp_reg_eth56g(hw, port, PHY_PCS_REF_INC_L,
1948 ICE_ETH56G_NOMINAL_PCS_REF_INC);
1949 if (err) {
1950 ice_debug(hw, ICE_DBG_PTP, "Failed to write PHY_PCS_REF_INC, status: %d",
1951 err);
1952 return err;
1953 }
1954
1955 return 0;
1956 }
1957
1958 /**
1959 * ice_phy_cfg_ptp_1step_eth56g - Configure 1-step PTP settings
1960 * @hw: Pointer to the HW struct
1961 * @port: Port to configure
1962 *
1963 * Return:
1964 * * %0 - success
1965 * * %other - PHY read/write failed
1966 */
ice_phy_cfg_ptp_1step_eth56g(struct ice_hw * hw,u8 port)1967 int ice_phy_cfg_ptp_1step_eth56g(struct ice_hw *hw, u8 port)
1968 {
1969 u8 port_blk = port & ~(ICE_PORTS_PER_QUAD - 1);
1970 u8 blk_port = port & (ICE_PORTS_PER_QUAD - 1);
1971 bool enable, sfd_ena;
1972 u32 val, peer_delay;
1973 int err;
1974
1975 enable = hw->ptp.phy.eth56g.onestep_ena;
1976 peer_delay = hw->ptp.phy.eth56g.peer_delay;
1977 sfd_ena = hw->ptp.phy.eth56g.sfd_ena;
1978
1979 /* PHY_PTP_1STEP_CONFIG */
1980 err = ice_read_ptp_reg_eth56g(hw, port_blk, PHY_PTP_1STEP_CONFIG, &val);
1981 if (err)
1982 return err;
1983
1984 if (enable)
1985 val |= blk_port;
1986 else
1987 val &= ~blk_port;
1988
1989 val &= ~(PHY_PTP_1STEP_T1S_UP64_M | PHY_PTP_1STEP_T1S_DELTA_M);
1990
1991 err = ice_write_ptp_reg_eth56g(hw, port_blk, PHY_PTP_1STEP_CONFIG, val);
1992 if (err)
1993 return err;
1994
1995 /* PHY_PTP_1STEP_PEER_DELAY */
1996 val = FIELD_PREP(PHY_PTP_1STEP_PD_DELAY_M, peer_delay);
1997 if (peer_delay)
1998 val |= PHY_PTP_1STEP_PD_ADD_PD_M;
1999 val |= PHY_PTP_1STEP_PD_DLY_V_M;
2000 err = ice_write_ptp_reg_eth56g(hw, port_blk,
2001 PHY_PTP_1STEP_PEER_DELAY(blk_port), val);
2002 if (err)
2003 return err;
2004
2005 val &= ~PHY_PTP_1STEP_PD_DLY_V_M;
2006 err = ice_write_ptp_reg_eth56g(hw, port_blk,
2007 PHY_PTP_1STEP_PEER_DELAY(blk_port), val);
2008 if (err)
2009 return err;
2010
2011 /* PHY_MAC_XIF_MODE */
2012 err = ice_read_mac_reg_eth56g(hw, port, PHY_MAC_XIF_MODE, &val);
2013 if (err)
2014 return err;
2015
2016 val &= ~(PHY_MAC_XIF_1STEP_ENA_M | PHY_MAC_XIF_TS_BIN_MODE_M |
2017 PHY_MAC_XIF_TS_SFD_ENA_M | PHY_MAC_XIF_GMII_TS_SEL_M);
2018
2019 switch (ice_phy_get_speed_eth56g(&hw->port_info->phy.link_info)) {
2020 case ICE_ETH56G_LNK_SPD_1G:
2021 case ICE_ETH56G_LNK_SPD_2_5G:
2022 val |= PHY_MAC_XIF_GMII_TS_SEL_M;
2023 break;
2024 default:
2025 break;
2026 }
2027
2028 val |= FIELD_PREP(PHY_MAC_XIF_1STEP_ENA_M, enable) |
2029 FIELD_PREP(PHY_MAC_XIF_TS_BIN_MODE_M, enable) |
2030 FIELD_PREP(PHY_MAC_XIF_TS_SFD_ENA_M, sfd_ena);
2031
2032 return ice_write_mac_reg_eth56g(hw, port, PHY_MAC_XIF_MODE, val);
2033 }
2034
2035 /**
2036 * mul_u32_u32_fx_q9 - Multiply two u32 fixed point Q9 values
2037 * @a: multiplier value
2038 * @b: multiplicand value
2039 *
2040 * Return: result of multiplication
2041 */
mul_u32_u32_fx_q9(u32 a,u32 b)2042 static u32 mul_u32_u32_fx_q9(u32 a, u32 b)
2043 {
2044 return (u32)(((u64)a * b) >> ICE_ETH56G_MAC_CFG_FRAC_W);
2045 }
2046
2047 /**
2048 * add_u32_u32_fx - Add two u32 fixed point values and discard overflow
2049 * @a: first value
2050 * @b: second value
2051 *
2052 * Return: result of addition
2053 */
add_u32_u32_fx(u32 a,u32 b)2054 static u32 add_u32_u32_fx(u32 a, u32 b)
2055 {
2056 return lower_32_bits(((u64)a + b));
2057 }
2058
2059 /**
2060 * ice_ptp_calc_bitslip_eth56g - Calculate bitslip value
2061 * @hw: pointer to the HW struct
2062 * @port: port to configure
2063 * @bs: bitslip multiplier
2064 * @fc: FC-FEC enabled
2065 * @rs: RS-FEC enabled
2066 * @spd: link speed
2067 *
2068 * Return: calculated bitslip value
2069 */
ice_ptp_calc_bitslip_eth56g(struct ice_hw * hw,u8 port,u32 bs,bool fc,bool rs,enum ice_eth56g_link_spd spd)2070 static u32 ice_ptp_calc_bitslip_eth56g(struct ice_hw *hw, u8 port, u32 bs,
2071 bool fc, bool rs,
2072 enum ice_eth56g_link_spd spd)
2073 {
2074 u8 port_offset = port & (ICE_PORTS_PER_QUAD - 1);
2075 u8 port_blk = port & ~(ICE_PORTS_PER_QUAD - 1);
2076 u32 bitslip;
2077 int err;
2078
2079 if (!bs || rs)
2080 return 0;
2081
2082 if (spd == ICE_ETH56G_LNK_SPD_1G || spd == ICE_ETH56G_LNK_SPD_2_5G)
2083 err = ice_read_gpcs_reg_eth56g(hw, port, PHY_GPCS_BITSLIP,
2084 &bitslip);
2085 else
2086 err = ice_read_ptp_reg_eth56g(hw, port_blk,
2087 PHY_REG_SD_BIT_SLIP(port_offset),
2088 &bitslip);
2089 if (err)
2090 return 0;
2091
2092 if (spd == ICE_ETH56G_LNK_SPD_1G && !bitslip) {
2093 /* Bitslip register value of 0 corresponds to 10 so substitute
2094 * it for calculations
2095 */
2096 bitslip = 10;
2097 } else if (spd == ICE_ETH56G_LNK_SPD_10G ||
2098 spd == ICE_ETH56G_LNK_SPD_25G) {
2099 if (fc)
2100 bitslip = bitslip * 2 + 32;
2101 else
2102 bitslip = (u32)((s32)bitslip * -1 + 20);
2103 }
2104
2105 bitslip <<= ICE_ETH56G_MAC_CFG_FRAC_W;
2106 return mul_u32_u32_fx_q9(bitslip, bs);
2107 }
2108
2109 /**
2110 * ice_ptp_calc_deskew_eth56g - Calculate deskew value
2111 * @hw: pointer to the HW struct
2112 * @port: port to configure
2113 * @ds: deskew multiplier
2114 * @rs: RS-FEC enabled
2115 * @spd: link speed
2116 *
2117 * Return: calculated deskew value
2118 */
ice_ptp_calc_deskew_eth56g(struct ice_hw * hw,u8 port,u32 ds,bool rs,enum ice_eth56g_link_spd spd)2119 static u32 ice_ptp_calc_deskew_eth56g(struct ice_hw *hw, u8 port, u32 ds,
2120 bool rs, enum ice_eth56g_link_spd spd)
2121 {
2122 u32 deskew_i, deskew_f;
2123 int err;
2124
2125 if (!ds)
2126 return 0;
2127
2128 read_poll_timeout(ice_read_ptp_reg_eth56g, err,
2129 FIELD_GET(PHY_REG_DESKEW_0_VALID, deskew_i), 500,
2130 50 * USEC_PER_MSEC, false, hw, port, PHY_REG_DESKEW_0,
2131 &deskew_i);
2132 if (err)
2133 return err;
2134
2135 deskew_f = FIELD_GET(PHY_REG_DESKEW_0_RLEVEL_FRAC, deskew_i);
2136 deskew_i = FIELD_GET(PHY_REG_DESKEW_0_RLEVEL, deskew_i);
2137
2138 if (rs && spd == ICE_ETH56G_LNK_SPD_50G2)
2139 ds = 0x633; /* 3.1 */
2140 else if (rs && spd == ICE_ETH56G_LNK_SPD_100G)
2141 ds = 0x31b; /* 1.552 */
2142
2143 deskew_i = FIELD_PREP(ICE_ETH56G_MAC_CFG_RX_OFFSET_INT, deskew_i);
2144 /* Shift 3 fractional bits to the end of the integer part */
2145 deskew_f <<= ICE_ETH56G_MAC_CFG_FRAC_W - PHY_REG_DESKEW_0_RLEVEL_FRAC_W;
2146 return mul_u32_u32_fx_q9(deskew_i | deskew_f, ds);
2147 }
2148
2149 /**
2150 * ice_phy_set_offsets_eth56g - Set Tx/Rx offset values
2151 * @hw: pointer to the HW struct
2152 * @port: port to configure
2153 * @spd: link speed
2154 * @cfg: structure to store output values
2155 * @fc: FC-FEC enabled
2156 * @rs: RS-FEC enabled
2157 *
2158 * Return:
2159 * * %0 - success
2160 * * %other - failed to write to PHY
2161 */
ice_phy_set_offsets_eth56g(struct ice_hw * hw,u8 port,enum ice_eth56g_link_spd spd,const struct ice_eth56g_mac_reg_cfg * cfg,bool fc,bool rs)2162 static int ice_phy_set_offsets_eth56g(struct ice_hw *hw, u8 port,
2163 enum ice_eth56g_link_spd spd,
2164 const struct ice_eth56g_mac_reg_cfg *cfg,
2165 bool fc, bool rs)
2166 {
2167 u32 rx_offset, tx_offset, bs_ds;
2168 bool onestep, sfd;
2169
2170 onestep = hw->ptp.phy.eth56g.onestep_ena;
2171 sfd = hw->ptp.phy.eth56g.sfd_ena;
2172 bs_ds = cfg->rx_offset.bs_ds;
2173
2174 if (fc)
2175 rx_offset = cfg->rx_offset.fc;
2176 else if (rs)
2177 rx_offset = cfg->rx_offset.rs;
2178 else
2179 rx_offset = cfg->rx_offset.no_fec;
2180
2181 rx_offset = add_u32_u32_fx(rx_offset, cfg->rx_offset.serdes);
2182 if (sfd)
2183 rx_offset = add_u32_u32_fx(rx_offset, cfg->rx_offset.sfd);
2184
2185 if (spd < ICE_ETH56G_LNK_SPD_40G)
2186 bs_ds = ice_ptp_calc_bitslip_eth56g(hw, port, bs_ds, fc, rs,
2187 spd);
2188 else
2189 bs_ds = ice_ptp_calc_deskew_eth56g(hw, port, bs_ds, rs, spd);
2190 rx_offset = add_u32_u32_fx(rx_offset, bs_ds);
2191 rx_offset &= ICE_ETH56G_MAC_CFG_RX_OFFSET_INT |
2192 ICE_ETH56G_MAC_CFG_RX_OFFSET_FRAC;
2193
2194 if (fc)
2195 tx_offset = cfg->tx_offset.fc;
2196 else if (rs)
2197 tx_offset = cfg->tx_offset.rs;
2198 else
2199 tx_offset = cfg->tx_offset.no_fec;
2200 tx_offset += cfg->tx_offset.serdes + cfg->tx_offset.sfd * sfd +
2201 cfg->tx_offset.onestep * onestep;
2202
2203 ice_write_mac_reg_eth56g(hw, port, PHY_MAC_RX_OFFSET, rx_offset);
2204 return ice_write_mac_reg_eth56g(hw, port, PHY_MAC_TX_OFFSET, tx_offset);
2205 }
2206
2207 /**
2208 * ice_phy_cfg_mac_eth56g - Configure MAC for PTP
2209 * @hw: Pointer to the HW struct
2210 * @port: Port to configure
2211 *
2212 * Return:
2213 * * %0 - success
2214 * * %other - failed to write to PHY
2215 */
ice_phy_cfg_mac_eth56g(struct ice_hw * hw,u8 port)2216 static int ice_phy_cfg_mac_eth56g(struct ice_hw *hw, u8 port)
2217 {
2218 const struct ice_eth56g_mac_reg_cfg *cfg;
2219 enum ice_eth56g_link_spd spd;
2220 struct ice_link_status *li;
2221 bool fc = false;
2222 bool rs = false;
2223 bool onestep;
2224 u32 val;
2225 int err;
2226
2227 onestep = hw->ptp.phy.eth56g.onestep_ena;
2228 li = &hw->port_info->phy.link_info;
2229 spd = ice_phy_get_speed_eth56g(li);
2230 if (!!(li->an_info & ICE_AQ_FEC_EN)) {
2231 if (spd == ICE_ETH56G_LNK_SPD_10G) {
2232 fc = true;
2233 } else {
2234 fc = !!(li->fec_info & ICE_AQ_LINK_25G_KR_FEC_EN);
2235 rs = !!(li->fec_info & ~ICE_AQ_LINK_25G_KR_FEC_EN);
2236 }
2237 }
2238 cfg = ð56g_mac_cfg[spd];
2239
2240 err = ice_write_mac_reg_eth56g(hw, port, PHY_MAC_RX_MODULO, 0);
2241 if (err)
2242 return err;
2243
2244 err = ice_write_mac_reg_eth56g(hw, port, PHY_MAC_TX_MODULO, 0);
2245 if (err)
2246 return err;
2247
2248 val = FIELD_PREP(PHY_MAC_TSU_CFG_TX_MODE_M,
2249 cfg->tx_mode.def + rs * cfg->tx_mode.rs) |
2250 FIELD_PREP(PHY_MAC_TSU_CFG_TX_MII_MK_DLY_M, cfg->tx_mk_dly) |
2251 FIELD_PREP(PHY_MAC_TSU_CFG_TX_MII_CW_DLY_M,
2252 cfg->tx_cw_dly.def +
2253 onestep * cfg->tx_cw_dly.onestep) |
2254 FIELD_PREP(PHY_MAC_TSU_CFG_RX_MODE_M,
2255 cfg->rx_mode.def + rs * cfg->rx_mode.rs) |
2256 FIELD_PREP(PHY_MAC_TSU_CFG_RX_MII_MK_DLY_M,
2257 cfg->rx_mk_dly.def + rs * cfg->rx_mk_dly.rs) |
2258 FIELD_PREP(PHY_MAC_TSU_CFG_RX_MII_CW_DLY_M,
2259 cfg->rx_cw_dly.def + rs * cfg->rx_cw_dly.rs) |
2260 FIELD_PREP(PHY_MAC_TSU_CFG_BLKS_PER_CLK_M, cfg->blks_per_clk);
2261 err = ice_write_mac_reg_eth56g(hw, port, PHY_MAC_TSU_CONFIG, val);
2262 if (err)
2263 return err;
2264
2265 err = ice_write_mac_reg_eth56g(hw, port, PHY_MAC_BLOCKTIME,
2266 cfg->blktime);
2267 if (err)
2268 return err;
2269
2270 err = ice_phy_set_offsets_eth56g(hw, port, spd, cfg, fc, rs);
2271 if (err)
2272 return err;
2273
2274 if (spd == ICE_ETH56G_LNK_SPD_25G && !rs)
2275 val = 0;
2276 else
2277 val = cfg->mktime;
2278
2279 return ice_write_mac_reg_eth56g(hw, port, PHY_MAC_MARKERTIME, val);
2280 }
2281
2282 /**
2283 * ice_phy_cfg_intr_eth56g - Configure TX timestamp interrupt
2284 * @hw: pointer to the HW struct
2285 * @port: the timestamp port
2286 * @ena: enable or disable interrupt
2287 * @threshold: interrupt threshold
2288 *
2289 * Configure TX timestamp interrupt for the specified port
2290 *
2291 * Return:
2292 * * %0 - success
2293 * * %other - PHY read/write failed
2294 */
ice_phy_cfg_intr_eth56g(struct ice_hw * hw,u8 port,bool ena,u8 threshold)2295 int ice_phy_cfg_intr_eth56g(struct ice_hw *hw, u8 port, bool ena, u8 threshold)
2296 {
2297 int err;
2298 u32 val;
2299
2300 err = ice_read_ptp_reg_eth56g(hw, port, PHY_REG_TS_INT_CONFIG, &val);
2301 if (err)
2302 return err;
2303
2304 if (ena) {
2305 val |= PHY_TS_INT_CONFIG_ENA_M;
2306 val &= ~PHY_TS_INT_CONFIG_THRESHOLD_M;
2307 val |= FIELD_PREP(PHY_TS_INT_CONFIG_THRESHOLD_M, threshold);
2308 } else {
2309 val &= ~PHY_TS_INT_CONFIG_ENA_M;
2310 }
2311
2312 return ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TS_INT_CONFIG, val);
2313 }
2314
2315 /**
2316 * ice_read_phy_and_phc_time_eth56g - Simultaneously capture PHC and PHY time
2317 * @hw: pointer to the HW struct
2318 * @port: the PHY port to read
2319 * @phy_time: on return, the 64bit PHY timer value
2320 * @phc_time: on return, the lower 64bits of PHC time
2321 *
2322 * Issue a ICE_PTP_READ_TIME timer command to simultaneously capture the PHY
2323 * and PHC timer values.
2324 *
2325 * Return:
2326 * * %0 - success
2327 * * %other - PHY read/write failed
2328 */
ice_read_phy_and_phc_time_eth56g(struct ice_hw * hw,u8 port,u64 * phy_time,u64 * phc_time)2329 static int ice_read_phy_and_phc_time_eth56g(struct ice_hw *hw, u8 port,
2330 u64 *phy_time, u64 *phc_time)
2331 {
2332 u64 tx_time, rx_time;
2333 u32 zo, lo;
2334 u8 tmr_idx;
2335 int err;
2336
2337 tmr_idx = ice_get_ptp_src_clock_index(hw);
2338
2339 /* Prepare the PHC timer for a ICE_PTP_READ_TIME capture command */
2340 ice_ptp_src_cmd(hw, ICE_PTP_READ_TIME);
2341
2342 /* Prepare the PHY timer for a ICE_PTP_READ_TIME capture command */
2343 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_READ_TIME);
2344 if (err)
2345 return err;
2346
2347 /* Issue the sync to start the ICE_PTP_READ_TIME capture */
2348 ice_ptp_exec_tmr_cmd(hw);
2349
2350 /* Read the captured PHC time from the shadow time registers */
2351 zo = rd32(hw, GLTSYN_SHTIME_0(tmr_idx));
2352 lo = rd32(hw, GLTSYN_SHTIME_L(tmr_idx));
2353 *phc_time = (u64)lo << 32 | zo;
2354
2355 /* Read the captured PHY time from the PHY shadow registers */
2356 err = ice_ptp_read_port_capture_eth56g(hw, port, &tx_time, &rx_time);
2357 if (err)
2358 return err;
2359
2360 /* If the PHY Tx and Rx timers don't match, log a warning message.
2361 * Note that this should not happen in normal circumstances since the
2362 * driver always programs them together.
2363 */
2364 if (tx_time != rx_time)
2365 dev_warn(ice_hw_to_dev(hw), "PHY port %u Tx and Rx timers do not match, tx_time 0x%016llX, rx_time 0x%016llX\n",
2366 port, tx_time, rx_time);
2367
2368 *phy_time = tx_time;
2369
2370 return 0;
2371 }
2372
2373 /**
2374 * ice_sync_phy_timer_eth56g - Synchronize the PHY timer with PHC timer
2375 * @hw: pointer to the HW struct
2376 * @port: the PHY port to synchronize
2377 *
2378 * Perform an adjustment to ensure that the PHY and PHC timers are in sync.
2379 * This is done by issuing a ICE_PTP_READ_TIME command which triggers a
2380 * simultaneous read of the PHY timer and PHC timer. Then we use the
2381 * difference to calculate an appropriate 2s complement addition to add
2382 * to the PHY timer in order to ensure it reads the same value as the
2383 * primary PHC timer.
2384 *
2385 * Return:
2386 * * %0 - success
2387 * * %-EBUSY- failed to acquire PTP semaphore
2388 * * %other - PHY read/write failed
2389 */
ice_sync_phy_timer_eth56g(struct ice_hw * hw,u8 port)2390 static int ice_sync_phy_timer_eth56g(struct ice_hw *hw, u8 port)
2391 {
2392 u64 phc_time, phy_time, difference;
2393 int err;
2394
2395 if (!ice_ptp_lock(hw)) {
2396 ice_debug(hw, ICE_DBG_PTP, "Failed to acquire PTP semaphore\n");
2397 return -EBUSY;
2398 }
2399
2400 err = ice_read_phy_and_phc_time_eth56g(hw, port, &phy_time, &phc_time);
2401 if (err)
2402 goto err_unlock;
2403
2404 /* Calculate the amount required to add to the port time in order for
2405 * it to match the PHC time.
2406 *
2407 * Note that the port adjustment is done using 2s complement
2408 * arithmetic. This is convenient since it means that we can simply
2409 * calculate the difference between the PHC time and the port time,
2410 * and it will be interpreted correctly.
2411 */
2412
2413 ice_ptp_src_cmd(hw, ICE_PTP_NOP);
2414 difference = phc_time - phy_time;
2415
2416 err = ice_ptp_prep_port_adj_eth56g(hw, port, (s64)difference);
2417 if (err)
2418 goto err_unlock;
2419
2420 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_ADJ_TIME);
2421 if (err)
2422 goto err_unlock;
2423
2424 /* Issue the sync to activate the time adjustment */
2425 ice_ptp_exec_tmr_cmd(hw);
2426
2427 /* Re-capture the timer values to flush the command registers and
2428 * verify that the time was properly adjusted.
2429 */
2430 err = ice_read_phy_and_phc_time_eth56g(hw, port, &phy_time, &phc_time);
2431 if (err)
2432 goto err_unlock;
2433
2434 dev_info(ice_hw_to_dev(hw),
2435 "Port %u PHY time synced to PHC: 0x%016llX, 0x%016llX\n",
2436 port, phy_time, phc_time);
2437
2438 err_unlock:
2439 ice_ptp_unlock(hw);
2440 return err;
2441 }
2442
2443 /**
2444 * ice_stop_phy_timer_eth56g - Stop the PHY clock timer
2445 * @hw: pointer to the HW struct
2446 * @port: the PHY port to stop
2447 * @soft_reset: if true, hold the SOFT_RESET bit of PHY_REG_PS
2448 *
2449 * Stop the clock of a PHY port. This must be done as part of the flow to
2450 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is
2451 * initialized or when link speed changes.
2452 *
2453 * Return:
2454 * * %0 - success
2455 * * %other - failed to write to PHY
2456 */
ice_stop_phy_timer_eth56g(struct ice_hw * hw,u8 port,bool soft_reset)2457 int ice_stop_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool soft_reset)
2458 {
2459 int err;
2460
2461 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_OFFSET_READY, 0);
2462 if (err)
2463 return err;
2464
2465 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_OFFSET_READY, 0);
2466 if (err)
2467 return err;
2468
2469 ice_debug(hw, ICE_DBG_PTP, "Disabled clock on PHY port %u\n", port);
2470
2471 return 0;
2472 }
2473
2474 /**
2475 * ice_start_phy_timer_eth56g - Start the PHY clock timer
2476 * @hw: pointer to the HW struct
2477 * @port: the PHY port to start
2478 *
2479 * Start the clock of a PHY port. This must be done as part of the flow to
2480 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is
2481 * initialized or when link speed changes.
2482 *
2483 * Return:
2484 * * %0 - success
2485 * * %other - PHY read/write failed
2486 */
ice_start_phy_timer_eth56g(struct ice_hw * hw,u8 port)2487 int ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port)
2488 {
2489 u32 lo, hi;
2490 u64 incval;
2491 u8 tmr_idx;
2492 int err;
2493
2494 tmr_idx = ice_get_ptp_src_clock_index(hw);
2495
2496 err = ice_stop_phy_timer_eth56g(hw, port, false);
2497 if (err)
2498 return err;
2499
2500 ice_ptp_src_cmd(hw, ICE_PTP_NOP);
2501
2502 err = ice_phy_cfg_parpcs_eth56g(hw, port);
2503 if (err)
2504 return err;
2505
2506 err = ice_phy_cfg_ptp_1step_eth56g(hw, port);
2507 if (err)
2508 return err;
2509
2510 err = ice_phy_cfg_mac_eth56g(hw, port);
2511 if (err)
2512 return err;
2513
2514 lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx));
2515 hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx));
2516 incval = (u64)hi << 32 | lo;
2517
2518 err = ice_write_40b_ptp_reg_eth56g(hw, port, PHY_REG_TIMETUS_L, incval);
2519 if (err)
2520 return err;
2521
2522 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_INIT_INCVAL);
2523 if (err)
2524 return err;
2525
2526 ice_ptp_exec_tmr_cmd(hw);
2527
2528 err = ice_sync_phy_timer_eth56g(hw, port);
2529 if (err)
2530 return err;
2531
2532 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_OFFSET_READY, 1);
2533 if (err)
2534 return err;
2535
2536 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_OFFSET_READY, 1);
2537 if (err)
2538 return err;
2539
2540 ice_debug(hw, ICE_DBG_PTP, "Enabled clock on PHY port %u\n", port);
2541
2542 return 0;
2543 }
2544
2545 /**
2546 * ice_sb_access_ena_eth56g - Enable SB devices (PHY and others) access
2547 * @hw: pointer to HW struct
2548 * @enable: Enable or disable access
2549 *
2550 * Enable sideband devices (PHY and others) access.
2551 */
ice_sb_access_ena_eth56g(struct ice_hw * hw,bool enable)2552 static void ice_sb_access_ena_eth56g(struct ice_hw *hw, bool enable)
2553 {
2554 u32 val = rd32(hw, PF_SB_REM_DEV_CTL);
2555
2556 if (enable)
2557 val |= BIT(eth56g_phy_0) | BIT(cgu) | BIT(eth56g_phy_1);
2558 else
2559 val &= ~(BIT(eth56g_phy_0) | BIT(cgu) | BIT(eth56g_phy_1));
2560
2561 wr32(hw, PF_SB_REM_DEV_CTL, val);
2562 }
2563
2564 /**
2565 * ice_ptp_init_phc_eth56g - Perform E82X specific PHC initialization
2566 * @hw: pointer to HW struct
2567 *
2568 * Perform PHC initialization steps specific to E82X devices.
2569 *
2570 * Return:
2571 * * %0 - success
2572 * * %other - failed to initialize CGU
2573 */
ice_ptp_init_phc_eth56g(struct ice_hw * hw)2574 static int ice_ptp_init_phc_eth56g(struct ice_hw *hw)
2575 {
2576 ice_sb_access_ena_eth56g(hw, true);
2577 /* Initialize the Clock Generation Unit */
2578 return ice_init_cgu_e82x(hw);
2579 }
2580
2581 /**
2582 * ice_ptp_read_tx_hwtstamp_status_eth56g - Get TX timestamp status
2583 * @hw: pointer to the HW struct
2584 * @ts_status: the timestamp mask pointer
2585 *
2586 * Read the PHY Tx timestamp status mask indicating which ports have Tx
2587 * timestamps available.
2588 *
2589 * Return:
2590 * * %0 - success
2591 * * %other - failed to read from PHY
2592 */
ice_ptp_read_tx_hwtstamp_status_eth56g(struct ice_hw * hw,u32 * ts_status)2593 int ice_ptp_read_tx_hwtstamp_status_eth56g(struct ice_hw *hw, u32 *ts_status)
2594 {
2595 const struct ice_eth56g_params *params = &hw->ptp.phy.eth56g;
2596 u8 phy, mask;
2597 u32 status;
2598
2599 mask = (1 << hw->ptp.ports_per_phy) - 1;
2600 *ts_status = 0;
2601
2602 for (phy = 0; phy < params->num_phys; phy++) {
2603 int err;
2604
2605 err = ice_read_phy_eth56g(hw, phy, PHY_PTP_INT_STATUS, &status);
2606 if (err)
2607 return err;
2608
2609 *ts_status |= (status & mask) << (phy * hw->ptp.ports_per_phy);
2610 }
2611
2612 ice_debug(hw, ICE_DBG_PTP, "PHY interrupt err: %x\n", *ts_status);
2613
2614 return 0;
2615 }
2616
2617 /**
2618 * ice_get_phy_tx_tstamp_ready_eth56g - Read the Tx memory status register
2619 * @hw: pointer to the HW struct
2620 * @port: the PHY port to read from
2621 * @tstamp_ready: contents of the Tx memory status register
2622 *
2623 * Read the PHY_REG_TX_MEMORY_STATUS register indicating which timestamps in
2624 * the PHY are ready. A set bit means the corresponding timestamp is valid and
2625 * ready to be captured from the PHY timestamp block.
2626 *
2627 * Return:
2628 * * %0 - success
2629 * * %other - failed to read from PHY
2630 */
ice_get_phy_tx_tstamp_ready_eth56g(struct ice_hw * hw,u8 port,u64 * tstamp_ready)2631 static int ice_get_phy_tx_tstamp_ready_eth56g(struct ice_hw *hw, u8 port,
2632 u64 *tstamp_ready)
2633 {
2634 int err;
2635
2636 err = ice_read_64b_ptp_reg_eth56g(hw, port, PHY_REG_TX_MEMORY_STATUS_L,
2637 tstamp_ready);
2638 if (err) {
2639 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS for port %u, err %d\n",
2640 port, err);
2641 return err;
2642 }
2643
2644 return 0;
2645 }
2646
2647 /**
2648 * ice_is_muxed_topo - detect breakout 2x50G topology for E825C
2649 * @hw: pointer to the HW struct
2650 *
2651 * Return: true if it's 2x50 breakout topology, false otherwise
2652 */
ice_is_muxed_topo(struct ice_hw * hw)2653 static bool ice_is_muxed_topo(struct ice_hw *hw)
2654 {
2655 u8 link_topo;
2656 bool mux;
2657 u32 val;
2658
2659 val = rd32(hw, GLGEN_SWITCH_MODE_CONFIG);
2660 mux = FIELD_GET(GLGEN_SWITCH_MODE_CONFIG_25X4_QUAD_M, val);
2661 val = rd32(hw, GLGEN_MAC_LINK_TOPO);
2662 link_topo = FIELD_GET(GLGEN_MAC_LINK_TOPO_LINK_TOPO_M, val);
2663
2664 return (mux && link_topo == ICE_LINK_TOPO_UP_TO_2_LINKS);
2665 }
2666
2667 /**
2668 * ice_ptp_init_phy_e825c - initialize PHY parameters
2669 * @hw: pointer to the HW struct
2670 */
ice_ptp_init_phy_e825c(struct ice_hw * hw)2671 static void ice_ptp_init_phy_e825c(struct ice_hw *hw)
2672 {
2673 struct ice_ptp_hw *ptp = &hw->ptp;
2674 struct ice_eth56g_params *params;
2675 u8 phy;
2676
2677 ptp->phy_model = ICE_PHY_ETH56G;
2678 params = &ptp->phy.eth56g;
2679 params->onestep_ena = false;
2680 params->peer_delay = 0;
2681 params->sfd_ena = false;
2682 params->phy_addr[0] = eth56g_phy_0;
2683 params->phy_addr[1] = eth56g_phy_1;
2684 params->num_phys = 2;
2685 ptp->ports_per_phy = 4;
2686 ptp->num_lports = params->num_phys * ptp->ports_per_phy;
2687
2688 ice_sb_access_ena_eth56g(hw, true);
2689 for (phy = 0; phy < params->num_phys; phy++) {
2690 u32 phy_rev;
2691 int err;
2692
2693 err = ice_read_phy_eth56g(hw, phy, PHY_REG_REVISION, &phy_rev);
2694 if (err || phy_rev != PHY_REVISION_ETH56G) {
2695 ptp->phy_model = ICE_PHY_UNSUP;
2696 return;
2697 }
2698 }
2699
2700 ptp->is_2x50g_muxed_topo = ice_is_muxed_topo(hw);
2701 }
2702
2703 /* E822 family functions
2704 *
2705 * The following functions operate on the E822 family of devices.
2706 */
2707
2708 /**
2709 * ice_fill_phy_msg_e82x - Fill message data for a PHY register access
2710 * @hw: pointer to the HW struct
2711 * @msg: the PHY message buffer to fill in
2712 * @port: the port to access
2713 * @offset: the register offset
2714 */
ice_fill_phy_msg_e82x(struct ice_hw * hw,struct ice_sbq_msg_input * msg,u8 port,u16 offset)2715 static void ice_fill_phy_msg_e82x(struct ice_hw *hw,
2716 struct ice_sbq_msg_input *msg, u8 port,
2717 u16 offset)
2718 {
2719 int phy_port, phy, quadtype;
2720
2721 phy_port = port % hw->ptp.ports_per_phy;
2722 phy = port / hw->ptp.ports_per_phy;
2723 quadtype = ICE_GET_QUAD_NUM(port) %
2724 ICE_GET_QUAD_NUM(hw->ptp.ports_per_phy);
2725
2726 if (quadtype == 0) {
2727 msg->msg_addr_low = P_Q0_L(P_0_BASE + offset, phy_port);
2728 msg->msg_addr_high = P_Q0_H(P_0_BASE + offset, phy_port);
2729 } else {
2730 msg->msg_addr_low = P_Q1_L(P_4_BASE + offset, phy_port);
2731 msg->msg_addr_high = P_Q1_H(P_4_BASE + offset, phy_port);
2732 }
2733
2734 if (phy == 0)
2735 msg->dest_dev = rmn_0;
2736 else if (phy == 1)
2737 msg->dest_dev = rmn_1;
2738 else
2739 msg->dest_dev = rmn_2;
2740 }
2741
2742 /**
2743 * ice_is_64b_phy_reg_e82x - Check if this is a 64bit PHY register
2744 * @low_addr: the low address to check
2745 * @high_addr: on return, contains the high address of the 64bit register
2746 *
2747 * Checks if the provided low address is one of the known 64bit PHY values
2748 * represented as two 32bit registers. If it is, return the appropriate high
2749 * register offset to use.
2750 */
ice_is_64b_phy_reg_e82x(u16 low_addr,u16 * high_addr)2751 static bool ice_is_64b_phy_reg_e82x(u16 low_addr, u16 *high_addr)
2752 {
2753 switch (low_addr) {
2754 case P_REG_PAR_PCS_TX_OFFSET_L:
2755 *high_addr = P_REG_PAR_PCS_TX_OFFSET_U;
2756 return true;
2757 case P_REG_PAR_PCS_RX_OFFSET_L:
2758 *high_addr = P_REG_PAR_PCS_RX_OFFSET_U;
2759 return true;
2760 case P_REG_PAR_TX_TIME_L:
2761 *high_addr = P_REG_PAR_TX_TIME_U;
2762 return true;
2763 case P_REG_PAR_RX_TIME_L:
2764 *high_addr = P_REG_PAR_RX_TIME_U;
2765 return true;
2766 case P_REG_TOTAL_TX_OFFSET_L:
2767 *high_addr = P_REG_TOTAL_TX_OFFSET_U;
2768 return true;
2769 case P_REG_TOTAL_RX_OFFSET_L:
2770 *high_addr = P_REG_TOTAL_RX_OFFSET_U;
2771 return true;
2772 case P_REG_UIX66_10G_40G_L:
2773 *high_addr = P_REG_UIX66_10G_40G_U;
2774 return true;
2775 case P_REG_UIX66_25G_100G_L:
2776 *high_addr = P_REG_UIX66_25G_100G_U;
2777 return true;
2778 case P_REG_TX_CAPTURE_L:
2779 *high_addr = P_REG_TX_CAPTURE_U;
2780 return true;
2781 case P_REG_RX_CAPTURE_L:
2782 *high_addr = P_REG_RX_CAPTURE_U;
2783 return true;
2784 case P_REG_TX_TIMER_INC_PRE_L:
2785 *high_addr = P_REG_TX_TIMER_INC_PRE_U;
2786 return true;
2787 case P_REG_RX_TIMER_INC_PRE_L:
2788 *high_addr = P_REG_RX_TIMER_INC_PRE_U;
2789 return true;
2790 default:
2791 return false;
2792 }
2793 }
2794
2795 /**
2796 * ice_is_40b_phy_reg_e82x - Check if this is a 40bit PHY register
2797 * @low_addr: the low address to check
2798 * @high_addr: on return, contains the high address of the 40bit value
2799 *
2800 * Checks if the provided low address is one of the known 40bit PHY values
2801 * split into two registers with the lower 8 bits in the low register and the
2802 * upper 32 bits in the high register. If it is, return the appropriate high
2803 * register offset to use.
2804 */
ice_is_40b_phy_reg_e82x(u16 low_addr,u16 * high_addr)2805 static bool ice_is_40b_phy_reg_e82x(u16 low_addr, u16 *high_addr)
2806 {
2807 switch (low_addr) {
2808 case P_REG_TIMETUS_L:
2809 *high_addr = P_REG_TIMETUS_U;
2810 return true;
2811 case P_REG_PAR_RX_TUS_L:
2812 *high_addr = P_REG_PAR_RX_TUS_U;
2813 return true;
2814 case P_REG_PAR_TX_TUS_L:
2815 *high_addr = P_REG_PAR_TX_TUS_U;
2816 return true;
2817 case P_REG_PCS_RX_TUS_L:
2818 *high_addr = P_REG_PCS_RX_TUS_U;
2819 return true;
2820 case P_REG_PCS_TX_TUS_L:
2821 *high_addr = P_REG_PCS_TX_TUS_U;
2822 return true;
2823 case P_REG_DESK_PAR_RX_TUS_L:
2824 *high_addr = P_REG_DESK_PAR_RX_TUS_U;
2825 return true;
2826 case P_REG_DESK_PAR_TX_TUS_L:
2827 *high_addr = P_REG_DESK_PAR_TX_TUS_U;
2828 return true;
2829 case P_REG_DESK_PCS_RX_TUS_L:
2830 *high_addr = P_REG_DESK_PCS_RX_TUS_U;
2831 return true;
2832 case P_REG_DESK_PCS_TX_TUS_L:
2833 *high_addr = P_REG_DESK_PCS_TX_TUS_U;
2834 return true;
2835 default:
2836 return false;
2837 }
2838 }
2839
2840 /**
2841 * ice_read_phy_reg_e82x - Read a PHY register
2842 * @hw: pointer to the HW struct
2843 * @port: PHY port to read from
2844 * @offset: PHY register offset to read
2845 * @val: on return, the contents read from the PHY
2846 *
2847 * Read a PHY register for the given port over the device sideband queue.
2848 */
2849 static int
ice_read_phy_reg_e82x(struct ice_hw * hw,u8 port,u16 offset,u32 * val)2850 ice_read_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 offset, u32 *val)
2851 {
2852 struct ice_sbq_msg_input msg = {0};
2853 int err;
2854
2855 ice_fill_phy_msg_e82x(hw, &msg, port, offset);
2856 msg.opcode = ice_sbq_msg_rd;
2857
2858 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD);
2859 if (err) {
2860 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n",
2861 err);
2862 return err;
2863 }
2864
2865 *val = msg.data;
2866
2867 return 0;
2868 }
2869
2870 /**
2871 * ice_read_64b_phy_reg_e82x - Read a 64bit value from PHY registers
2872 * @hw: pointer to the HW struct
2873 * @port: PHY port to read from
2874 * @low_addr: offset of the lower register to read from
2875 * @val: on return, the contents of the 64bit value from the PHY registers
2876 *
2877 * Reads the two registers associated with a 64bit value and returns it in the
2878 * val pointer. The offset always specifies the lower register offset to use.
2879 * The high offset is looked up. This function only operates on registers
2880 * known to be two parts of a 64bit value.
2881 */
2882 static int
ice_read_64b_phy_reg_e82x(struct ice_hw * hw,u8 port,u16 low_addr,u64 * val)2883 ice_read_64b_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 low_addr, u64 *val)
2884 {
2885 u32 low, high;
2886 u16 high_addr;
2887 int err;
2888
2889 /* Only operate on registers known to be split into two 32bit
2890 * registers.
2891 */
2892 if (!ice_is_64b_phy_reg_e82x(low_addr, &high_addr)) {
2893 ice_debug(hw, ICE_DBG_PTP, "Invalid 64b register addr 0x%08x\n",
2894 low_addr);
2895 return -EINVAL;
2896 }
2897
2898 err = ice_read_phy_reg_e82x(hw, port, low_addr, &low);
2899 if (err) {
2900 ice_debug(hw, ICE_DBG_PTP, "Failed to read from low register 0x%08x\n, err %d",
2901 low_addr, err);
2902 return err;
2903 }
2904
2905 err = ice_read_phy_reg_e82x(hw, port, high_addr, &high);
2906 if (err) {
2907 ice_debug(hw, ICE_DBG_PTP, "Failed to read from high register 0x%08x\n, err %d",
2908 high_addr, err);
2909 return err;
2910 }
2911
2912 *val = (u64)high << 32 | low;
2913
2914 return 0;
2915 }
2916
2917 /**
2918 * ice_write_phy_reg_e82x - Write a PHY register
2919 * @hw: pointer to the HW struct
2920 * @port: PHY port to write to
2921 * @offset: PHY register offset to write
2922 * @val: The value to write to the register
2923 *
2924 * Write a PHY register for the given port over the device sideband queue.
2925 */
2926 static int
ice_write_phy_reg_e82x(struct ice_hw * hw,u8 port,u16 offset,u32 val)2927 ice_write_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 offset, u32 val)
2928 {
2929 struct ice_sbq_msg_input msg = {0};
2930 int err;
2931
2932 ice_fill_phy_msg_e82x(hw, &msg, port, offset);
2933 msg.opcode = ice_sbq_msg_wr;
2934 msg.data = val;
2935
2936 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD);
2937 if (err) {
2938 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n",
2939 err);
2940 return err;
2941 }
2942
2943 return 0;
2944 }
2945
2946 /**
2947 * ice_write_40b_phy_reg_e82x - Write a 40b value to the PHY
2948 * @hw: pointer to the HW struct
2949 * @port: port to write to
2950 * @low_addr: offset of the low register
2951 * @val: 40b value to write
2952 *
2953 * Write the provided 40b value to the two associated registers by splitting
2954 * it up into two chunks, the lower 8 bits and the upper 32 bits.
2955 */
2956 static int
ice_write_40b_phy_reg_e82x(struct ice_hw * hw,u8 port,u16 low_addr,u64 val)2957 ice_write_40b_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 low_addr, u64 val)
2958 {
2959 u32 low, high;
2960 u16 high_addr;
2961 int err;
2962
2963 /* Only operate on registers known to be split into a lower 8 bit
2964 * register and an upper 32 bit register.
2965 */
2966 if (!ice_is_40b_phy_reg_e82x(low_addr, &high_addr)) {
2967 ice_debug(hw, ICE_DBG_PTP, "Invalid 40b register addr 0x%08x\n",
2968 low_addr);
2969 return -EINVAL;
2970 }
2971 low = FIELD_GET(P_REG_40B_LOW_M, val);
2972 high = (u32)(val >> P_REG_40B_HIGH_S);
2973
2974 err = ice_write_phy_reg_e82x(hw, port, low_addr, low);
2975 if (err) {
2976 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d",
2977 low_addr, err);
2978 return err;
2979 }
2980
2981 err = ice_write_phy_reg_e82x(hw, port, high_addr, high);
2982 if (err) {
2983 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d",
2984 high_addr, err);
2985 return err;
2986 }
2987
2988 return 0;
2989 }
2990
2991 /**
2992 * ice_write_64b_phy_reg_e82x - Write a 64bit value to PHY registers
2993 * @hw: pointer to the HW struct
2994 * @port: PHY port to read from
2995 * @low_addr: offset of the lower register to read from
2996 * @val: the contents of the 64bit value to write to PHY
2997 *
2998 * Write the 64bit value to the two associated 32bit PHY registers. The offset
2999 * is always specified as the lower register, and the high address is looked
3000 * up. This function only operates on registers known to be two parts of
3001 * a 64bit value.
3002 */
3003 static int
ice_write_64b_phy_reg_e82x(struct ice_hw * hw,u8 port,u16 low_addr,u64 val)3004 ice_write_64b_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 low_addr, u64 val)
3005 {
3006 u32 low, high;
3007 u16 high_addr;
3008 int err;
3009
3010 /* Only operate on registers known to be split into two 32bit
3011 * registers.
3012 */
3013 if (!ice_is_64b_phy_reg_e82x(low_addr, &high_addr)) {
3014 ice_debug(hw, ICE_DBG_PTP, "Invalid 64b register addr 0x%08x\n",
3015 low_addr);
3016 return -EINVAL;
3017 }
3018
3019 low = lower_32_bits(val);
3020 high = upper_32_bits(val);
3021
3022 err = ice_write_phy_reg_e82x(hw, port, low_addr, low);
3023 if (err) {
3024 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d",
3025 low_addr, err);
3026 return err;
3027 }
3028
3029 err = ice_write_phy_reg_e82x(hw, port, high_addr, high);
3030 if (err) {
3031 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d",
3032 high_addr, err);
3033 return err;
3034 }
3035
3036 return 0;
3037 }
3038
3039 /**
3040 * ice_fill_quad_msg_e82x - Fill message data for quad register access
3041 * @hw: pointer to the HW struct
3042 * @msg: the PHY message buffer to fill in
3043 * @quad: the quad to access
3044 * @offset: the register offset
3045 *
3046 * Fill a message buffer for accessing a register in a quad shared between
3047 * multiple PHYs.
3048 *
3049 * Return:
3050 * * %0 - OK
3051 * * %-EINVAL - invalid quad number
3052 */
ice_fill_quad_msg_e82x(struct ice_hw * hw,struct ice_sbq_msg_input * msg,u8 quad,u16 offset)3053 static int ice_fill_quad_msg_e82x(struct ice_hw *hw,
3054 struct ice_sbq_msg_input *msg, u8 quad,
3055 u16 offset)
3056 {
3057 u32 addr;
3058
3059 if (quad >= ICE_GET_QUAD_NUM(hw->ptp.num_lports))
3060 return -EINVAL;
3061
3062 msg->dest_dev = rmn_0;
3063
3064 if (!(quad % ICE_GET_QUAD_NUM(hw->ptp.ports_per_phy)))
3065 addr = Q_0_BASE + offset;
3066 else
3067 addr = Q_1_BASE + offset;
3068
3069 msg->msg_addr_low = lower_16_bits(addr);
3070 msg->msg_addr_high = upper_16_bits(addr);
3071
3072 return 0;
3073 }
3074
3075 /**
3076 * ice_read_quad_reg_e82x - Read a PHY quad register
3077 * @hw: pointer to the HW struct
3078 * @quad: quad to read from
3079 * @offset: quad register offset to read
3080 * @val: on return, the contents read from the quad
3081 *
3082 * Read a quad register over the device sideband queue. Quad registers are
3083 * shared between multiple PHYs.
3084 */
3085 int
ice_read_quad_reg_e82x(struct ice_hw * hw,u8 quad,u16 offset,u32 * val)3086 ice_read_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 *val)
3087 {
3088 struct ice_sbq_msg_input msg = {0};
3089 int err;
3090
3091 err = ice_fill_quad_msg_e82x(hw, &msg, quad, offset);
3092 if (err)
3093 return err;
3094
3095 msg.opcode = ice_sbq_msg_rd;
3096
3097 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD);
3098 if (err) {
3099 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n",
3100 err);
3101 return err;
3102 }
3103
3104 *val = msg.data;
3105
3106 return 0;
3107 }
3108
3109 /**
3110 * ice_write_quad_reg_e82x - Write a PHY quad register
3111 * @hw: pointer to the HW struct
3112 * @quad: quad to write to
3113 * @offset: quad register offset to write
3114 * @val: The value to write to the register
3115 *
3116 * Write a quad register over the device sideband queue. Quad registers are
3117 * shared between multiple PHYs.
3118 */
3119 int
ice_write_quad_reg_e82x(struct ice_hw * hw,u8 quad,u16 offset,u32 val)3120 ice_write_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 val)
3121 {
3122 struct ice_sbq_msg_input msg = {0};
3123 int err;
3124
3125 err = ice_fill_quad_msg_e82x(hw, &msg, quad, offset);
3126 if (err)
3127 return err;
3128
3129 msg.opcode = ice_sbq_msg_wr;
3130 msg.data = val;
3131
3132 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD);
3133 if (err) {
3134 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n",
3135 err);
3136 return err;
3137 }
3138
3139 return 0;
3140 }
3141
3142 /**
3143 * ice_read_phy_tstamp_e82x - Read a PHY timestamp out of the quad block
3144 * @hw: pointer to the HW struct
3145 * @quad: the quad to read from
3146 * @idx: the timestamp index to read
3147 * @tstamp: on return, the 40bit timestamp value
3148 *
3149 * Read a 40bit timestamp value out of the two associated registers in the
3150 * quad memory block that is shared between the internal PHYs of the E822
3151 * family of devices.
3152 */
3153 static int
ice_read_phy_tstamp_e82x(struct ice_hw * hw,u8 quad,u8 idx,u64 * tstamp)3154 ice_read_phy_tstamp_e82x(struct ice_hw *hw, u8 quad, u8 idx, u64 *tstamp)
3155 {
3156 u16 lo_addr, hi_addr;
3157 u32 lo, hi;
3158 int err;
3159
3160 lo_addr = (u16)TS_L(Q_REG_TX_MEMORY_BANK_START, idx);
3161 hi_addr = (u16)TS_H(Q_REG_TX_MEMORY_BANK_START, idx);
3162
3163 err = ice_read_quad_reg_e82x(hw, quad, lo_addr, &lo);
3164 if (err) {
3165 ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n",
3166 err);
3167 return err;
3168 }
3169
3170 err = ice_read_quad_reg_e82x(hw, quad, hi_addr, &hi);
3171 if (err) {
3172 ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n",
3173 err);
3174 return err;
3175 }
3176
3177 /* For E822 based internal PHYs, the timestamp is reported with the
3178 * lower 8 bits in the low register, and the upper 32 bits in the high
3179 * register.
3180 */
3181 *tstamp = FIELD_PREP(TS_PHY_HIGH_M, hi) | FIELD_PREP(TS_PHY_LOW_M, lo);
3182
3183 return 0;
3184 }
3185
3186 /**
3187 * ice_clear_phy_tstamp_e82x - Clear a timestamp from the quad block
3188 * @hw: pointer to the HW struct
3189 * @quad: the quad to read from
3190 * @idx: the timestamp index to reset
3191 *
3192 * Read the timestamp out of the quad to clear its timestamp status bit from
3193 * the PHY quad block that is shared between the internal PHYs of the E822
3194 * devices.
3195 *
3196 * Note that unlike E810, software cannot directly write to the quad memory
3197 * bank registers. E822 relies on the ice_get_phy_tx_tstamp_ready() function
3198 * to determine which timestamps are valid. Reading a timestamp auto-clears
3199 * the valid bit.
3200 *
3201 * To directly clear the contents of the timestamp block entirely, discarding
3202 * all timestamp data at once, software should instead use
3203 * ice_ptp_reset_ts_memory_quad_e82x().
3204 *
3205 * This function should only be called on an idx whose bit is set according to
3206 * ice_get_phy_tx_tstamp_ready().
3207 */
3208 static int
ice_clear_phy_tstamp_e82x(struct ice_hw * hw,u8 quad,u8 idx)3209 ice_clear_phy_tstamp_e82x(struct ice_hw *hw, u8 quad, u8 idx)
3210 {
3211 u64 unused_tstamp;
3212 int err;
3213
3214 err = ice_read_phy_tstamp_e82x(hw, quad, idx, &unused_tstamp);
3215 if (err) {
3216 ice_debug(hw, ICE_DBG_PTP, "Failed to read the timestamp register for quad %u, idx %u, err %d\n",
3217 quad, idx, err);
3218 return err;
3219 }
3220
3221 return 0;
3222 }
3223
3224 /**
3225 * ice_ptp_reset_ts_memory_quad_e82x - Clear all timestamps from the quad block
3226 * @hw: pointer to the HW struct
3227 * @quad: the quad to read from
3228 *
3229 * Clear all timestamps from the PHY quad block that is shared between the
3230 * internal PHYs on the E822 devices.
3231 */
ice_ptp_reset_ts_memory_quad_e82x(struct ice_hw * hw,u8 quad)3232 void ice_ptp_reset_ts_memory_quad_e82x(struct ice_hw *hw, u8 quad)
3233 {
3234 ice_write_quad_reg_e82x(hw, quad, Q_REG_TS_CTRL, Q_REG_TS_CTRL_M);
3235 ice_write_quad_reg_e82x(hw, quad, Q_REG_TS_CTRL, ~(u32)Q_REG_TS_CTRL_M);
3236 }
3237
3238 /**
3239 * ice_ptp_reset_ts_memory_e82x - Clear all timestamps from all quad blocks
3240 * @hw: pointer to the HW struct
3241 */
ice_ptp_reset_ts_memory_e82x(struct ice_hw * hw)3242 static void ice_ptp_reset_ts_memory_e82x(struct ice_hw *hw)
3243 {
3244 unsigned int quad;
3245
3246 for (quad = 0; quad < ICE_GET_QUAD_NUM(hw->ptp.num_lports); quad++)
3247 ice_ptp_reset_ts_memory_quad_e82x(hw, quad);
3248 }
3249
3250 /**
3251 * ice_ptp_set_vernier_wl - Set the window length for vernier calibration
3252 * @hw: pointer to the HW struct
3253 *
3254 * Set the window length used for the vernier port calibration process.
3255 */
ice_ptp_set_vernier_wl(struct ice_hw * hw)3256 static int ice_ptp_set_vernier_wl(struct ice_hw *hw)
3257 {
3258 u8 port;
3259
3260 for (port = 0; port < hw->ptp.num_lports; port++) {
3261 int err;
3262
3263 err = ice_write_phy_reg_e82x(hw, port, P_REG_WL,
3264 PTP_VERNIER_WL);
3265 if (err) {
3266 ice_debug(hw, ICE_DBG_PTP, "Failed to set vernier window length for port %u, err %d\n",
3267 port, err);
3268 return err;
3269 }
3270 }
3271
3272 return 0;
3273 }
3274
3275 /**
3276 * ice_ptp_init_phc_e82x - Perform E822 specific PHC initialization
3277 * @hw: pointer to HW struct
3278 *
3279 * Perform PHC initialization steps specific to E822 devices.
3280 */
ice_ptp_init_phc_e82x(struct ice_hw * hw)3281 static int ice_ptp_init_phc_e82x(struct ice_hw *hw)
3282 {
3283 int err;
3284 u32 val;
3285
3286 /* Enable reading switch and PHY registers over the sideband queue */
3287 #define PF_SB_REM_DEV_CTL_SWITCH_READ BIT(1)
3288 #define PF_SB_REM_DEV_CTL_PHY0 BIT(2)
3289 val = rd32(hw, PF_SB_REM_DEV_CTL);
3290 val |= (PF_SB_REM_DEV_CTL_SWITCH_READ | PF_SB_REM_DEV_CTL_PHY0);
3291 wr32(hw, PF_SB_REM_DEV_CTL, val);
3292
3293 /* Initialize the Clock Generation Unit */
3294 err = ice_init_cgu_e82x(hw);
3295 if (err)
3296 return err;
3297
3298 /* Set window length for all the ports */
3299 return ice_ptp_set_vernier_wl(hw);
3300 }
3301
3302 /**
3303 * ice_ptp_prep_phy_time_e82x - Prepare PHY port with initial time
3304 * @hw: pointer to the HW struct
3305 * @time: Time to initialize the PHY port clocks to
3306 *
3307 * Program the PHY port registers with a new initial time value. The port
3308 * clock will be initialized once the driver issues an ICE_PTP_INIT_TIME sync
3309 * command. The time value is the upper 32 bits of the PHY timer, usually in
3310 * units of nominal nanoseconds.
3311 */
3312 static int
ice_ptp_prep_phy_time_e82x(struct ice_hw * hw,u32 time)3313 ice_ptp_prep_phy_time_e82x(struct ice_hw *hw, u32 time)
3314 {
3315 u64 phy_time;
3316 u8 port;
3317 int err;
3318
3319 /* The time represents the upper 32 bits of the PHY timer, so we need
3320 * to shift to account for this when programming.
3321 */
3322 phy_time = (u64)time << 32;
3323
3324 for (port = 0; port < hw->ptp.num_lports; port++) {
3325 /* Tx case */
3326 err = ice_write_64b_phy_reg_e82x(hw, port,
3327 P_REG_TX_TIMER_INC_PRE_L,
3328 phy_time);
3329 if (err)
3330 goto exit_err;
3331
3332 /* Rx case */
3333 err = ice_write_64b_phy_reg_e82x(hw, port,
3334 P_REG_RX_TIMER_INC_PRE_L,
3335 phy_time);
3336 if (err)
3337 goto exit_err;
3338 }
3339
3340 return 0;
3341
3342 exit_err:
3343 ice_debug(hw, ICE_DBG_PTP, "Failed to write init time for port %u, err %d\n",
3344 port, err);
3345
3346 return err;
3347 }
3348
3349 /**
3350 * ice_ptp_prep_port_adj_e82x - Prepare a single port for time adjust
3351 * @hw: pointer to HW struct
3352 * @port: Port number to be programmed
3353 * @time: time in cycles to adjust the port Tx and Rx clocks
3354 *
3355 * Program the port for an atomic adjustment by writing the Tx and Rx timer
3356 * registers. The atomic adjustment won't be completed until the driver issues
3357 * an ICE_PTP_ADJ_TIME command.
3358 *
3359 * Note that time is not in units of nanoseconds. It is in clock time
3360 * including the lower sub-nanosecond portion of the port timer.
3361 *
3362 * Negative adjustments are supported using 2s complement arithmetic.
3363 */
3364 static int
ice_ptp_prep_port_adj_e82x(struct ice_hw * hw,u8 port,s64 time)3365 ice_ptp_prep_port_adj_e82x(struct ice_hw *hw, u8 port, s64 time)
3366 {
3367 u32 l_time, u_time;
3368 int err;
3369
3370 l_time = lower_32_bits(time);
3371 u_time = upper_32_bits(time);
3372
3373 /* Tx case */
3374 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_TIMER_INC_PRE_L,
3375 l_time);
3376 if (err)
3377 goto exit_err;
3378
3379 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_TIMER_INC_PRE_U,
3380 u_time);
3381 if (err)
3382 goto exit_err;
3383
3384 /* Rx case */
3385 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_TIMER_INC_PRE_L,
3386 l_time);
3387 if (err)
3388 goto exit_err;
3389
3390 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_TIMER_INC_PRE_U,
3391 u_time);
3392 if (err)
3393 goto exit_err;
3394
3395 return 0;
3396
3397 exit_err:
3398 ice_debug(hw, ICE_DBG_PTP, "Failed to write time adjust for port %u, err %d\n",
3399 port, err);
3400 return err;
3401 }
3402
3403 /**
3404 * ice_ptp_prep_phy_adj_e82x - Prep PHY ports for a time adjustment
3405 * @hw: pointer to HW struct
3406 * @adj: adjustment in nanoseconds
3407 *
3408 * Prepare the PHY ports for an atomic time adjustment by programming the PHY
3409 * Tx and Rx port registers. The actual adjustment is completed by issuing an
3410 * ICE_PTP_ADJ_TIME or ICE_PTP_ADJ_TIME_AT_TIME sync command.
3411 */
3412 static int
ice_ptp_prep_phy_adj_e82x(struct ice_hw * hw,s32 adj)3413 ice_ptp_prep_phy_adj_e82x(struct ice_hw *hw, s32 adj)
3414 {
3415 s64 cycles;
3416 u8 port;
3417
3418 /* The port clock supports adjustment of the sub-nanosecond portion of
3419 * the clock. We shift the provided adjustment in nanoseconds to
3420 * calculate the appropriate adjustment to program into the PHY ports.
3421 */
3422 if (adj > 0)
3423 cycles = (s64)adj << 32;
3424 else
3425 cycles = -(((s64)-adj) << 32);
3426
3427 for (port = 0; port < hw->ptp.num_lports; port++) {
3428 int err;
3429
3430 err = ice_ptp_prep_port_adj_e82x(hw, port, cycles);
3431 if (err)
3432 return err;
3433 }
3434
3435 return 0;
3436 }
3437
3438 /**
3439 * ice_ptp_prep_phy_incval_e82x - Prepare PHY ports for time adjustment
3440 * @hw: pointer to HW struct
3441 * @incval: new increment value to prepare
3442 *
3443 * Prepare each of the PHY ports for a new increment value by programming the
3444 * port's TIMETUS registers. The new increment value will be updated after
3445 * issuing an ICE_PTP_INIT_INCVAL command.
3446 */
3447 static int
ice_ptp_prep_phy_incval_e82x(struct ice_hw * hw,u64 incval)3448 ice_ptp_prep_phy_incval_e82x(struct ice_hw *hw, u64 incval)
3449 {
3450 int err;
3451 u8 port;
3452
3453 for (port = 0; port < hw->ptp.num_lports; port++) {
3454 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_TIMETUS_L,
3455 incval);
3456 if (err)
3457 goto exit_err;
3458 }
3459
3460 return 0;
3461
3462 exit_err:
3463 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval for port %u, err %d\n",
3464 port, err);
3465
3466 return err;
3467 }
3468
3469 /**
3470 * ice_ptp_read_port_capture - Read a port's local time capture
3471 * @hw: pointer to HW struct
3472 * @port: Port number to read
3473 * @tx_ts: on return, the Tx port time capture
3474 * @rx_ts: on return, the Rx port time capture
3475 *
3476 * Read the port's Tx and Rx local time capture values.
3477 *
3478 * Note this has no equivalent for the E810 devices.
3479 */
3480 static int
ice_ptp_read_port_capture(struct ice_hw * hw,u8 port,u64 * tx_ts,u64 * rx_ts)3481 ice_ptp_read_port_capture(struct ice_hw *hw, u8 port, u64 *tx_ts, u64 *rx_ts)
3482 {
3483 int err;
3484
3485 /* Tx case */
3486 err = ice_read_64b_phy_reg_e82x(hw, port, P_REG_TX_CAPTURE_L, tx_ts);
3487 if (err) {
3488 ice_debug(hw, ICE_DBG_PTP, "Failed to read REG_TX_CAPTURE, err %d\n",
3489 err);
3490 return err;
3491 }
3492
3493 ice_debug(hw, ICE_DBG_PTP, "tx_init = 0x%016llx\n",
3494 (unsigned long long)*tx_ts);
3495
3496 /* Rx case */
3497 err = ice_read_64b_phy_reg_e82x(hw, port, P_REG_RX_CAPTURE_L, rx_ts);
3498 if (err) {
3499 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_CAPTURE, err %d\n",
3500 err);
3501 return err;
3502 }
3503
3504 ice_debug(hw, ICE_DBG_PTP, "rx_init = 0x%016llx\n",
3505 (unsigned long long)*rx_ts);
3506
3507 return 0;
3508 }
3509
3510 /**
3511 * ice_ptp_write_port_cmd_e82x - Prepare a single PHY port for a timer command
3512 * @hw: pointer to HW struct
3513 * @port: Port to which cmd has to be sent
3514 * @cmd: Command to be sent to the port
3515 *
3516 * Prepare the requested port for an upcoming timer sync command.
3517 *
3518 * Note there is no equivalent of this operation on E810, as that device
3519 * always handles all external PHYs internally.
3520 *
3521 * Return:
3522 * * %0 - success
3523 * * %other - failed to write to PHY
3524 */
ice_ptp_write_port_cmd_e82x(struct ice_hw * hw,u8 port,enum ice_ptp_tmr_cmd cmd)3525 static int ice_ptp_write_port_cmd_e82x(struct ice_hw *hw, u8 port,
3526 enum ice_ptp_tmr_cmd cmd)
3527 {
3528 u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd);
3529 int err;
3530
3531 /* Tx case */
3532 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_TMR_CMD, val);
3533 if (err) {
3534 ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_TMR_CMD, err %d\n",
3535 err);
3536 return err;
3537 }
3538
3539 /* Rx case */
3540 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_TMR_CMD,
3541 val | TS_CMD_RX_TYPE);
3542 if (err) {
3543 ice_debug(hw, ICE_DBG_PTP, "Failed to write back RX_TMR_CMD, err %d\n",
3544 err);
3545 return err;
3546 }
3547
3548 return 0;
3549 }
3550
3551 /* E822 Vernier calibration functions
3552 *
3553 * The following functions are used as part of the vernier calibration of
3554 * a port. This calibration increases the precision of the timestamps on the
3555 * port.
3556 */
3557
3558 /**
3559 * ice_phy_get_speed_and_fec_e82x - Get link speed and FEC based on serdes mode
3560 * @hw: pointer to HW struct
3561 * @port: the port to read from
3562 * @link_out: if non-NULL, holds link speed on success
3563 * @fec_out: if non-NULL, holds FEC algorithm on success
3564 *
3565 * Read the serdes data for the PHY port and extract the link speed and FEC
3566 * algorithm.
3567 */
3568 static int
ice_phy_get_speed_and_fec_e82x(struct ice_hw * hw,u8 port,enum ice_ptp_link_spd * link_out,enum ice_ptp_fec_mode * fec_out)3569 ice_phy_get_speed_and_fec_e82x(struct ice_hw *hw, u8 port,
3570 enum ice_ptp_link_spd *link_out,
3571 enum ice_ptp_fec_mode *fec_out)
3572 {
3573 enum ice_ptp_link_spd link;
3574 enum ice_ptp_fec_mode fec;
3575 u32 serdes;
3576 int err;
3577
3578 err = ice_read_phy_reg_e82x(hw, port, P_REG_LINK_SPEED, &serdes);
3579 if (err) {
3580 ice_debug(hw, ICE_DBG_PTP, "Failed to read serdes info\n");
3581 return err;
3582 }
3583
3584 /* Determine the FEC algorithm */
3585 fec = (enum ice_ptp_fec_mode)P_REG_LINK_SPEED_FEC_MODE(serdes);
3586
3587 serdes &= P_REG_LINK_SPEED_SERDES_M;
3588
3589 /* Determine the link speed */
3590 if (fec == ICE_PTP_FEC_MODE_RS_FEC) {
3591 switch (serdes) {
3592 case ICE_PTP_SERDES_25G:
3593 link = ICE_PTP_LNK_SPD_25G_RS;
3594 break;
3595 case ICE_PTP_SERDES_50G:
3596 link = ICE_PTP_LNK_SPD_50G_RS;
3597 break;
3598 case ICE_PTP_SERDES_100G:
3599 link = ICE_PTP_LNK_SPD_100G_RS;
3600 break;
3601 default:
3602 return -EIO;
3603 }
3604 } else {
3605 switch (serdes) {
3606 case ICE_PTP_SERDES_1G:
3607 link = ICE_PTP_LNK_SPD_1G;
3608 break;
3609 case ICE_PTP_SERDES_10G:
3610 link = ICE_PTP_LNK_SPD_10G;
3611 break;
3612 case ICE_PTP_SERDES_25G:
3613 link = ICE_PTP_LNK_SPD_25G;
3614 break;
3615 case ICE_PTP_SERDES_40G:
3616 link = ICE_PTP_LNK_SPD_40G;
3617 break;
3618 case ICE_PTP_SERDES_50G:
3619 link = ICE_PTP_LNK_SPD_50G;
3620 break;
3621 default:
3622 return -EIO;
3623 }
3624 }
3625
3626 if (link_out)
3627 *link_out = link;
3628 if (fec_out)
3629 *fec_out = fec;
3630
3631 return 0;
3632 }
3633
3634 /**
3635 * ice_phy_cfg_lane_e82x - Configure PHY quad for single/multi-lane timestamp
3636 * @hw: pointer to HW struct
3637 * @port: to configure the quad for
3638 */
ice_phy_cfg_lane_e82x(struct ice_hw * hw,u8 port)3639 static void ice_phy_cfg_lane_e82x(struct ice_hw *hw, u8 port)
3640 {
3641 enum ice_ptp_link_spd link_spd;
3642 int err;
3643 u32 val;
3644 u8 quad;
3645
3646 err = ice_phy_get_speed_and_fec_e82x(hw, port, &link_spd, NULL);
3647 if (err) {
3648 ice_debug(hw, ICE_DBG_PTP, "Failed to get PHY link speed, err %d\n",
3649 err);
3650 return;
3651 }
3652
3653 quad = ICE_GET_QUAD_NUM(port);
3654
3655 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, &val);
3656 if (err) {
3657 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEM_GLB_CFG, err %d\n",
3658 err);
3659 return;
3660 }
3661
3662 if (link_spd >= ICE_PTP_LNK_SPD_40G)
3663 val &= ~Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M;
3664 else
3665 val |= Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M;
3666
3667 err = ice_write_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, val);
3668 if (err) {
3669 ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_MEM_GBL_CFG, err %d\n",
3670 err);
3671 return;
3672 }
3673 }
3674
3675 /**
3676 * ice_phy_cfg_uix_e82x - Configure Serdes UI to TU conversion for E822
3677 * @hw: pointer to the HW structure
3678 * @port: the port to configure
3679 *
3680 * Program the conversion ration of Serdes clock "unit intervals" (UIs) to PHC
3681 * hardware clock time units (TUs). That is, determine the number of TUs per
3682 * serdes unit interval, and program the UIX registers with this conversion.
3683 *
3684 * This conversion is used as part of the calibration process when determining
3685 * the additional error of a timestamp vs the real time of transmission or
3686 * receipt of the packet.
3687 *
3688 * Hardware uses the number of TUs per 66 UIs, written to the UIX registers
3689 * for the two main serdes clock rates, 10G/40G and 25G/100G serdes clocks.
3690 *
3691 * To calculate the conversion ratio, we use the following facts:
3692 *
3693 * a) the clock frequency in Hz (cycles per second)
3694 * b) the number of TUs per cycle (the increment value of the clock)
3695 * c) 1 second per 1 billion nanoseconds
3696 * d) the duration of 66 UIs in nanoseconds
3697 *
3698 * Given these facts, we can use the following table to work out what ratios
3699 * to multiply in order to get the number of TUs per 66 UIs:
3700 *
3701 * cycles | 1 second | incval (TUs) | nanoseconds
3702 * -------+--------------+--------------+-------------
3703 * second | 1 billion ns | cycle | 66 UIs
3704 *
3705 * To perform the multiplication using integers without too much loss of
3706 * precision, we can take use the following equation:
3707 *
3708 * (freq * incval * 6600 LINE_UI ) / ( 100 * 1 billion)
3709 *
3710 * We scale up to using 6600 UI instead of 66 in order to avoid fractional
3711 * nanosecond UIs (66 UI at 10G/40G is 6.4 ns)
3712 *
3713 * The increment value has a maximum expected range of about 34 bits, while
3714 * the frequency value is about 29 bits. Multiplying these values shouldn't
3715 * overflow the 64 bits. However, we must then further multiply them again by
3716 * the Serdes unit interval duration. To avoid overflow here, we split the
3717 * overall divide by 1e11 into a divide by 256 (shift down by 8 bits) and
3718 * a divide by 390,625,000. This does lose some precision, but avoids
3719 * miscalculation due to arithmetic overflow.
3720 */
ice_phy_cfg_uix_e82x(struct ice_hw * hw,u8 port)3721 static int ice_phy_cfg_uix_e82x(struct ice_hw *hw, u8 port)
3722 {
3723 u64 cur_freq, clk_incval, tu_per_sec, uix;
3724 int err;
3725
3726 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw));
3727 clk_incval = ice_ptp_read_src_incval(hw);
3728
3729 /* Calculate TUs per second divided by 256 */
3730 tu_per_sec = (cur_freq * clk_incval) >> 8;
3731
3732 #define LINE_UI_10G_40G 640 /* 6600 UIs is 640 nanoseconds at 10Gb/40Gb */
3733 #define LINE_UI_25G_100G 256 /* 6600 UIs is 256 nanoseconds at 25Gb/100Gb */
3734
3735 /* Program the 10Gb/40Gb conversion ratio */
3736 uix = div_u64(tu_per_sec * LINE_UI_10G_40G, 390625000);
3737
3738 err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_UIX66_10G_40G_L,
3739 uix);
3740 if (err) {
3741 ice_debug(hw, ICE_DBG_PTP, "Failed to write UIX66_10G_40G, err %d\n",
3742 err);
3743 return err;
3744 }
3745
3746 /* Program the 25Gb/100Gb conversion ratio */
3747 uix = div_u64(tu_per_sec * LINE_UI_25G_100G, 390625000);
3748
3749 err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_UIX66_25G_100G_L,
3750 uix);
3751 if (err) {
3752 ice_debug(hw, ICE_DBG_PTP, "Failed to write UIX66_25G_100G, err %d\n",
3753 err);
3754 return err;
3755 }
3756
3757 return 0;
3758 }
3759
3760 /**
3761 * ice_phy_cfg_parpcs_e82x - Configure TUs per PAR/PCS clock cycle
3762 * @hw: pointer to the HW struct
3763 * @port: port to configure
3764 *
3765 * Configure the number of TUs for the PAR and PCS clocks used as part of the
3766 * timestamp calibration process. This depends on the link speed, as the PHY
3767 * uses different markers depending on the speed.
3768 *
3769 * 1Gb/10Gb/25Gb:
3770 * - Tx/Rx PAR/PCS markers
3771 *
3772 * 25Gb RS:
3773 * - Tx/Rx Reed Solomon gearbox PAR/PCS markers
3774 *
3775 * 40Gb/50Gb:
3776 * - Tx/Rx PAR/PCS markers
3777 * - Rx Deskew PAR/PCS markers
3778 *
3779 * 50G RS and 100GB RS:
3780 * - Tx/Rx Reed Solomon gearbox PAR/PCS markers
3781 * - Rx Deskew PAR/PCS markers
3782 * - Tx PAR/PCS markers
3783 *
3784 * To calculate the conversion, we use the PHC clock frequency (cycles per
3785 * second), the increment value (TUs per cycle), and the related PHY clock
3786 * frequency to calculate the TUs per unit of the PHY link clock. The
3787 * following table shows how the units convert:
3788 *
3789 * cycles | TUs | second
3790 * -------+-------+--------
3791 * second | cycle | cycles
3792 *
3793 * For each conversion register, look up the appropriate frequency from the
3794 * e822 PAR/PCS table and calculate the TUs per unit of that clock. Program
3795 * this to the appropriate register, preparing hardware to perform timestamp
3796 * calibration to calculate the total Tx or Rx offset to adjust the timestamp
3797 * in order to calibrate for the internal PHY delays.
3798 *
3799 * Note that the increment value ranges up to ~34 bits, and the clock
3800 * frequency is ~29 bits, so multiplying them together should fit within the
3801 * 64 bit arithmetic.
3802 */
ice_phy_cfg_parpcs_e82x(struct ice_hw * hw,u8 port)3803 static int ice_phy_cfg_parpcs_e82x(struct ice_hw *hw, u8 port)
3804 {
3805 u64 cur_freq, clk_incval, tu_per_sec, phy_tus;
3806 enum ice_ptp_link_spd link_spd;
3807 enum ice_ptp_fec_mode fec_mode;
3808 int err;
3809
3810 err = ice_phy_get_speed_and_fec_e82x(hw, port, &link_spd, &fec_mode);
3811 if (err)
3812 return err;
3813
3814 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw));
3815 clk_incval = ice_ptp_read_src_incval(hw);
3816
3817 /* Calculate TUs per cycle of the PHC clock */
3818 tu_per_sec = cur_freq * clk_incval;
3819
3820 /* For each PHY conversion register, look up the appropriate link
3821 * speed frequency and determine the TUs per that clock's cycle time.
3822 * Split this into a high and low value and then program the
3823 * appropriate register. If that link speed does not use the
3824 * associated register, write zeros to clear it instead.
3825 */
3826
3827 /* P_REG_PAR_TX_TUS */
3828 if (e822_vernier[link_spd].tx_par_clk)
3829 phy_tus = div_u64(tu_per_sec,
3830 e822_vernier[link_spd].tx_par_clk);
3831 else
3832 phy_tus = 0;
3833
3834 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PAR_TX_TUS_L,
3835 phy_tus);
3836 if (err)
3837 return err;
3838
3839 /* P_REG_PAR_RX_TUS */
3840 if (e822_vernier[link_spd].rx_par_clk)
3841 phy_tus = div_u64(tu_per_sec,
3842 e822_vernier[link_spd].rx_par_clk);
3843 else
3844 phy_tus = 0;
3845
3846 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PAR_RX_TUS_L,
3847 phy_tus);
3848 if (err)
3849 return err;
3850
3851 /* P_REG_PCS_TX_TUS */
3852 if (e822_vernier[link_spd].tx_pcs_clk)
3853 phy_tus = div_u64(tu_per_sec,
3854 e822_vernier[link_spd].tx_pcs_clk);
3855 else
3856 phy_tus = 0;
3857
3858 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PCS_TX_TUS_L,
3859 phy_tus);
3860 if (err)
3861 return err;
3862
3863 /* P_REG_PCS_RX_TUS */
3864 if (e822_vernier[link_spd].rx_pcs_clk)
3865 phy_tus = div_u64(tu_per_sec,
3866 e822_vernier[link_spd].rx_pcs_clk);
3867 else
3868 phy_tus = 0;
3869
3870 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PCS_RX_TUS_L,
3871 phy_tus);
3872 if (err)
3873 return err;
3874
3875 /* P_REG_DESK_PAR_TX_TUS */
3876 if (e822_vernier[link_spd].tx_desk_rsgb_par)
3877 phy_tus = div_u64(tu_per_sec,
3878 e822_vernier[link_spd].tx_desk_rsgb_par);
3879 else
3880 phy_tus = 0;
3881
3882 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_DESK_PAR_TX_TUS_L,
3883 phy_tus);
3884 if (err)
3885 return err;
3886
3887 /* P_REG_DESK_PAR_RX_TUS */
3888 if (e822_vernier[link_spd].rx_desk_rsgb_par)
3889 phy_tus = div_u64(tu_per_sec,
3890 e822_vernier[link_spd].rx_desk_rsgb_par);
3891 else
3892 phy_tus = 0;
3893
3894 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_DESK_PAR_RX_TUS_L,
3895 phy_tus);
3896 if (err)
3897 return err;
3898
3899 /* P_REG_DESK_PCS_TX_TUS */
3900 if (e822_vernier[link_spd].tx_desk_rsgb_pcs)
3901 phy_tus = div_u64(tu_per_sec,
3902 e822_vernier[link_spd].tx_desk_rsgb_pcs);
3903 else
3904 phy_tus = 0;
3905
3906 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_DESK_PCS_TX_TUS_L,
3907 phy_tus);
3908 if (err)
3909 return err;
3910
3911 /* P_REG_DESK_PCS_RX_TUS */
3912 if (e822_vernier[link_spd].rx_desk_rsgb_pcs)
3913 phy_tus = div_u64(tu_per_sec,
3914 e822_vernier[link_spd].rx_desk_rsgb_pcs);
3915 else
3916 phy_tus = 0;
3917
3918 return ice_write_40b_phy_reg_e82x(hw, port, P_REG_DESK_PCS_RX_TUS_L,
3919 phy_tus);
3920 }
3921
3922 /**
3923 * ice_calc_fixed_tx_offset_e82x - Calculated Fixed Tx offset for a port
3924 * @hw: pointer to the HW struct
3925 * @link_spd: the Link speed to calculate for
3926 *
3927 * Calculate the fixed offset due to known static latency data.
3928 */
3929 static u64
ice_calc_fixed_tx_offset_e82x(struct ice_hw * hw,enum ice_ptp_link_spd link_spd)3930 ice_calc_fixed_tx_offset_e82x(struct ice_hw *hw, enum ice_ptp_link_spd link_spd)
3931 {
3932 u64 cur_freq, clk_incval, tu_per_sec, fixed_offset;
3933
3934 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw));
3935 clk_incval = ice_ptp_read_src_incval(hw);
3936
3937 /* Calculate TUs per second */
3938 tu_per_sec = cur_freq * clk_incval;
3939
3940 /* Calculate number of TUs to add for the fixed Tx latency. Since the
3941 * latency measurement is in 1/100th of a nanosecond, we need to
3942 * multiply by tu_per_sec and then divide by 1e11. This calculation
3943 * overflows 64 bit integer arithmetic, so break it up into two
3944 * divisions by 1e4 first then by 1e7.
3945 */
3946 fixed_offset = div_u64(tu_per_sec, 10000);
3947 fixed_offset *= e822_vernier[link_spd].tx_fixed_delay;
3948 fixed_offset = div_u64(fixed_offset, 10000000);
3949
3950 return fixed_offset;
3951 }
3952
3953 /**
3954 * ice_phy_cfg_tx_offset_e82x - Configure total Tx timestamp offset
3955 * @hw: pointer to the HW struct
3956 * @port: the PHY port to configure
3957 *
3958 * Program the P_REG_TOTAL_TX_OFFSET register with the total number of TUs to
3959 * adjust Tx timestamps by. This is calculated by combining some known static
3960 * latency along with the Vernier offset computations done by hardware.
3961 *
3962 * This function will not return successfully until the Tx offset calculations
3963 * have been completed, which requires waiting until at least one packet has
3964 * been transmitted by the device. It is safe to call this function
3965 * periodically until calibration succeeds, as it will only program the offset
3966 * once.
3967 *
3968 * To avoid overflow, when calculating the offset based on the known static
3969 * latency values, we use measurements in 1/100th of a nanosecond, and divide
3970 * the TUs per second up front. This avoids overflow while allowing
3971 * calculation of the adjustment using integer arithmetic.
3972 *
3973 * Returns zero on success, -EBUSY if the hardware vernier offset
3974 * calibration has not completed, or another error code on failure.
3975 */
ice_phy_cfg_tx_offset_e82x(struct ice_hw * hw,u8 port)3976 int ice_phy_cfg_tx_offset_e82x(struct ice_hw *hw, u8 port)
3977 {
3978 enum ice_ptp_link_spd link_spd;
3979 enum ice_ptp_fec_mode fec_mode;
3980 u64 total_offset, val;
3981 int err;
3982 u32 reg;
3983
3984 /* Nothing to do if we've already programmed the offset */
3985 err = ice_read_phy_reg_e82x(hw, port, P_REG_TX_OR, ®);
3986 if (err) {
3987 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_OR for port %u, err %d\n",
3988 port, err);
3989 return err;
3990 }
3991
3992 if (reg)
3993 return 0;
3994
3995 err = ice_read_phy_reg_e82x(hw, port, P_REG_TX_OV_STATUS, ®);
3996 if (err) {
3997 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_OV_STATUS for port %u, err %d\n",
3998 port, err);
3999 return err;
4000 }
4001
4002 if (!(reg & P_REG_TX_OV_STATUS_OV_M))
4003 return -EBUSY;
4004
4005 err = ice_phy_get_speed_and_fec_e82x(hw, port, &link_spd, &fec_mode);
4006 if (err)
4007 return err;
4008
4009 total_offset = ice_calc_fixed_tx_offset_e82x(hw, link_spd);
4010
4011 /* Read the first Vernier offset from the PHY register and add it to
4012 * the total offset.
4013 */
4014 if (link_spd == ICE_PTP_LNK_SPD_1G ||
4015 link_spd == ICE_PTP_LNK_SPD_10G ||
4016 link_spd == ICE_PTP_LNK_SPD_25G ||
4017 link_spd == ICE_PTP_LNK_SPD_25G_RS ||
4018 link_spd == ICE_PTP_LNK_SPD_40G ||
4019 link_spd == ICE_PTP_LNK_SPD_50G) {
4020 err = ice_read_64b_phy_reg_e82x(hw, port,
4021 P_REG_PAR_PCS_TX_OFFSET_L,
4022 &val);
4023 if (err)
4024 return err;
4025
4026 total_offset += val;
4027 }
4028
4029 /* For Tx, we only need to use the second Vernier offset for
4030 * multi-lane link speeds with RS-FEC. The lanes will always be
4031 * aligned.
4032 */
4033 if (link_spd == ICE_PTP_LNK_SPD_50G_RS ||
4034 link_spd == ICE_PTP_LNK_SPD_100G_RS) {
4035 err = ice_read_64b_phy_reg_e82x(hw, port,
4036 P_REG_PAR_TX_TIME_L,
4037 &val);
4038 if (err)
4039 return err;
4040
4041 total_offset += val;
4042 }
4043
4044 /* Now that the total offset has been calculated, program it to the
4045 * PHY and indicate that the Tx offset is ready. After this,
4046 * timestamps will be enabled.
4047 */
4048 err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_TOTAL_TX_OFFSET_L,
4049 total_offset);
4050 if (err)
4051 return err;
4052
4053 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_OR, 1);
4054 if (err)
4055 return err;
4056
4057 dev_info(ice_hw_to_dev(hw), "Port=%d Tx vernier offset calibration complete\n",
4058 port);
4059
4060 return 0;
4061 }
4062
4063 /**
4064 * ice_phy_calc_pmd_adj_e82x - Calculate PMD adjustment for Rx
4065 * @hw: pointer to the HW struct
4066 * @port: the PHY port to adjust for
4067 * @link_spd: the current link speed of the PHY
4068 * @fec_mode: the current FEC mode of the PHY
4069 * @pmd_adj: on return, the amount to adjust the Rx total offset by
4070 *
4071 * Calculates the adjustment to Rx timestamps due to PMD alignment in the PHY.
4072 * This varies by link speed and FEC mode. The value calculated accounts for
4073 * various delays caused when receiving a packet.
4074 */
4075 static int
ice_phy_calc_pmd_adj_e82x(struct ice_hw * hw,u8 port,enum ice_ptp_link_spd link_spd,enum ice_ptp_fec_mode fec_mode,u64 * pmd_adj)4076 ice_phy_calc_pmd_adj_e82x(struct ice_hw *hw, u8 port,
4077 enum ice_ptp_link_spd link_spd,
4078 enum ice_ptp_fec_mode fec_mode, u64 *pmd_adj)
4079 {
4080 u64 cur_freq, clk_incval, tu_per_sec, mult, adj;
4081 u8 pmd_align;
4082 u32 val;
4083 int err;
4084
4085 err = ice_read_phy_reg_e82x(hw, port, P_REG_PMD_ALIGNMENT, &val);
4086 if (err) {
4087 ice_debug(hw, ICE_DBG_PTP, "Failed to read PMD alignment, err %d\n",
4088 err);
4089 return err;
4090 }
4091
4092 pmd_align = (u8)val;
4093
4094 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw));
4095 clk_incval = ice_ptp_read_src_incval(hw);
4096
4097 /* Calculate TUs per second */
4098 tu_per_sec = cur_freq * clk_incval;
4099
4100 /* The PMD alignment adjustment measurement depends on the link speed,
4101 * and whether FEC is enabled. For each link speed, the alignment
4102 * adjustment is calculated by dividing a value by the length of
4103 * a Time Unit in nanoseconds.
4104 *
4105 * 1G: align == 4 ? 10 * 0.8 : (align + 6 % 10) * 0.8
4106 * 10G: align == 65 ? 0 : (align * 0.1 * 32/33)
4107 * 10G w/FEC: align * 0.1 * 32/33
4108 * 25G: align == 65 ? 0 : (align * 0.4 * 32/33)
4109 * 25G w/FEC: align * 0.4 * 32/33
4110 * 40G: align == 65 ? 0 : (align * 0.1 * 32/33)
4111 * 40G w/FEC: align * 0.1 * 32/33
4112 * 50G: align == 65 ? 0 : (align * 0.4 * 32/33)
4113 * 50G w/FEC: align * 0.8 * 32/33
4114 *
4115 * For RS-FEC, if align is < 17 then we must also add 1.6 * 32/33.
4116 *
4117 * To allow for calculating this value using integer arithmetic, we
4118 * instead start with the number of TUs per second, (inverse of the
4119 * length of a Time Unit in nanoseconds), multiply by a value based
4120 * on the PMD alignment register, and then divide by the right value
4121 * calculated based on the table above. To avoid integer overflow this
4122 * division is broken up into a step of dividing by 125 first.
4123 */
4124 if (link_spd == ICE_PTP_LNK_SPD_1G) {
4125 if (pmd_align == 4)
4126 mult = 10;
4127 else
4128 mult = (pmd_align + 6) % 10;
4129 } else if (link_spd == ICE_PTP_LNK_SPD_10G ||
4130 link_spd == ICE_PTP_LNK_SPD_25G ||
4131 link_spd == ICE_PTP_LNK_SPD_40G ||
4132 link_spd == ICE_PTP_LNK_SPD_50G) {
4133 /* If Clause 74 FEC, always calculate PMD adjust */
4134 if (pmd_align != 65 || fec_mode == ICE_PTP_FEC_MODE_CLAUSE74)
4135 mult = pmd_align;
4136 else
4137 mult = 0;
4138 } else if (link_spd == ICE_PTP_LNK_SPD_25G_RS ||
4139 link_spd == ICE_PTP_LNK_SPD_50G_RS ||
4140 link_spd == ICE_PTP_LNK_SPD_100G_RS) {
4141 if (pmd_align < 17)
4142 mult = pmd_align + 40;
4143 else
4144 mult = pmd_align;
4145 } else {
4146 ice_debug(hw, ICE_DBG_PTP, "Unknown link speed %d, skipping PMD adjustment\n",
4147 link_spd);
4148 mult = 0;
4149 }
4150
4151 /* In some cases, there's no need to adjust for the PMD alignment */
4152 if (!mult) {
4153 *pmd_adj = 0;
4154 return 0;
4155 }
4156
4157 /* Calculate the adjustment by multiplying TUs per second by the
4158 * appropriate multiplier and divisor. To avoid overflow, we first
4159 * divide by 125, and then handle remaining divisor based on the link
4160 * speed pmd_adj_divisor value.
4161 */
4162 adj = div_u64(tu_per_sec, 125);
4163 adj *= mult;
4164 adj = div_u64(adj, e822_vernier[link_spd].pmd_adj_divisor);
4165
4166 /* Finally, for 25G-RS and 50G-RS, a further adjustment for the Rx
4167 * cycle count is necessary.
4168 */
4169 if (link_spd == ICE_PTP_LNK_SPD_25G_RS) {
4170 u64 cycle_adj;
4171 u8 rx_cycle;
4172
4173 err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_40_TO_160_CNT,
4174 &val);
4175 if (err) {
4176 ice_debug(hw, ICE_DBG_PTP, "Failed to read 25G-RS Rx cycle count, err %d\n",
4177 err);
4178 return err;
4179 }
4180
4181 rx_cycle = val & P_REG_RX_40_TO_160_CNT_RXCYC_M;
4182 if (rx_cycle) {
4183 mult = (4 - rx_cycle) * 40;
4184
4185 cycle_adj = div_u64(tu_per_sec, 125);
4186 cycle_adj *= mult;
4187 cycle_adj = div_u64(cycle_adj, e822_vernier[link_spd].pmd_adj_divisor);
4188
4189 adj += cycle_adj;
4190 }
4191 } else if (link_spd == ICE_PTP_LNK_SPD_50G_RS) {
4192 u64 cycle_adj;
4193 u8 rx_cycle;
4194
4195 err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_80_TO_160_CNT,
4196 &val);
4197 if (err) {
4198 ice_debug(hw, ICE_DBG_PTP, "Failed to read 50G-RS Rx cycle count, err %d\n",
4199 err);
4200 return err;
4201 }
4202
4203 rx_cycle = val & P_REG_RX_80_TO_160_CNT_RXCYC_M;
4204 if (rx_cycle) {
4205 mult = rx_cycle * 40;
4206
4207 cycle_adj = div_u64(tu_per_sec, 125);
4208 cycle_adj *= mult;
4209 cycle_adj = div_u64(cycle_adj, e822_vernier[link_spd].pmd_adj_divisor);
4210
4211 adj += cycle_adj;
4212 }
4213 }
4214
4215 /* Return the calculated adjustment */
4216 *pmd_adj = adj;
4217
4218 return 0;
4219 }
4220
4221 /**
4222 * ice_calc_fixed_rx_offset_e82x - Calculated the fixed Rx offset for a port
4223 * @hw: pointer to HW struct
4224 * @link_spd: The Link speed to calculate for
4225 *
4226 * Determine the fixed Rx latency for a given link speed.
4227 */
4228 static u64
ice_calc_fixed_rx_offset_e82x(struct ice_hw * hw,enum ice_ptp_link_spd link_spd)4229 ice_calc_fixed_rx_offset_e82x(struct ice_hw *hw, enum ice_ptp_link_spd link_spd)
4230 {
4231 u64 cur_freq, clk_incval, tu_per_sec, fixed_offset;
4232
4233 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw));
4234 clk_incval = ice_ptp_read_src_incval(hw);
4235
4236 /* Calculate TUs per second */
4237 tu_per_sec = cur_freq * clk_incval;
4238
4239 /* Calculate number of TUs to add for the fixed Rx latency. Since the
4240 * latency measurement is in 1/100th of a nanosecond, we need to
4241 * multiply by tu_per_sec and then divide by 1e11. This calculation
4242 * overflows 64 bit integer arithmetic, so break it up into two
4243 * divisions by 1e4 first then by 1e7.
4244 */
4245 fixed_offset = div_u64(tu_per_sec, 10000);
4246 fixed_offset *= e822_vernier[link_spd].rx_fixed_delay;
4247 fixed_offset = div_u64(fixed_offset, 10000000);
4248
4249 return fixed_offset;
4250 }
4251
4252 /**
4253 * ice_phy_cfg_rx_offset_e82x - Configure total Rx timestamp offset
4254 * @hw: pointer to the HW struct
4255 * @port: the PHY port to configure
4256 *
4257 * Program the P_REG_TOTAL_RX_OFFSET register with the number of Time Units to
4258 * adjust Rx timestamps by. This combines calculations from the Vernier offset
4259 * measurements taken in hardware with some data about known fixed delay as
4260 * well as adjusting for multi-lane alignment delay.
4261 *
4262 * This function will not return successfully until the Rx offset calculations
4263 * have been completed, which requires waiting until at least one packet has
4264 * been received by the device. It is safe to call this function periodically
4265 * until calibration succeeds, as it will only program the offset once.
4266 *
4267 * This function must be called only after the offset registers are valid,
4268 * i.e. after the Vernier calibration wait has passed, to ensure that the PHY
4269 * has measured the offset.
4270 *
4271 * To avoid overflow, when calculating the offset based on the known static
4272 * latency values, we use measurements in 1/100th of a nanosecond, and divide
4273 * the TUs per second up front. This avoids overflow while allowing
4274 * calculation of the adjustment using integer arithmetic.
4275 *
4276 * Returns zero on success, -EBUSY if the hardware vernier offset
4277 * calibration has not completed, or another error code on failure.
4278 */
ice_phy_cfg_rx_offset_e82x(struct ice_hw * hw,u8 port)4279 int ice_phy_cfg_rx_offset_e82x(struct ice_hw *hw, u8 port)
4280 {
4281 enum ice_ptp_link_spd link_spd;
4282 enum ice_ptp_fec_mode fec_mode;
4283 u64 total_offset, pmd, val;
4284 int err;
4285 u32 reg;
4286
4287 /* Nothing to do if we've already programmed the offset */
4288 err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_OR, ®);
4289 if (err) {
4290 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_OR for port %u, err %d\n",
4291 port, err);
4292 return err;
4293 }
4294
4295 if (reg)
4296 return 0;
4297
4298 err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_OV_STATUS, ®);
4299 if (err) {
4300 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_OV_STATUS for port %u, err %d\n",
4301 port, err);
4302 return err;
4303 }
4304
4305 if (!(reg & P_REG_RX_OV_STATUS_OV_M))
4306 return -EBUSY;
4307
4308 err = ice_phy_get_speed_and_fec_e82x(hw, port, &link_spd, &fec_mode);
4309 if (err)
4310 return err;
4311
4312 total_offset = ice_calc_fixed_rx_offset_e82x(hw, link_spd);
4313
4314 /* Read the first Vernier offset from the PHY register and add it to
4315 * the total offset.
4316 */
4317 err = ice_read_64b_phy_reg_e82x(hw, port,
4318 P_REG_PAR_PCS_RX_OFFSET_L,
4319 &val);
4320 if (err)
4321 return err;
4322
4323 total_offset += val;
4324
4325 /* For Rx, all multi-lane link speeds include a second Vernier
4326 * calibration, because the lanes might not be aligned.
4327 */
4328 if (link_spd == ICE_PTP_LNK_SPD_40G ||
4329 link_spd == ICE_PTP_LNK_SPD_50G ||
4330 link_spd == ICE_PTP_LNK_SPD_50G_RS ||
4331 link_spd == ICE_PTP_LNK_SPD_100G_RS) {
4332 err = ice_read_64b_phy_reg_e82x(hw, port,
4333 P_REG_PAR_RX_TIME_L,
4334 &val);
4335 if (err)
4336 return err;
4337
4338 total_offset += val;
4339 }
4340
4341 /* In addition, Rx must account for the PMD alignment */
4342 err = ice_phy_calc_pmd_adj_e82x(hw, port, link_spd, fec_mode, &pmd);
4343 if (err)
4344 return err;
4345
4346 /* For RS-FEC, this adjustment adds delay, but for other modes, it
4347 * subtracts delay.
4348 */
4349 if (fec_mode == ICE_PTP_FEC_MODE_RS_FEC)
4350 total_offset += pmd;
4351 else
4352 total_offset -= pmd;
4353
4354 /* Now that the total offset has been calculated, program it to the
4355 * PHY and indicate that the Rx offset is ready. After this,
4356 * timestamps will be enabled.
4357 */
4358 err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_TOTAL_RX_OFFSET_L,
4359 total_offset);
4360 if (err)
4361 return err;
4362
4363 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_OR, 1);
4364 if (err)
4365 return err;
4366
4367 dev_info(ice_hw_to_dev(hw), "Port=%d Rx vernier offset calibration complete\n",
4368 port);
4369
4370 return 0;
4371 }
4372
4373 /**
4374 * ice_ptp_clear_phy_offset_ready_e82x - Clear PHY TX_/RX_OFFSET_READY registers
4375 * @hw: pointer to the HW struct
4376 *
4377 * Clear PHY TX_/RX_OFFSET_READY registers, effectively marking all transmitted
4378 * and received timestamps as invalid.
4379 *
4380 * Return: 0 on success, other error codes when failed to write to PHY
4381 */
ice_ptp_clear_phy_offset_ready_e82x(struct ice_hw * hw)4382 int ice_ptp_clear_phy_offset_ready_e82x(struct ice_hw *hw)
4383 {
4384 u8 port;
4385
4386 for (port = 0; port < hw->ptp.num_lports; port++) {
4387 int err;
4388
4389 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_OR, 0);
4390 if (err) {
4391 dev_warn(ice_hw_to_dev(hw),
4392 "Failed to clear PHY TX_OFFSET_READY register\n");
4393 return err;
4394 }
4395
4396 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_OR, 0);
4397 if (err) {
4398 dev_warn(ice_hw_to_dev(hw),
4399 "Failed to clear PHY RX_OFFSET_READY register\n");
4400 return err;
4401 }
4402 }
4403
4404 return 0;
4405 }
4406
4407 /**
4408 * ice_read_phy_and_phc_time_e82x - Simultaneously capture PHC and PHY time
4409 * @hw: pointer to the HW struct
4410 * @port: the PHY port to read
4411 * @phy_time: on return, the 64bit PHY timer value
4412 * @phc_time: on return, the lower 64bits of PHC time
4413 *
4414 * Issue a ICE_PTP_READ_TIME timer command to simultaneously capture the PHY
4415 * and PHC timer values.
4416 */
4417 static int
ice_read_phy_and_phc_time_e82x(struct ice_hw * hw,u8 port,u64 * phy_time,u64 * phc_time)4418 ice_read_phy_and_phc_time_e82x(struct ice_hw *hw, u8 port, u64 *phy_time,
4419 u64 *phc_time)
4420 {
4421 u64 tx_time, rx_time;
4422 u32 zo, lo;
4423 u8 tmr_idx;
4424 int err;
4425
4426 tmr_idx = ice_get_ptp_src_clock_index(hw);
4427
4428 /* Prepare the PHC timer for a ICE_PTP_READ_TIME capture command */
4429 ice_ptp_src_cmd(hw, ICE_PTP_READ_TIME);
4430
4431 /* Prepare the PHY timer for a ICE_PTP_READ_TIME capture command */
4432 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_READ_TIME);
4433 if (err)
4434 return err;
4435
4436 /* Issue the sync to start the ICE_PTP_READ_TIME capture */
4437 ice_ptp_exec_tmr_cmd(hw);
4438
4439 /* Read the captured PHC time from the shadow time registers */
4440 zo = rd32(hw, GLTSYN_SHTIME_0(tmr_idx));
4441 lo = rd32(hw, GLTSYN_SHTIME_L(tmr_idx));
4442 *phc_time = (u64)lo << 32 | zo;
4443
4444 /* Read the captured PHY time from the PHY shadow registers */
4445 err = ice_ptp_read_port_capture(hw, port, &tx_time, &rx_time);
4446 if (err)
4447 return err;
4448
4449 /* If the PHY Tx and Rx timers don't match, log a warning message.
4450 * Note that this should not happen in normal circumstances since the
4451 * driver always programs them together.
4452 */
4453 if (tx_time != rx_time)
4454 dev_warn(ice_hw_to_dev(hw),
4455 "PHY port %u Tx and Rx timers do not match, tx_time 0x%016llX, rx_time 0x%016llX\n",
4456 port, (unsigned long long)tx_time,
4457 (unsigned long long)rx_time);
4458
4459 *phy_time = tx_time;
4460
4461 return 0;
4462 }
4463
4464 /**
4465 * ice_sync_phy_timer_e82x - Synchronize the PHY timer with PHC timer
4466 * @hw: pointer to the HW struct
4467 * @port: the PHY port to synchronize
4468 *
4469 * Perform an adjustment to ensure that the PHY and PHC timers are in sync.
4470 * This is done by issuing a ICE_PTP_READ_TIME command which triggers a
4471 * simultaneous read of the PHY timer and PHC timer. Then we use the
4472 * difference to calculate an appropriate 2s complement addition to add
4473 * to the PHY timer in order to ensure it reads the same value as the
4474 * primary PHC timer.
4475 */
ice_sync_phy_timer_e82x(struct ice_hw * hw,u8 port)4476 static int ice_sync_phy_timer_e82x(struct ice_hw *hw, u8 port)
4477 {
4478 u64 phc_time, phy_time, difference;
4479 int err;
4480
4481 if (!ice_ptp_lock(hw)) {
4482 ice_debug(hw, ICE_DBG_PTP, "Failed to acquire PTP semaphore\n");
4483 return -EBUSY;
4484 }
4485
4486 err = ice_read_phy_and_phc_time_e82x(hw, port, &phy_time, &phc_time);
4487 if (err)
4488 goto err_unlock;
4489
4490 /* Calculate the amount required to add to the port time in order for
4491 * it to match the PHC time.
4492 *
4493 * Note that the port adjustment is done using 2s complement
4494 * arithmetic. This is convenient since it means that we can simply
4495 * calculate the difference between the PHC time and the port time,
4496 * and it will be interpreted correctly.
4497 */
4498 difference = phc_time - phy_time;
4499
4500 err = ice_ptp_prep_port_adj_e82x(hw, port, (s64)difference);
4501 if (err)
4502 goto err_unlock;
4503
4504 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_ADJ_TIME);
4505 if (err)
4506 goto err_unlock;
4507
4508 /* Do not perform any action on the main timer */
4509 ice_ptp_src_cmd(hw, ICE_PTP_NOP);
4510
4511 /* Issue the sync to activate the time adjustment */
4512 ice_ptp_exec_tmr_cmd(hw);
4513
4514 /* Re-capture the timer values to flush the command registers and
4515 * verify that the time was properly adjusted.
4516 */
4517 err = ice_read_phy_and_phc_time_e82x(hw, port, &phy_time, &phc_time);
4518 if (err)
4519 goto err_unlock;
4520
4521 dev_info(ice_hw_to_dev(hw),
4522 "Port %u PHY time synced to PHC: 0x%016llX, 0x%016llX\n",
4523 port, (unsigned long long)phy_time,
4524 (unsigned long long)phc_time);
4525
4526 ice_ptp_unlock(hw);
4527
4528 return 0;
4529
4530 err_unlock:
4531 ice_ptp_unlock(hw);
4532 return err;
4533 }
4534
4535 /**
4536 * ice_stop_phy_timer_e82x - Stop the PHY clock timer
4537 * @hw: pointer to the HW struct
4538 * @port: the PHY port to stop
4539 * @soft_reset: if true, hold the SOFT_RESET bit of P_REG_PS
4540 *
4541 * Stop the clock of a PHY port. This must be done as part of the flow to
4542 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is
4543 * initialized or when link speed changes.
4544 */
4545 int
ice_stop_phy_timer_e82x(struct ice_hw * hw,u8 port,bool soft_reset)4546 ice_stop_phy_timer_e82x(struct ice_hw *hw, u8 port, bool soft_reset)
4547 {
4548 int err;
4549 u32 val;
4550
4551 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_OR, 0);
4552 if (err)
4553 return err;
4554
4555 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_OR, 0);
4556 if (err)
4557 return err;
4558
4559 err = ice_read_phy_reg_e82x(hw, port, P_REG_PS, &val);
4560 if (err)
4561 return err;
4562
4563 val &= ~P_REG_PS_START_M;
4564 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val);
4565 if (err)
4566 return err;
4567
4568 val &= ~P_REG_PS_ENA_CLK_M;
4569 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val);
4570 if (err)
4571 return err;
4572
4573 if (soft_reset) {
4574 val |= P_REG_PS_SFT_RESET_M;
4575 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val);
4576 if (err)
4577 return err;
4578 }
4579
4580 ice_debug(hw, ICE_DBG_PTP, "Disabled clock on PHY port %u\n", port);
4581
4582 return 0;
4583 }
4584
4585 /**
4586 * ice_start_phy_timer_e82x - Start the PHY clock timer
4587 * @hw: pointer to the HW struct
4588 * @port: the PHY port to start
4589 *
4590 * Start the clock of a PHY port. This must be done as part of the flow to
4591 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is
4592 * initialized or when link speed changes.
4593 *
4594 * Hardware will take Vernier measurements on Tx or Rx of packets.
4595 */
ice_start_phy_timer_e82x(struct ice_hw * hw,u8 port)4596 int ice_start_phy_timer_e82x(struct ice_hw *hw, u8 port)
4597 {
4598 u32 lo, hi, val;
4599 u64 incval;
4600 u8 tmr_idx;
4601 int err;
4602
4603 tmr_idx = ice_get_ptp_src_clock_index(hw);
4604
4605 err = ice_stop_phy_timer_e82x(hw, port, false);
4606 if (err)
4607 return err;
4608
4609 ice_phy_cfg_lane_e82x(hw, port);
4610
4611 err = ice_phy_cfg_uix_e82x(hw, port);
4612 if (err)
4613 return err;
4614
4615 err = ice_phy_cfg_parpcs_e82x(hw, port);
4616 if (err)
4617 return err;
4618
4619 lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx));
4620 hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx));
4621 incval = (u64)hi << 32 | lo;
4622
4623 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_TIMETUS_L, incval);
4624 if (err)
4625 return err;
4626
4627 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_INIT_INCVAL);
4628 if (err)
4629 return err;
4630
4631 /* Do not perform any action on the main timer */
4632 ice_ptp_src_cmd(hw, ICE_PTP_NOP);
4633
4634 ice_ptp_exec_tmr_cmd(hw);
4635
4636 err = ice_read_phy_reg_e82x(hw, port, P_REG_PS, &val);
4637 if (err)
4638 return err;
4639
4640 val |= P_REG_PS_SFT_RESET_M;
4641 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val);
4642 if (err)
4643 return err;
4644
4645 val |= P_REG_PS_START_M;
4646 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val);
4647 if (err)
4648 return err;
4649
4650 val &= ~P_REG_PS_SFT_RESET_M;
4651 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val);
4652 if (err)
4653 return err;
4654
4655 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_INIT_INCVAL);
4656 if (err)
4657 return err;
4658
4659 ice_ptp_exec_tmr_cmd(hw);
4660
4661 val |= P_REG_PS_ENA_CLK_M;
4662 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val);
4663 if (err)
4664 return err;
4665
4666 val |= P_REG_PS_LOAD_OFFSET_M;
4667 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val);
4668 if (err)
4669 return err;
4670
4671 ice_ptp_exec_tmr_cmd(hw);
4672
4673 err = ice_sync_phy_timer_e82x(hw, port);
4674 if (err)
4675 return err;
4676
4677 ice_debug(hw, ICE_DBG_PTP, "Enabled clock on PHY port %u\n", port);
4678
4679 return 0;
4680 }
4681
4682 /**
4683 * ice_get_phy_tx_tstamp_ready_e82x - Read Tx memory status register
4684 * @hw: pointer to the HW struct
4685 * @quad: the timestamp quad to read from
4686 * @tstamp_ready: contents of the Tx memory status register
4687 *
4688 * Read the Q_REG_TX_MEMORY_STATUS register indicating which timestamps in
4689 * the PHY are ready. A set bit means the corresponding timestamp is valid and
4690 * ready to be captured from the PHY timestamp block.
4691 */
4692 static int
ice_get_phy_tx_tstamp_ready_e82x(struct ice_hw * hw,u8 quad,u64 * tstamp_ready)4693 ice_get_phy_tx_tstamp_ready_e82x(struct ice_hw *hw, u8 quad, u64 *tstamp_ready)
4694 {
4695 u32 hi, lo;
4696 int err;
4697
4698 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEMORY_STATUS_U, &hi);
4699 if (err) {
4700 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS_U for quad %u, err %d\n",
4701 quad, err);
4702 return err;
4703 }
4704
4705 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEMORY_STATUS_L, &lo);
4706 if (err) {
4707 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS_L for quad %u, err %d\n",
4708 quad, err);
4709 return err;
4710 }
4711
4712 *tstamp_ready = (u64)hi << 32 | (u64)lo;
4713
4714 return 0;
4715 }
4716
4717 /**
4718 * ice_phy_cfg_intr_e82x - Configure TX timestamp interrupt
4719 * @hw: pointer to the HW struct
4720 * @quad: the timestamp quad
4721 * @ena: enable or disable interrupt
4722 * @threshold: interrupt threshold
4723 *
4724 * Configure TX timestamp interrupt for the specified quad
4725 *
4726 * Return: 0 on success, other error codes when failed to read/write quad
4727 */
4728
ice_phy_cfg_intr_e82x(struct ice_hw * hw,u8 quad,bool ena,u8 threshold)4729 int ice_phy_cfg_intr_e82x(struct ice_hw *hw, u8 quad, bool ena, u8 threshold)
4730 {
4731 int err;
4732 u32 val;
4733
4734 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, &val);
4735 if (err)
4736 return err;
4737
4738 val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M;
4739 if (ena) {
4740 val |= Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M;
4741 val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_THR_M;
4742 val |= FIELD_PREP(Q_REG_TX_MEM_GBL_CFG_INTR_THR_M, threshold);
4743 }
4744
4745 return ice_write_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, val);
4746 }
4747
4748 /**
4749 * ice_ptp_init_phy_e82x - initialize PHY parameters
4750 * @ptp: pointer to the PTP HW struct
4751 */
ice_ptp_init_phy_e82x(struct ice_ptp_hw * ptp)4752 static void ice_ptp_init_phy_e82x(struct ice_ptp_hw *ptp)
4753 {
4754 ptp->phy_model = ICE_PHY_E82X;
4755 ptp->num_lports = 8;
4756 ptp->ports_per_phy = 8;
4757 }
4758
4759 /* E810 functions
4760 *
4761 * The following functions operate on the E810 series devices which use
4762 * a separate external PHY.
4763 */
4764
4765 /**
4766 * ice_read_phy_reg_e810 - Read register from external PHY on E810
4767 * @hw: pointer to the HW struct
4768 * @addr: the address to read from
4769 * @val: On return, the value read from the PHY
4770 *
4771 * Read a register from the external PHY on the E810 device.
4772 */
ice_read_phy_reg_e810(struct ice_hw * hw,u32 addr,u32 * val)4773 static int ice_read_phy_reg_e810(struct ice_hw *hw, u32 addr, u32 *val)
4774 {
4775 struct ice_sbq_msg_input msg = {0};
4776 int err;
4777
4778 msg.msg_addr_low = lower_16_bits(addr);
4779 msg.msg_addr_high = upper_16_bits(addr);
4780 msg.opcode = ice_sbq_msg_rd;
4781 msg.dest_dev = rmn_0;
4782
4783 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD);
4784 if (err) {
4785 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n",
4786 err);
4787 return err;
4788 }
4789
4790 *val = msg.data;
4791
4792 return 0;
4793 }
4794
4795 /**
4796 * ice_write_phy_reg_e810 - Write register on external PHY on E810
4797 * @hw: pointer to the HW struct
4798 * @addr: the address to writem to
4799 * @val: the value to write to the PHY
4800 *
4801 * Write a value to a register of the external PHY on the E810 device.
4802 */
ice_write_phy_reg_e810(struct ice_hw * hw,u32 addr,u32 val)4803 static int ice_write_phy_reg_e810(struct ice_hw *hw, u32 addr, u32 val)
4804 {
4805 struct ice_sbq_msg_input msg = {0};
4806 int err;
4807
4808 msg.msg_addr_low = lower_16_bits(addr);
4809 msg.msg_addr_high = upper_16_bits(addr);
4810 msg.opcode = ice_sbq_msg_wr;
4811 msg.dest_dev = rmn_0;
4812 msg.data = val;
4813
4814 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD);
4815 if (err) {
4816 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n",
4817 err);
4818 return err;
4819 }
4820
4821 return 0;
4822 }
4823
4824 /**
4825 * ice_read_phy_tstamp_ll_e810 - Read a PHY timestamp registers through the FW
4826 * @hw: pointer to the HW struct
4827 * @idx: the timestamp index to read
4828 * @hi: 8 bit timestamp high value
4829 * @lo: 32 bit timestamp low value
4830 *
4831 * Read a 8bit timestamp high value and 32 bit timestamp low value out of the
4832 * timestamp block of the external PHY on the E810 device using the low latency
4833 * timestamp read.
4834 */
4835 static int
ice_read_phy_tstamp_ll_e810(struct ice_hw * hw,u8 idx,u8 * hi,u32 * lo)4836 ice_read_phy_tstamp_ll_e810(struct ice_hw *hw, u8 idx, u8 *hi, u32 *lo)
4837 {
4838 u32 val;
4839 u8 i;
4840
4841 /* Write TS index to read to the PF register so the FW can read it */
4842 val = FIELD_PREP(TS_LL_READ_TS_IDX, idx) | TS_LL_READ_TS;
4843 wr32(hw, PF_SB_ATQBAL, val);
4844
4845 /* Read the register repeatedly until the FW provides us the TS */
4846 for (i = TS_LL_READ_RETRIES; i > 0; i--) {
4847 val = rd32(hw, PF_SB_ATQBAL);
4848
4849 /* When the bit is cleared, the TS is ready in the register */
4850 if (!(FIELD_GET(TS_LL_READ_TS, val))) {
4851 /* High 8 bit value of the TS is on the bits 16:23 */
4852 *hi = FIELD_GET(TS_LL_READ_TS_HIGH, val);
4853
4854 /* Read the low 32 bit value and set the TS valid bit */
4855 *lo = rd32(hw, PF_SB_ATQBAH) | TS_VALID;
4856 return 0;
4857 }
4858
4859 udelay(10);
4860 }
4861
4862 /* FW failed to provide the TS in time */
4863 ice_debug(hw, ICE_DBG_PTP, "Failed to read PTP timestamp using low latency read\n");
4864 return -EINVAL;
4865 }
4866
4867 /**
4868 * ice_read_phy_tstamp_sbq_e810 - Read a PHY timestamp registers through the sbq
4869 * @hw: pointer to the HW struct
4870 * @lport: the lport to read from
4871 * @idx: the timestamp index to read
4872 * @hi: 8 bit timestamp high value
4873 * @lo: 32 bit timestamp low value
4874 *
4875 * Read a 8bit timestamp high value and 32 bit timestamp low value out of the
4876 * timestamp block of the external PHY on the E810 device using sideband queue.
4877 */
4878 static int
ice_read_phy_tstamp_sbq_e810(struct ice_hw * hw,u8 lport,u8 idx,u8 * hi,u32 * lo)4879 ice_read_phy_tstamp_sbq_e810(struct ice_hw *hw, u8 lport, u8 idx, u8 *hi,
4880 u32 *lo)
4881 {
4882 u32 hi_addr = TS_EXT(HIGH_TX_MEMORY_BANK_START, lport, idx);
4883 u32 lo_addr = TS_EXT(LOW_TX_MEMORY_BANK_START, lport, idx);
4884 u32 lo_val, hi_val;
4885 int err;
4886
4887 err = ice_read_phy_reg_e810(hw, lo_addr, &lo_val);
4888 if (err) {
4889 ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n",
4890 err);
4891 return err;
4892 }
4893
4894 err = ice_read_phy_reg_e810(hw, hi_addr, &hi_val);
4895 if (err) {
4896 ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n",
4897 err);
4898 return err;
4899 }
4900
4901 *lo = lo_val;
4902 *hi = (u8)hi_val;
4903
4904 return 0;
4905 }
4906
4907 /**
4908 * ice_read_phy_tstamp_e810 - Read a PHY timestamp out of the external PHY
4909 * @hw: pointer to the HW struct
4910 * @lport: the lport to read from
4911 * @idx: the timestamp index to read
4912 * @tstamp: on return, the 40bit timestamp value
4913 *
4914 * Read a 40bit timestamp value out of the timestamp block of the external PHY
4915 * on the E810 device.
4916 */
4917 static int
ice_read_phy_tstamp_e810(struct ice_hw * hw,u8 lport,u8 idx,u64 * tstamp)4918 ice_read_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx, u64 *tstamp)
4919 {
4920 u32 lo = 0;
4921 u8 hi = 0;
4922 int err;
4923
4924 if (hw->dev_caps.ts_dev_info.ts_ll_read)
4925 err = ice_read_phy_tstamp_ll_e810(hw, idx, &hi, &lo);
4926 else
4927 err = ice_read_phy_tstamp_sbq_e810(hw, lport, idx, &hi, &lo);
4928
4929 if (err)
4930 return err;
4931
4932 /* For E810 devices, the timestamp is reported with the lower 32 bits
4933 * in the low register, and the upper 8 bits in the high register.
4934 */
4935 *tstamp = ((u64)hi) << TS_HIGH_S | ((u64)lo & TS_LOW_M);
4936
4937 return 0;
4938 }
4939
4940 /**
4941 * ice_clear_phy_tstamp_e810 - Clear a timestamp from the external PHY
4942 * @hw: pointer to the HW struct
4943 * @lport: the lport to read from
4944 * @idx: the timestamp index to reset
4945 *
4946 * Read the timestamp and then forcibly overwrite its value to clear the valid
4947 * bit from the timestamp block of the external PHY on the E810 device.
4948 *
4949 * This function should only be called on an idx whose bit is set according to
4950 * ice_get_phy_tx_tstamp_ready().
4951 */
ice_clear_phy_tstamp_e810(struct ice_hw * hw,u8 lport,u8 idx)4952 static int ice_clear_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx)
4953 {
4954 u32 lo_addr, hi_addr;
4955 u64 unused_tstamp;
4956 int err;
4957
4958 err = ice_read_phy_tstamp_e810(hw, lport, idx, &unused_tstamp);
4959 if (err) {
4960 ice_debug(hw, ICE_DBG_PTP, "Failed to read the timestamp register for lport %u, idx %u, err %d\n",
4961 lport, idx, err);
4962 return err;
4963 }
4964
4965 lo_addr = TS_EXT(LOW_TX_MEMORY_BANK_START, lport, idx);
4966 hi_addr = TS_EXT(HIGH_TX_MEMORY_BANK_START, lport, idx);
4967
4968 err = ice_write_phy_reg_e810(hw, lo_addr, 0);
4969 if (err) {
4970 ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register for lport %u, idx %u, err %d\n",
4971 lport, idx, err);
4972 return err;
4973 }
4974
4975 err = ice_write_phy_reg_e810(hw, hi_addr, 0);
4976 if (err) {
4977 ice_debug(hw, ICE_DBG_PTP, "Failed to clear high PTP timestamp register for lport %u, idx %u, err %d\n",
4978 lport, idx, err);
4979 return err;
4980 }
4981
4982 return 0;
4983 }
4984
4985 /**
4986 * ice_ptp_init_phc_e810 - Perform E810 specific PHC initialization
4987 * @hw: pointer to HW struct
4988 *
4989 * Perform E810-specific PTP hardware clock initialization steps.
4990 *
4991 * Return: 0 on success, other error codes when failed to initialize TimeSync
4992 */
ice_ptp_init_phc_e810(struct ice_hw * hw)4993 static int ice_ptp_init_phc_e810(struct ice_hw *hw)
4994 {
4995 u8 tmr_idx;
4996 int err;
4997
4998 /* Ensure synchronization delay is zero */
4999 wr32(hw, GLTSYN_SYNC_DLAY, 0);
5000
5001 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
5002 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_ENA(tmr_idx),
5003 GLTSYN_ENA_TSYN_ENA_M);
5004 if (err)
5005 ice_debug(hw, ICE_DBG_PTP, "PTP failed in ena_phy_time_syn %d\n",
5006 err);
5007
5008 return err;
5009 }
5010
5011 /**
5012 * ice_ptp_prep_phy_time_e810 - Prepare PHY port with initial time
5013 * @hw: Board private structure
5014 * @time: Time to initialize the PHY port clock to
5015 *
5016 * Program the PHY port ETH_GLTSYN_SHTIME registers in preparation setting the
5017 * initial clock time. The time will not actually be programmed until the
5018 * driver issues an ICE_PTP_INIT_TIME command.
5019 *
5020 * The time value is the upper 32 bits of the PHY timer, usually in units of
5021 * nominal nanoseconds.
5022 */
ice_ptp_prep_phy_time_e810(struct ice_hw * hw,u32 time)5023 static int ice_ptp_prep_phy_time_e810(struct ice_hw *hw, u32 time)
5024 {
5025 u8 tmr_idx;
5026 int err;
5027
5028 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
5029 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_0(tmr_idx), 0);
5030 if (err) {
5031 ice_debug(hw, ICE_DBG_PTP, "Failed to write SHTIME_0, err %d\n",
5032 err);
5033 return err;
5034 }
5035
5036 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_L(tmr_idx), time);
5037 if (err) {
5038 ice_debug(hw, ICE_DBG_PTP, "Failed to write SHTIME_L, err %d\n",
5039 err);
5040 return err;
5041 }
5042
5043 return 0;
5044 }
5045
5046 /**
5047 * ice_ptp_prep_phy_adj_e810 - Prep PHY port for a time adjustment
5048 * @hw: pointer to HW struct
5049 * @adj: adjustment value to program
5050 *
5051 * Prepare the PHY port for an atomic adjustment by programming the PHY
5052 * ETH_GLTSYN_SHADJ_L and ETH_GLTSYN_SHADJ_H registers. The actual adjustment
5053 * is completed by issuing an ICE_PTP_ADJ_TIME sync command.
5054 *
5055 * The adjustment value only contains the portion used for the upper 32bits of
5056 * the PHY timer, usually in units of nominal nanoseconds. Negative
5057 * adjustments are supported using 2s complement arithmetic.
5058 */
ice_ptp_prep_phy_adj_e810(struct ice_hw * hw,s32 adj)5059 static int ice_ptp_prep_phy_adj_e810(struct ice_hw *hw, s32 adj)
5060 {
5061 u8 tmr_idx;
5062 int err;
5063
5064 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
5065
5066 /* Adjustments are represented as signed 2's complement values in
5067 * nanoseconds. Sub-nanosecond adjustment is not supported.
5068 */
5069 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_L(tmr_idx), 0);
5070 if (err) {
5071 ice_debug(hw, ICE_DBG_PTP, "Failed to write adj to PHY SHADJ_L, err %d\n",
5072 err);
5073 return err;
5074 }
5075
5076 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_H(tmr_idx), adj);
5077 if (err) {
5078 ice_debug(hw, ICE_DBG_PTP, "Failed to write adj to PHY SHADJ_H, err %d\n",
5079 err);
5080 return err;
5081 }
5082
5083 return 0;
5084 }
5085
5086 /**
5087 * ice_ptp_prep_phy_incval_e810 - Prep PHY port increment value change
5088 * @hw: pointer to HW struct
5089 * @incval: The new 40bit increment value to prepare
5090 *
5091 * Prepare the PHY port for a new increment value by programming the PHY
5092 * ETH_GLTSYN_SHADJ_L and ETH_GLTSYN_SHADJ_H registers. The actual change is
5093 * completed by issuing an ICE_PTP_INIT_INCVAL command.
5094 */
ice_ptp_prep_phy_incval_e810(struct ice_hw * hw,u64 incval)5095 static int ice_ptp_prep_phy_incval_e810(struct ice_hw *hw, u64 incval)
5096 {
5097 u32 high, low;
5098 u8 tmr_idx;
5099 int err;
5100
5101 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
5102 low = lower_32_bits(incval);
5103 high = upper_32_bits(incval);
5104
5105 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_L(tmr_idx), low);
5106 if (err) {
5107 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval to PHY SHADJ_L, err %d\n",
5108 err);
5109 return err;
5110 }
5111
5112 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_H(tmr_idx), high);
5113 if (err) {
5114 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval PHY SHADJ_H, err %d\n",
5115 err);
5116 return err;
5117 }
5118
5119 return 0;
5120 }
5121
5122 /**
5123 * ice_ptp_port_cmd_e810 - Prepare all external PHYs for a timer command
5124 * @hw: pointer to HW struct
5125 * @cmd: Command to be sent to the port
5126 *
5127 * Prepare the external PHYs connected to this device for a timer sync
5128 * command.
5129 */
ice_ptp_port_cmd_e810(struct ice_hw * hw,enum ice_ptp_tmr_cmd cmd)5130 static int ice_ptp_port_cmd_e810(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd)
5131 {
5132 u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd);
5133
5134 return ice_write_phy_reg_e810(hw, E810_ETH_GLTSYN_CMD, val);
5135 }
5136
5137 /**
5138 * ice_get_phy_tx_tstamp_ready_e810 - Read Tx memory status register
5139 * @hw: pointer to the HW struct
5140 * @port: the PHY port to read
5141 * @tstamp_ready: contents of the Tx memory status register
5142 *
5143 * E810 devices do not use a Tx memory status register. Instead simply
5144 * indicate that all timestamps are currently ready.
5145 */
5146 static int
ice_get_phy_tx_tstamp_ready_e810(struct ice_hw * hw,u8 port,u64 * tstamp_ready)5147 ice_get_phy_tx_tstamp_ready_e810(struct ice_hw *hw, u8 port, u64 *tstamp_ready)
5148 {
5149 *tstamp_ready = 0xFFFFFFFFFFFFFFFF;
5150 return 0;
5151 }
5152
5153 /* E810T SMA functions
5154 *
5155 * The following functions operate specifically on E810T hardware and are used
5156 * to access the extended GPIOs available.
5157 */
5158
5159 /**
5160 * ice_get_pca9575_handle
5161 * @hw: pointer to the hw struct
5162 * @pca9575_handle: GPIO controller's handle
5163 *
5164 * Find and return the GPIO controller's handle in the netlist.
5165 * When found - the value will be cached in the hw structure and following calls
5166 * will return cached value
5167 */
5168 static int
ice_get_pca9575_handle(struct ice_hw * hw,u16 * pca9575_handle)5169 ice_get_pca9575_handle(struct ice_hw *hw, u16 *pca9575_handle)
5170 {
5171 struct ice_aqc_get_link_topo *cmd;
5172 struct ice_aq_desc desc;
5173 int status;
5174 u8 idx;
5175
5176 /* If handle was read previously return cached value */
5177 if (hw->io_expander_handle) {
5178 *pca9575_handle = hw->io_expander_handle;
5179 return 0;
5180 }
5181
5182 /* If handle was not detected read it from the netlist */
5183 cmd = &desc.params.get_link_topo;
5184 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo);
5185
5186 /* Set node type to GPIO controller */
5187 cmd->addr.topo_params.node_type_ctx =
5188 (ICE_AQC_LINK_TOPO_NODE_TYPE_M &
5189 ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL);
5190
5191 #define SW_PCA9575_SFP_TOPO_IDX 2
5192 #define SW_PCA9575_QSFP_TOPO_IDX 1
5193
5194 /* Check if the SW IO expander controlling SMA exists in the netlist. */
5195 if (hw->device_id == ICE_DEV_ID_E810C_SFP)
5196 idx = SW_PCA9575_SFP_TOPO_IDX;
5197 else if (hw->device_id == ICE_DEV_ID_E810C_QSFP)
5198 idx = SW_PCA9575_QSFP_TOPO_IDX;
5199 else
5200 return -EOPNOTSUPP;
5201
5202 cmd->addr.topo_params.index = idx;
5203
5204 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
5205 if (status)
5206 return -EOPNOTSUPP;
5207
5208 /* Verify if we found the right IO expander type */
5209 if (desc.params.get_link_topo.node_part_num !=
5210 ICE_AQC_GET_LINK_TOPO_NODE_NR_PCA9575)
5211 return -EOPNOTSUPP;
5212
5213 /* If present save the handle and return it */
5214 hw->io_expander_handle =
5215 le16_to_cpu(desc.params.get_link_topo.addr.handle);
5216 *pca9575_handle = hw->io_expander_handle;
5217
5218 return 0;
5219 }
5220
5221 /**
5222 * ice_read_sma_ctrl_e810t
5223 * @hw: pointer to the hw struct
5224 * @data: pointer to data to be read from the GPIO controller
5225 *
5226 * Read the SMA controller state. It is connected to pins 3-7 of Port 1 of the
5227 * PCA9575 expander, so only bits 3-7 in data are valid.
5228 */
ice_read_sma_ctrl_e810t(struct ice_hw * hw,u8 * data)5229 int ice_read_sma_ctrl_e810t(struct ice_hw *hw, u8 *data)
5230 {
5231 int status;
5232 u16 handle;
5233 u8 i;
5234
5235 status = ice_get_pca9575_handle(hw, &handle);
5236 if (status)
5237 return status;
5238
5239 *data = 0;
5240
5241 for (i = ICE_SMA_MIN_BIT_E810T; i <= ICE_SMA_MAX_BIT_E810T; i++) {
5242 bool pin;
5243
5244 status = ice_aq_get_gpio(hw, handle, i + ICE_PCA9575_P1_OFFSET,
5245 &pin, NULL);
5246 if (status)
5247 break;
5248 *data |= (u8)(!pin) << i;
5249 }
5250
5251 return status;
5252 }
5253
5254 /**
5255 * ice_write_sma_ctrl_e810t
5256 * @hw: pointer to the hw struct
5257 * @data: data to be written to the GPIO controller
5258 *
5259 * Write the data to the SMA controller. It is connected to pins 3-7 of Port 1
5260 * of the PCA9575 expander, so only bits 3-7 in data are valid.
5261 */
ice_write_sma_ctrl_e810t(struct ice_hw * hw,u8 data)5262 int ice_write_sma_ctrl_e810t(struct ice_hw *hw, u8 data)
5263 {
5264 int status;
5265 u16 handle;
5266 u8 i;
5267
5268 status = ice_get_pca9575_handle(hw, &handle);
5269 if (status)
5270 return status;
5271
5272 for (i = ICE_SMA_MIN_BIT_E810T; i <= ICE_SMA_MAX_BIT_E810T; i++) {
5273 bool pin;
5274
5275 pin = !(data & (1 << i));
5276 status = ice_aq_set_gpio(hw, handle, i + ICE_PCA9575_P1_OFFSET,
5277 pin, NULL);
5278 if (status)
5279 break;
5280 }
5281
5282 return status;
5283 }
5284
5285 /**
5286 * ice_read_pca9575_reg_e810t
5287 * @hw: pointer to the hw struct
5288 * @offset: GPIO controller register offset
5289 * @data: pointer to data to be read from the GPIO controller
5290 *
5291 * Read the register from the GPIO controller
5292 */
ice_read_pca9575_reg_e810t(struct ice_hw * hw,u8 offset,u8 * data)5293 int ice_read_pca9575_reg_e810t(struct ice_hw *hw, u8 offset, u8 *data)
5294 {
5295 struct ice_aqc_link_topo_addr link_topo;
5296 __le16 addr;
5297 u16 handle;
5298 int err;
5299
5300 memset(&link_topo, 0, sizeof(link_topo));
5301
5302 err = ice_get_pca9575_handle(hw, &handle);
5303 if (err)
5304 return err;
5305
5306 link_topo.handle = cpu_to_le16(handle);
5307 link_topo.topo_params.node_type_ctx =
5308 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M,
5309 ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED);
5310
5311 addr = cpu_to_le16((u16)offset);
5312
5313 return ice_aq_read_i2c(hw, link_topo, 0, addr, 1, data, NULL);
5314 }
5315
5316 /**
5317 * ice_ptp_init_phy_e810 - initialize PHY parameters
5318 * @ptp: pointer to the PTP HW struct
5319 */
ice_ptp_init_phy_e810(struct ice_ptp_hw * ptp)5320 static void ice_ptp_init_phy_e810(struct ice_ptp_hw *ptp)
5321 {
5322 ptp->phy_model = ICE_PHY_E810;
5323 ptp->num_lports = 8;
5324 ptp->ports_per_phy = 4;
5325 }
5326
5327 /* Device agnostic functions
5328 *
5329 * The following functions implement shared behavior common to both E822 and
5330 * E810 devices, possibly calling a device specific implementation where
5331 * necessary.
5332 */
5333
5334 /**
5335 * ice_ptp_lock - Acquire PTP global semaphore register lock
5336 * @hw: pointer to the HW struct
5337 *
5338 * Acquire the global PTP hardware semaphore lock. Returns true if the lock
5339 * was acquired, false otherwise.
5340 *
5341 * The PFTSYN_SEM register sets the busy bit on read, returning the previous
5342 * value. If software sees the busy bit cleared, this means that this function
5343 * acquired the lock (and the busy bit is now set). If software sees the busy
5344 * bit set, it means that another function acquired the lock.
5345 *
5346 * Software must clear the busy bit with a write to release the lock for other
5347 * functions when done.
5348 */
ice_ptp_lock(struct ice_hw * hw)5349 bool ice_ptp_lock(struct ice_hw *hw)
5350 {
5351 u32 hw_lock;
5352 int i;
5353
5354 #define MAX_TRIES 15
5355
5356 for (i = 0; i < MAX_TRIES; i++) {
5357 hw_lock = rd32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id));
5358 hw_lock = hw_lock & PFTSYN_SEM_BUSY_M;
5359 if (hw_lock) {
5360 /* Somebody is holding the lock */
5361 usleep_range(5000, 6000);
5362 continue;
5363 }
5364
5365 break;
5366 }
5367
5368 return !hw_lock;
5369 }
5370
5371 /**
5372 * ice_ptp_unlock - Release PTP global semaphore register lock
5373 * @hw: pointer to the HW struct
5374 *
5375 * Release the global PTP hardware semaphore lock. This is done by writing to
5376 * the PFTSYN_SEM register.
5377 */
ice_ptp_unlock(struct ice_hw * hw)5378 void ice_ptp_unlock(struct ice_hw *hw)
5379 {
5380 wr32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id), 0);
5381 }
5382
5383 /**
5384 * ice_ptp_init_hw - Initialize hw based on device type
5385 * @hw: pointer to the HW structure
5386 *
5387 * Determine the PHY model for the device, and initialize hw
5388 * for use by other functions.
5389 */
ice_ptp_init_hw(struct ice_hw * hw)5390 void ice_ptp_init_hw(struct ice_hw *hw)
5391 {
5392 struct ice_ptp_hw *ptp = &hw->ptp;
5393
5394 if (ice_is_e822(hw) || ice_is_e823(hw))
5395 ice_ptp_init_phy_e82x(ptp);
5396 else if (ice_is_e810(hw))
5397 ice_ptp_init_phy_e810(ptp);
5398 else if (ice_is_e825c(hw))
5399 ice_ptp_init_phy_e825c(hw);
5400 else
5401 ptp->phy_model = ICE_PHY_UNSUP;
5402 }
5403
5404 /**
5405 * ice_ptp_write_port_cmd - Prepare a single PHY port for a timer command
5406 * @hw: pointer to HW struct
5407 * @port: Port to which cmd has to be sent
5408 * @cmd: Command to be sent to the port
5409 *
5410 * Prepare one port for the upcoming timer sync command. Do not use this for
5411 * programming only a single port, instead use ice_ptp_one_port_cmd() to
5412 * ensure non-modified ports get properly initialized to ICE_PTP_NOP.
5413 *
5414 * Return:
5415 * * %0 - success
5416 * %-EBUSY - PHY type not supported
5417 * * %other - failed to write port command
5418 */
ice_ptp_write_port_cmd(struct ice_hw * hw,u8 port,enum ice_ptp_tmr_cmd cmd)5419 static int ice_ptp_write_port_cmd(struct ice_hw *hw, u8 port,
5420 enum ice_ptp_tmr_cmd cmd)
5421 {
5422 switch (hw->ptp.phy_model) {
5423 case ICE_PHY_ETH56G:
5424 return ice_ptp_write_port_cmd_eth56g(hw, port, cmd);
5425 case ICE_PHY_E82X:
5426 return ice_ptp_write_port_cmd_e82x(hw, port, cmd);
5427 default:
5428 return -EOPNOTSUPP;
5429 }
5430 }
5431
5432 /**
5433 * ice_ptp_one_port_cmd - Program one PHY port for a timer command
5434 * @hw: pointer to HW struct
5435 * @configured_port: the port that should execute the command
5436 * @configured_cmd: the command to be executed on the configured port
5437 *
5438 * Prepare one port for executing a timer command, while preparing all other
5439 * ports to ICE_PTP_NOP. This allows executing a command on a single port
5440 * while ensuring all other ports do not execute stale commands.
5441 *
5442 * Return:
5443 * * %0 - success
5444 * * %other - failed to write port command
5445 */
ice_ptp_one_port_cmd(struct ice_hw * hw,u8 configured_port,enum ice_ptp_tmr_cmd configured_cmd)5446 int ice_ptp_one_port_cmd(struct ice_hw *hw, u8 configured_port,
5447 enum ice_ptp_tmr_cmd configured_cmd)
5448 {
5449 u32 port;
5450
5451 for (port = 0; port < hw->ptp.num_lports; port++) {
5452 int err;
5453
5454 /* Program the configured port with the configured command,
5455 * program all other ports with ICE_PTP_NOP.
5456 */
5457 if (port == configured_port)
5458 err = ice_ptp_write_port_cmd(hw, port, configured_cmd);
5459 else
5460 err = ice_ptp_write_port_cmd(hw, port, ICE_PTP_NOP);
5461
5462 if (err)
5463 return err;
5464 }
5465
5466 return 0;
5467 }
5468
5469 /**
5470 * ice_ptp_port_cmd - Prepare PHY ports for a timer sync command
5471 * @hw: pointer to HW struct
5472 * @cmd: the timer command to setup
5473 *
5474 * Prepare all PHY ports on this device for the requested timer command. For
5475 * some families this can be done in one shot, but for other families each
5476 * port must be configured individually.
5477 *
5478 * Return:
5479 * * %0 - success
5480 * * %other - failed to write port command
5481 */
ice_ptp_port_cmd(struct ice_hw * hw,enum ice_ptp_tmr_cmd cmd)5482 static int ice_ptp_port_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd)
5483 {
5484 u32 port;
5485
5486 /* PHY models which can program all ports simultaneously */
5487 switch (hw->ptp.phy_model) {
5488 case ICE_PHY_E810:
5489 return ice_ptp_port_cmd_e810(hw, cmd);
5490 default:
5491 break;
5492 }
5493
5494 /* PHY models which require programming each port separately */
5495 for (port = 0; port < hw->ptp.num_lports; port++) {
5496 int err;
5497
5498 err = ice_ptp_write_port_cmd(hw, port, cmd);
5499 if (err)
5500 return err;
5501 }
5502
5503 return 0;
5504 }
5505
5506 /**
5507 * ice_ptp_tmr_cmd - Prepare and trigger a timer sync command
5508 * @hw: pointer to HW struct
5509 * @cmd: the command to issue
5510 *
5511 * Prepare the source timer and PHY timers and then trigger the requested
5512 * command. This causes the shadow registers previously written in preparation
5513 * for the command to be synchronously applied to both the source and PHY
5514 * timers.
5515 */
ice_ptp_tmr_cmd(struct ice_hw * hw,enum ice_ptp_tmr_cmd cmd)5516 static int ice_ptp_tmr_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd)
5517 {
5518 int err;
5519
5520 /* First, prepare the source timer */
5521 ice_ptp_src_cmd(hw, cmd);
5522
5523 /* Next, prepare the ports */
5524 err = ice_ptp_port_cmd(hw, cmd);
5525 if (err) {
5526 ice_debug(hw, ICE_DBG_PTP, "Failed to prepare PHY ports for timer command %u, err %d\n",
5527 cmd, err);
5528 return err;
5529 }
5530
5531 /* Write the sync command register to drive both source and PHY timer
5532 * commands synchronously
5533 */
5534 ice_ptp_exec_tmr_cmd(hw);
5535
5536 return 0;
5537 }
5538
5539 /**
5540 * ice_ptp_init_time - Initialize device time to provided value
5541 * @hw: pointer to HW struct
5542 * @time: 64bits of time (GLTSYN_TIME_L and GLTSYN_TIME_H)
5543 *
5544 * Initialize the device to the specified time provided. This requires a three
5545 * step process:
5546 *
5547 * 1) write the new init time to the source timer shadow registers
5548 * 2) write the new init time to the PHY timer shadow registers
5549 * 3) issue an init_time timer command to synchronously switch both the source
5550 * and port timers to the new init time value at the next clock cycle.
5551 */
ice_ptp_init_time(struct ice_hw * hw,u64 time)5552 int ice_ptp_init_time(struct ice_hw *hw, u64 time)
5553 {
5554 u8 tmr_idx;
5555 int err;
5556
5557 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
5558
5559 /* Source timers */
5560 wr32(hw, GLTSYN_SHTIME_L(tmr_idx), lower_32_bits(time));
5561 wr32(hw, GLTSYN_SHTIME_H(tmr_idx), upper_32_bits(time));
5562 wr32(hw, GLTSYN_SHTIME_0(tmr_idx), 0);
5563
5564 /* PHY timers */
5565 /* Fill Rx and Tx ports and send msg to PHY */
5566 switch (hw->ptp.phy_model) {
5567 case ICE_PHY_ETH56G:
5568 err = ice_ptp_prep_phy_time_eth56g(hw,
5569 (u32)(time & 0xFFFFFFFF));
5570 break;
5571 case ICE_PHY_E810:
5572 err = ice_ptp_prep_phy_time_e810(hw, time & 0xFFFFFFFF);
5573 break;
5574 case ICE_PHY_E82X:
5575 err = ice_ptp_prep_phy_time_e82x(hw, time & 0xFFFFFFFF);
5576 break;
5577 default:
5578 err = -EOPNOTSUPP;
5579 }
5580
5581 if (err)
5582 return err;
5583
5584 return ice_ptp_tmr_cmd(hw, ICE_PTP_INIT_TIME);
5585 }
5586
5587 /**
5588 * ice_ptp_write_incval - Program PHC with new increment value
5589 * @hw: pointer to HW struct
5590 * @incval: Source timer increment value per clock cycle
5591 *
5592 * Program the PHC with a new increment value. This requires a three-step
5593 * process:
5594 *
5595 * 1) Write the increment value to the source timer shadow registers
5596 * 2) Write the increment value to the PHY timer shadow registers
5597 * 3) Issue an ICE_PTP_INIT_INCVAL timer command to synchronously switch both
5598 * the source and port timers to the new increment value at the next clock
5599 * cycle.
5600 */
ice_ptp_write_incval(struct ice_hw * hw,u64 incval)5601 int ice_ptp_write_incval(struct ice_hw *hw, u64 incval)
5602 {
5603 u8 tmr_idx;
5604 int err;
5605
5606 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
5607
5608 /* Shadow Adjust */
5609 wr32(hw, GLTSYN_SHADJ_L(tmr_idx), lower_32_bits(incval));
5610 wr32(hw, GLTSYN_SHADJ_H(tmr_idx), upper_32_bits(incval));
5611
5612 switch (hw->ptp.phy_model) {
5613 case ICE_PHY_ETH56G:
5614 err = ice_ptp_prep_phy_incval_eth56g(hw, incval);
5615 break;
5616 case ICE_PHY_E810:
5617 err = ice_ptp_prep_phy_incval_e810(hw, incval);
5618 break;
5619 case ICE_PHY_E82X:
5620 err = ice_ptp_prep_phy_incval_e82x(hw, incval);
5621 break;
5622 default:
5623 err = -EOPNOTSUPP;
5624 }
5625
5626 if (err)
5627 return err;
5628
5629 return ice_ptp_tmr_cmd(hw, ICE_PTP_INIT_INCVAL);
5630 }
5631
5632 /**
5633 * ice_ptp_write_incval_locked - Program new incval while holding semaphore
5634 * @hw: pointer to HW struct
5635 * @incval: Source timer increment value per clock cycle
5636 *
5637 * Program a new PHC incval while holding the PTP semaphore.
5638 */
ice_ptp_write_incval_locked(struct ice_hw * hw,u64 incval)5639 int ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval)
5640 {
5641 int err;
5642
5643 if (!ice_ptp_lock(hw))
5644 return -EBUSY;
5645
5646 err = ice_ptp_write_incval(hw, incval);
5647
5648 ice_ptp_unlock(hw);
5649
5650 return err;
5651 }
5652
5653 /**
5654 * ice_ptp_adj_clock - Adjust PHC clock time atomically
5655 * @hw: pointer to HW struct
5656 * @adj: Adjustment in nanoseconds
5657 *
5658 * Perform an atomic adjustment of the PHC time by the specified number of
5659 * nanoseconds. This requires a three-step process:
5660 *
5661 * 1) Write the adjustment to the source timer shadow registers
5662 * 2) Write the adjustment to the PHY timer shadow registers
5663 * 3) Issue an ICE_PTP_ADJ_TIME timer command to synchronously apply the
5664 * adjustment to both the source and port timers at the next clock cycle.
5665 */
ice_ptp_adj_clock(struct ice_hw * hw,s32 adj)5666 int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj)
5667 {
5668 u8 tmr_idx;
5669 int err;
5670
5671 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
5672
5673 /* Write the desired clock adjustment into the GLTSYN_SHADJ register.
5674 * For an ICE_PTP_ADJ_TIME command, this set of registers represents
5675 * the value to add to the clock time. It supports subtraction by
5676 * interpreting the value as a 2's complement integer.
5677 */
5678 wr32(hw, GLTSYN_SHADJ_L(tmr_idx), 0);
5679 wr32(hw, GLTSYN_SHADJ_H(tmr_idx), adj);
5680
5681 switch (hw->ptp.phy_model) {
5682 case ICE_PHY_ETH56G:
5683 err = ice_ptp_prep_phy_adj_eth56g(hw, adj);
5684 break;
5685 case ICE_PHY_E810:
5686 err = ice_ptp_prep_phy_adj_e810(hw, adj);
5687 break;
5688 case ICE_PHY_E82X:
5689 err = ice_ptp_prep_phy_adj_e82x(hw, adj);
5690 break;
5691 default:
5692 err = -EOPNOTSUPP;
5693 }
5694
5695 if (err)
5696 return err;
5697
5698 return ice_ptp_tmr_cmd(hw, ICE_PTP_ADJ_TIME);
5699 }
5700
5701 /**
5702 * ice_read_phy_tstamp - Read a PHY timestamp from the timestamo block
5703 * @hw: pointer to the HW struct
5704 * @block: the block to read from
5705 * @idx: the timestamp index to read
5706 * @tstamp: on return, the 40bit timestamp value
5707 *
5708 * Read a 40bit timestamp value out of the timestamp block. For E822 devices,
5709 * the block is the quad to read from. For E810 devices, the block is the
5710 * logical port to read from.
5711 */
ice_read_phy_tstamp(struct ice_hw * hw,u8 block,u8 idx,u64 * tstamp)5712 int ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp)
5713 {
5714 switch (hw->ptp.phy_model) {
5715 case ICE_PHY_ETH56G:
5716 return ice_read_ptp_tstamp_eth56g(hw, block, idx, tstamp);
5717 case ICE_PHY_E810:
5718 return ice_read_phy_tstamp_e810(hw, block, idx, tstamp);
5719 case ICE_PHY_E82X:
5720 return ice_read_phy_tstamp_e82x(hw, block, idx, tstamp);
5721 default:
5722 return -EOPNOTSUPP;
5723 }
5724 }
5725
5726 /**
5727 * ice_clear_phy_tstamp - Clear a timestamp from the timestamp block
5728 * @hw: pointer to the HW struct
5729 * @block: the block to read from
5730 * @idx: the timestamp index to reset
5731 *
5732 * Clear a timestamp from the timestamp block, discarding its value without
5733 * returning it. This resets the memory status bit for the timestamp index
5734 * allowing it to be reused for another timestamp in the future.
5735 *
5736 * For E822 devices, the block number is the PHY quad to clear from. For E810
5737 * devices, the block number is the logical port to clear from.
5738 *
5739 * This function must only be called on a timestamp index whose valid bit is
5740 * set according to ice_get_phy_tx_tstamp_ready().
5741 */
ice_clear_phy_tstamp(struct ice_hw * hw,u8 block,u8 idx)5742 int ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx)
5743 {
5744 switch (hw->ptp.phy_model) {
5745 case ICE_PHY_ETH56G:
5746 return ice_clear_ptp_tstamp_eth56g(hw, block, idx);
5747 case ICE_PHY_E810:
5748 return ice_clear_phy_tstamp_e810(hw, block, idx);
5749 case ICE_PHY_E82X:
5750 return ice_clear_phy_tstamp_e82x(hw, block, idx);
5751 default:
5752 return -EOPNOTSUPP;
5753 }
5754 }
5755
5756 /**
5757 * ice_get_pf_c827_idx - find and return the C827 index for the current pf
5758 * @hw: pointer to the hw struct
5759 * @idx: index of the found C827 PHY
5760 * Return:
5761 * * 0 - success
5762 * * negative - failure
5763 */
ice_get_pf_c827_idx(struct ice_hw * hw,u8 * idx)5764 static int ice_get_pf_c827_idx(struct ice_hw *hw, u8 *idx)
5765 {
5766 struct ice_aqc_get_link_topo cmd;
5767 u8 node_part_number;
5768 u16 node_handle;
5769 int status;
5770 u8 ctx;
5771
5772 if (hw->mac_type != ICE_MAC_E810)
5773 return -ENODEV;
5774
5775 if (hw->device_id != ICE_DEV_ID_E810C_QSFP) {
5776 *idx = C827_0;
5777 return 0;
5778 }
5779
5780 memset(&cmd, 0, sizeof(cmd));
5781
5782 ctx = ICE_AQC_LINK_TOPO_NODE_TYPE_PHY << ICE_AQC_LINK_TOPO_NODE_TYPE_S;
5783 ctx |= ICE_AQC_LINK_TOPO_NODE_CTX_PORT << ICE_AQC_LINK_TOPO_NODE_CTX_S;
5784 cmd.addr.topo_params.node_type_ctx = ctx;
5785
5786 status = ice_aq_get_netlist_node(hw, &cmd, &node_part_number,
5787 &node_handle);
5788 if (status || node_part_number != ICE_AQC_GET_LINK_TOPO_NODE_NR_C827)
5789 return -ENOENT;
5790
5791 if (node_handle == E810C_QSFP_C827_0_HANDLE)
5792 *idx = C827_0;
5793 else if (node_handle == E810C_QSFP_C827_1_HANDLE)
5794 *idx = C827_1;
5795 else
5796 return -EIO;
5797
5798 return 0;
5799 }
5800
5801 /**
5802 * ice_ptp_reset_ts_memory - Reset timestamp memory for all blocks
5803 * @hw: pointer to the HW struct
5804 */
ice_ptp_reset_ts_memory(struct ice_hw * hw)5805 void ice_ptp_reset_ts_memory(struct ice_hw *hw)
5806 {
5807 switch (hw->ptp.phy_model) {
5808 case ICE_PHY_ETH56G:
5809 ice_ptp_reset_ts_memory_eth56g(hw);
5810 break;
5811 case ICE_PHY_E82X:
5812 ice_ptp_reset_ts_memory_e82x(hw);
5813 break;
5814 case ICE_PHY_E810:
5815 default:
5816 return;
5817 }
5818 }
5819
5820 /**
5821 * ice_ptp_init_phc - Initialize PTP hardware clock
5822 * @hw: pointer to the HW struct
5823 *
5824 * Perform the steps required to initialize the PTP hardware clock.
5825 */
ice_ptp_init_phc(struct ice_hw * hw)5826 int ice_ptp_init_phc(struct ice_hw *hw)
5827 {
5828 u8 src_idx = hw->func_caps.ts_func_info.tmr_index_owned;
5829
5830 /* Enable source clocks */
5831 wr32(hw, GLTSYN_ENA(src_idx), GLTSYN_ENA_TSYN_ENA_M);
5832
5833 /* Clear event err indications for auxiliary pins */
5834 (void)rd32(hw, GLTSYN_STAT(src_idx));
5835
5836 switch (hw->ptp.phy_model) {
5837 case ICE_PHY_ETH56G:
5838 return ice_ptp_init_phc_eth56g(hw);
5839 case ICE_PHY_E810:
5840 return ice_ptp_init_phc_e810(hw);
5841 case ICE_PHY_E82X:
5842 return ice_ptp_init_phc_e82x(hw);
5843 default:
5844 return -EOPNOTSUPP;
5845 }
5846 }
5847
5848 /**
5849 * ice_get_phy_tx_tstamp_ready - Read PHY Tx memory status indication
5850 * @hw: pointer to the HW struct
5851 * @block: the timestamp block to check
5852 * @tstamp_ready: storage for the PHY Tx memory status information
5853 *
5854 * Check the PHY for Tx timestamp memory status. This reports a 64 bit value
5855 * which indicates which timestamps in the block may be captured. A set bit
5856 * means the timestamp can be read. An unset bit means the timestamp is not
5857 * ready and software should avoid reading the register.
5858 */
ice_get_phy_tx_tstamp_ready(struct ice_hw * hw,u8 block,u64 * tstamp_ready)5859 int ice_get_phy_tx_tstamp_ready(struct ice_hw *hw, u8 block, u64 *tstamp_ready)
5860 {
5861 switch (hw->ptp.phy_model) {
5862 case ICE_PHY_ETH56G:
5863 return ice_get_phy_tx_tstamp_ready_eth56g(hw, block,
5864 tstamp_ready);
5865 case ICE_PHY_E810:
5866 return ice_get_phy_tx_tstamp_ready_e810(hw, block,
5867 tstamp_ready);
5868 case ICE_PHY_E82X:
5869 return ice_get_phy_tx_tstamp_ready_e82x(hw, block,
5870 tstamp_ready);
5871 break;
5872 default:
5873 return -EOPNOTSUPP;
5874 }
5875 }
5876
5877 /**
5878 * ice_cgu_get_pin_desc_e823 - get pin description array
5879 * @hw: pointer to the hw struct
5880 * @input: if request is done against input or output pin
5881 * @size: number of inputs/outputs
5882 *
5883 * Return: pointer to pin description array associated to given hw.
5884 */
5885 static const struct ice_cgu_pin_desc *
ice_cgu_get_pin_desc_e823(struct ice_hw * hw,bool input,int * size)5886 ice_cgu_get_pin_desc_e823(struct ice_hw *hw, bool input, int *size)
5887 {
5888 static const struct ice_cgu_pin_desc *t;
5889
5890 if (hw->cgu_part_number ==
5891 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032) {
5892 if (input) {
5893 t = ice_e823_zl_cgu_inputs;
5894 *size = ARRAY_SIZE(ice_e823_zl_cgu_inputs);
5895 } else {
5896 t = ice_e823_zl_cgu_outputs;
5897 *size = ARRAY_SIZE(ice_e823_zl_cgu_outputs);
5898 }
5899 } else if (hw->cgu_part_number ==
5900 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384) {
5901 if (input) {
5902 t = ice_e823_si_cgu_inputs;
5903 *size = ARRAY_SIZE(ice_e823_si_cgu_inputs);
5904 } else {
5905 t = ice_e823_si_cgu_outputs;
5906 *size = ARRAY_SIZE(ice_e823_si_cgu_outputs);
5907 }
5908 } else {
5909 t = NULL;
5910 *size = 0;
5911 }
5912
5913 return t;
5914 }
5915
5916 /**
5917 * ice_cgu_get_pin_desc - get pin description array
5918 * @hw: pointer to the hw struct
5919 * @input: if request is done against input or output pins
5920 * @size: size of array returned by function
5921 *
5922 * Return: pointer to pin description array associated to given hw.
5923 */
5924 static const struct ice_cgu_pin_desc *
ice_cgu_get_pin_desc(struct ice_hw * hw,bool input,int * size)5925 ice_cgu_get_pin_desc(struct ice_hw *hw, bool input, int *size)
5926 {
5927 const struct ice_cgu_pin_desc *t = NULL;
5928
5929 switch (hw->device_id) {
5930 case ICE_DEV_ID_E810C_SFP:
5931 if (input) {
5932 t = ice_e810t_sfp_cgu_inputs;
5933 *size = ARRAY_SIZE(ice_e810t_sfp_cgu_inputs);
5934 } else {
5935 t = ice_e810t_sfp_cgu_outputs;
5936 *size = ARRAY_SIZE(ice_e810t_sfp_cgu_outputs);
5937 }
5938 break;
5939 case ICE_DEV_ID_E810C_QSFP:
5940 if (input) {
5941 t = ice_e810t_qsfp_cgu_inputs;
5942 *size = ARRAY_SIZE(ice_e810t_qsfp_cgu_inputs);
5943 } else {
5944 t = ice_e810t_qsfp_cgu_outputs;
5945 *size = ARRAY_SIZE(ice_e810t_qsfp_cgu_outputs);
5946 }
5947 break;
5948 case ICE_DEV_ID_E823L_10G_BASE_T:
5949 case ICE_DEV_ID_E823L_1GBE:
5950 case ICE_DEV_ID_E823L_BACKPLANE:
5951 case ICE_DEV_ID_E823L_QSFP:
5952 case ICE_DEV_ID_E823L_SFP:
5953 case ICE_DEV_ID_E823C_10G_BASE_T:
5954 case ICE_DEV_ID_E823C_BACKPLANE:
5955 case ICE_DEV_ID_E823C_QSFP:
5956 case ICE_DEV_ID_E823C_SFP:
5957 case ICE_DEV_ID_E823C_SGMII:
5958 t = ice_cgu_get_pin_desc_e823(hw, input, size);
5959 break;
5960 default:
5961 break;
5962 }
5963
5964 return t;
5965 }
5966
5967 /**
5968 * ice_cgu_get_pin_type - get pin's type
5969 * @hw: pointer to the hw struct
5970 * @pin: pin index
5971 * @input: if request is done against input or output pin
5972 *
5973 * Return: type of a pin.
5974 */
ice_cgu_get_pin_type(struct ice_hw * hw,u8 pin,bool input)5975 enum dpll_pin_type ice_cgu_get_pin_type(struct ice_hw *hw, u8 pin, bool input)
5976 {
5977 const struct ice_cgu_pin_desc *t;
5978 int t_size;
5979
5980 t = ice_cgu_get_pin_desc(hw, input, &t_size);
5981
5982 if (!t)
5983 return 0;
5984
5985 if (pin >= t_size)
5986 return 0;
5987
5988 return t[pin].type;
5989 }
5990
5991 /**
5992 * ice_cgu_get_pin_freq_supp - get pin's supported frequency
5993 * @hw: pointer to the hw struct
5994 * @pin: pin index
5995 * @input: if request is done against input or output pin
5996 * @num: output number of supported frequencies
5997 *
5998 * Get frequency supported number and array of supported frequencies.
5999 *
6000 * Return: array of supported frequencies for given pin.
6001 */
6002 struct dpll_pin_frequency *
ice_cgu_get_pin_freq_supp(struct ice_hw * hw,u8 pin,bool input,u8 * num)6003 ice_cgu_get_pin_freq_supp(struct ice_hw *hw, u8 pin, bool input, u8 *num)
6004 {
6005 const struct ice_cgu_pin_desc *t;
6006 int t_size;
6007
6008 *num = 0;
6009 t = ice_cgu_get_pin_desc(hw, input, &t_size);
6010 if (!t)
6011 return NULL;
6012 if (pin >= t_size)
6013 return NULL;
6014 *num = t[pin].freq_supp_num;
6015
6016 return t[pin].freq_supp;
6017 }
6018
6019 /**
6020 * ice_cgu_get_pin_name - get pin's name
6021 * @hw: pointer to the hw struct
6022 * @pin: pin index
6023 * @input: if request is done against input or output pin
6024 *
6025 * Return:
6026 * * null terminated char array with name
6027 * * NULL in case of failure
6028 */
ice_cgu_get_pin_name(struct ice_hw * hw,u8 pin,bool input)6029 const char *ice_cgu_get_pin_name(struct ice_hw *hw, u8 pin, bool input)
6030 {
6031 const struct ice_cgu_pin_desc *t;
6032 int t_size;
6033
6034 t = ice_cgu_get_pin_desc(hw, input, &t_size);
6035
6036 if (!t)
6037 return NULL;
6038
6039 if (pin >= t_size)
6040 return NULL;
6041
6042 return t[pin].name;
6043 }
6044
6045 /**
6046 * ice_get_cgu_state - get the state of the DPLL
6047 * @hw: pointer to the hw struct
6048 * @dpll_idx: Index of internal DPLL unit
6049 * @last_dpll_state: last known state of DPLL
6050 * @pin: pointer to a buffer for returning currently active pin
6051 * @ref_state: reference clock state
6052 * @eec_mode: eec mode of the DPLL
6053 * @phase_offset: pointer to a buffer for returning phase offset
6054 * @dpll_state: state of the DPLL (output)
6055 *
6056 * This function will read the state of the DPLL(dpll_idx). Non-null
6057 * 'pin', 'ref_state', 'eec_mode' and 'phase_offset' parameters are used to
6058 * retrieve currently active pin, state, mode and phase_offset respectively.
6059 *
6060 * Return: state of the DPLL
6061 */
ice_get_cgu_state(struct ice_hw * hw,u8 dpll_idx,enum dpll_lock_status last_dpll_state,u8 * pin,u8 * ref_state,u8 * eec_mode,s64 * phase_offset,enum dpll_lock_status * dpll_state)6062 int ice_get_cgu_state(struct ice_hw *hw, u8 dpll_idx,
6063 enum dpll_lock_status last_dpll_state, u8 *pin,
6064 u8 *ref_state, u8 *eec_mode, s64 *phase_offset,
6065 enum dpll_lock_status *dpll_state)
6066 {
6067 u8 hw_ref_state, hw_dpll_state, hw_eec_mode, hw_config;
6068 s64 hw_phase_offset;
6069 int status;
6070
6071 status = ice_aq_get_cgu_dpll_status(hw, dpll_idx, &hw_ref_state,
6072 &hw_dpll_state, &hw_config,
6073 &hw_phase_offset, &hw_eec_mode);
6074 if (status)
6075 return status;
6076
6077 if (pin)
6078 /* current ref pin in dpll_state_refsel_status_X register */
6079 *pin = hw_config & ICE_AQC_GET_CGU_DPLL_CONFIG_CLK_REF_SEL;
6080 if (phase_offset)
6081 *phase_offset = hw_phase_offset;
6082 if (ref_state)
6083 *ref_state = hw_ref_state;
6084 if (eec_mode)
6085 *eec_mode = hw_eec_mode;
6086 if (!dpll_state)
6087 return 0;
6088
6089 /* According to ZL DPLL documentation, once state reach LOCKED_HO_ACQ
6090 * it would never return to FREERUN. This aligns to ITU-T G.781
6091 * Recommendation. We cannot report HOLDOVER as HO memory is cleared
6092 * while switching to another reference.
6093 * Only for situations where previous state was either: "LOCKED without
6094 * HO_ACQ" or "HOLDOVER" we actually back to FREERUN.
6095 */
6096 if (hw_dpll_state & ICE_AQC_GET_CGU_DPLL_STATUS_STATE_LOCK) {
6097 if (hw_dpll_state & ICE_AQC_GET_CGU_DPLL_STATUS_STATE_HO_READY)
6098 *dpll_state = DPLL_LOCK_STATUS_LOCKED_HO_ACQ;
6099 else
6100 *dpll_state = DPLL_LOCK_STATUS_LOCKED;
6101 } else if (last_dpll_state == DPLL_LOCK_STATUS_LOCKED_HO_ACQ ||
6102 last_dpll_state == DPLL_LOCK_STATUS_HOLDOVER) {
6103 *dpll_state = DPLL_LOCK_STATUS_HOLDOVER;
6104 } else {
6105 *dpll_state = DPLL_LOCK_STATUS_UNLOCKED;
6106 }
6107
6108 return 0;
6109 }
6110
6111 /**
6112 * ice_get_cgu_rclk_pin_info - get info on available recovered clock pins
6113 * @hw: pointer to the hw struct
6114 * @base_idx: returns index of first recovered clock pin on device
6115 * @pin_num: returns number of recovered clock pins available on device
6116 *
6117 * Based on hw provide caller info about recovery clock pins available on the
6118 * board.
6119 *
6120 * Return:
6121 * * 0 - success, information is valid
6122 * * negative - failure, information is not valid
6123 */
ice_get_cgu_rclk_pin_info(struct ice_hw * hw,u8 * base_idx,u8 * pin_num)6124 int ice_get_cgu_rclk_pin_info(struct ice_hw *hw, u8 *base_idx, u8 *pin_num)
6125 {
6126 u8 phy_idx;
6127 int ret;
6128
6129 switch (hw->device_id) {
6130 case ICE_DEV_ID_E810C_SFP:
6131 case ICE_DEV_ID_E810C_QSFP:
6132
6133 ret = ice_get_pf_c827_idx(hw, &phy_idx);
6134 if (ret)
6135 return ret;
6136 *base_idx = E810T_CGU_INPUT_C827(phy_idx, ICE_RCLKA_PIN);
6137 *pin_num = ICE_E810_RCLK_PINS_NUM;
6138 ret = 0;
6139 break;
6140 case ICE_DEV_ID_E823L_10G_BASE_T:
6141 case ICE_DEV_ID_E823L_1GBE:
6142 case ICE_DEV_ID_E823L_BACKPLANE:
6143 case ICE_DEV_ID_E823L_QSFP:
6144 case ICE_DEV_ID_E823L_SFP:
6145 case ICE_DEV_ID_E823C_10G_BASE_T:
6146 case ICE_DEV_ID_E823C_BACKPLANE:
6147 case ICE_DEV_ID_E823C_QSFP:
6148 case ICE_DEV_ID_E823C_SFP:
6149 case ICE_DEV_ID_E823C_SGMII:
6150 *pin_num = ICE_E82X_RCLK_PINS_NUM;
6151 ret = 0;
6152 if (hw->cgu_part_number ==
6153 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032)
6154 *base_idx = ZL_REF1P;
6155 else if (hw->cgu_part_number ==
6156 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384)
6157 *base_idx = SI_REF1P;
6158 else
6159 ret = -ENODEV;
6160
6161 break;
6162 default:
6163 ret = -ENODEV;
6164 break;
6165 }
6166
6167 return ret;
6168 }
6169
6170 /**
6171 * ice_cgu_get_output_pin_state_caps - get output pin state capabilities
6172 * @hw: pointer to the hw struct
6173 * @pin_id: id of a pin
6174 * @caps: capabilities to modify
6175 *
6176 * Return:
6177 * * 0 - success, state capabilities were modified
6178 * * negative - failure, capabilities were not modified
6179 */
ice_cgu_get_output_pin_state_caps(struct ice_hw * hw,u8 pin_id,unsigned long * caps)6180 int ice_cgu_get_output_pin_state_caps(struct ice_hw *hw, u8 pin_id,
6181 unsigned long *caps)
6182 {
6183 bool can_change = true;
6184
6185 switch (hw->device_id) {
6186 case ICE_DEV_ID_E810C_SFP:
6187 if (pin_id == ZL_OUT2 || pin_id == ZL_OUT3)
6188 can_change = false;
6189 break;
6190 case ICE_DEV_ID_E810C_QSFP:
6191 if (pin_id == ZL_OUT2 || pin_id == ZL_OUT3 || pin_id == ZL_OUT4)
6192 can_change = false;
6193 break;
6194 case ICE_DEV_ID_E823L_10G_BASE_T:
6195 case ICE_DEV_ID_E823L_1GBE:
6196 case ICE_DEV_ID_E823L_BACKPLANE:
6197 case ICE_DEV_ID_E823L_QSFP:
6198 case ICE_DEV_ID_E823L_SFP:
6199 case ICE_DEV_ID_E823C_10G_BASE_T:
6200 case ICE_DEV_ID_E823C_BACKPLANE:
6201 case ICE_DEV_ID_E823C_QSFP:
6202 case ICE_DEV_ID_E823C_SFP:
6203 case ICE_DEV_ID_E823C_SGMII:
6204 if (hw->cgu_part_number ==
6205 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032 &&
6206 pin_id == ZL_OUT2)
6207 can_change = false;
6208 else if (hw->cgu_part_number ==
6209 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384 &&
6210 pin_id == SI_OUT1)
6211 can_change = false;
6212 break;
6213 default:
6214 return -EINVAL;
6215 }
6216 if (can_change)
6217 *caps |= DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE;
6218 else
6219 *caps &= ~DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE;
6220
6221 return 0;
6222 }
6223