Lines Matching +full:quad +full:- +full:precision
11 ---------------
46 -------------
56 -------------
65 -------------------
67 HWCAPs are allocated as described in Power Architecture 64-Bit ELF V2 ABI
71 ---------------------------------
74 32-bit CPU
77 64-bit CPU (userspace may be running in 32-bit mode).
105 Embedded Floating Point single precision operations are available.
108 Embedded Floating Point double precision operations are available.
167 The processor supports architected PMU events in the range 0xE0-0xFF.
170 The processor supports true little-endian mode.
173 The processor supports "PowerPC Little-Endian", that uses address
174 munging to make storage access appear to be little-endian, but the
179 ----------------------------------
206 Documentation/arch/powerpc/syscall64-abi.rst
213 IEEE 128-bit binary floating point is supported with VSX
214 quad-precision instructions and data types.
221 Documentation/arch/powerpc/syscall64-abi.rst.