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Searched +full:pxa3xx +full:- +full:nand +full:- +full:controller (Results 1 – 11 of 11) sorted by relevance

/linux/Documentation/devicetree/bindings/mtd/
H A Dmarvell,nand-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/marvell,nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell NAND Flash Controller (NFC)
10 - Miquel Raynal <miquel.raynal@bootlin.com>
15 - items:
16 - const: marvell,armada-8k-nand-controller
17 - const: marvell,armada370-nand-controller
18 - enum:
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/linux/drivers/clk/pxa/
H A Dclk-pxa3xx.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * Heavily inspired from former arch/arm/mach-pxa/pxa3xx.c
9 * For non-devicetree platforms. Once pxa is fully converted to devicetree, this
14 #include <linux/clk-provider.h>
21 #include <dt-bindings/clock/pxa-clock.h>
22 #include "clk-pxa.h"
41 #define ACCR_SMCFS_MASK (0x7 << 23) /* Static Memory Controller Frequency Select */
42 #define ACCR_SFLFS_MASK (0x3 << 18) /* Frequency Select for Internal Memory Controller */
44 #define ACCR_HSS_MASK (0x3 << 14) /* System Bus-Clock Frequency Select */
45 #define ACCR_DMCFS_MASK (0x3 << 12) /* Dynamic Memory Controller Clock Frequency Select */
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/linux/arch/arm/boot/dts/intel/pxa/
H A Dpxa3xx.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /* The pxa3xx skeleton simply augments the 2xx version */
7 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \
8 (gpio <= 98) ? (0x0400 + 4 * (gpio - 27)) : \
9 (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \
18 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \
19 (gpio <= 29) ? (0x0400 + 4 * (gpio - 27)) : \
20 (gpio <= 98) ? (0x0418 + 4 * (gpio - 30)) : \
21 (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \
23 (gpio <= 268) ? (0x052c + 4 * (gpio - 263)) : \
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H A Dpxa300-raumfeld-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include "pxa3xx.dtsi"
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
10 hw-revision = <0>;
14 stdout-path = &ffuart;
22 reg_3v3: regulator-3v3 {
23 compatible = "regulator-fixed";
24 regulator-name = "3v3-fixed-supply";
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/linux/arch/arm/mach-pxa/
H A Daddr-map.h1 /* SPDX-License-Identifier: GPL-2.0 */
28 * Static Memory Controller (w/ SDRAM controls on PXA25x/PXA27x)
36 * Dynamic Memory Controller (only on PXA3xx)
48 * DFI Bus for NAND, PXA3xx only
55 * Internal Memory Controller (PXA27x and later)
H A Dirqs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * arch/arm/mach-pxa/include/mach/irqs.h
20 #define IRQ_USBH1 PXA_IRQ(3) /* USB Host interrupt 2 (non-OHCI,PXA27x) */
21 #define IRQ_KEYPAD PXA_IRQ(4) /* Key pad controller */
23 #define IRQ_ACIPC0 PXA_IRQ(5) /* AP-CP Communication (PXA930) */
26 #define IRQ_OST_4_11 PXA_IRQ(7) /* OS timer 4-11 matches (PXA27x) */
29 #define IRQ_GPIO_2_x PXA_IRQ(10) /* GPIO[2-x] Edge Detect */
33 #define IRQ_SSP4 PXA_IRQ(13) /* SSP4 service request (PXA3xx) */
39 #define IRQ_LCD PXA_IRQ(17) /* LCD Controller Service Request */
42 #define IRQ_ACIPC2 PXA_IRQ(19) /* AP-CP Communication (PXA930) */
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H A Dpxa3xx.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-pxa/pxa3xx.c
5 * code specific to pxa3xx aka Monahans
9 * 2007-09-02: eric miao <eric.miao@marvell.com>
13 #include <linux/dma/pxa-dma.h>
17 #include <linux/gpio-pxa.h>
25 #include <linux/platform_data/i2c-pxa.h>
32 #include "pxa3xx-regs.h"
34 #include <linux/platform_data/usb-ohci-pxa27x.h>
36 #include "addr-map.h"
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/linux/drivers/mtd/nand/raw/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "Raw/Parallel NAND Device Support"
8 NAND flash devices. For further information see
9 <http://www.linux-mtd.infradead.org/doc/nand.html>.
13 comment "Raw/parallel NAND flash controllers"
19 tristate "Denali NAND controller on Intel Moorestown"
23 Enable the driver for NAND flash on Intel Moorestown, using the
24 Denali NAND controller core.
27 tristate "Denali NAND controller as a DT device"
31 Enable the driver for NAND flash on platforms using a Denali NAND
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H A Dmarvell_nand.c1 // SPDX-License-Identifier: GPL-2.0
3 * Marvell NAND flash controller driver
6 * Author: Miquel RAYNAL <miquel.raynal@free-electrons.com>
9 * This NAND controller driver handles two versions of the hardware,
17 * The ECC layouts are depicted in details in Marvell AN-379, but here
26 * controller when Hamming is chosen:
28 * +-------------------------------------------------------------+
30 * +-------------------------------------------------------------+
36 * 30B per ECC chunk. Here is the page layout used by the controller
39 * +-----------------------------------------
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/linux/Documentation/admin-guide/
H A Ddevices.txt1 0 Unnamed devices (e.g. non-device mounts)
7 2 = /dev/kmem OBSOLETE - replaced by /proc/kcore
11 6 = /dev/core OBSOLETE - replaced by /proc/kcore
18 12 = /dev/oldmem OBSOLETE - replaced by /proc/vmcore
31 2 char Pseudo-TTY masters
37 Pseudo-tty's are named as follows:
40 the 1st through 16th series of 16 pseudo-ttys each, and
44 These are the old-style (BSD) PTY devices; Unix98
50 0 = /dev/fd0 Controller 0, drive 0, autodetect
51 1 = /dev/fd1 Controller 0, drive 1, autodetect
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/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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