Lines Matching +full:pxa3xx +full:- +full:nand +full:- +full:controller
1 // SPDX-License-Identifier: GPL-2.0
3 * Marvell NAND flash controller driver
6 * Author: Miquel RAYNAL <miquel.raynal@free-electrons.com>
9 * This NAND controller driver handles two versions of the hardware,
17 * The ECC layouts are depicted in details in Marvell AN-379, but here
26 * controller when Hamming is chosen:
28 * +-------------------------------------------------------------+
30 * +-------------------------------------------------------------+
36 * 30B per ECC chunk. Here is the page layout used by the controller
39 * +-----------------------------------------
41 * +-----------------------------------------
43 * -------------------------------------------
45 * -------------------------------------------
47 * --------------------------------------------+
49 * --------------------------------------------+
56 * The controller has certain limitations that are handled by the
58 * - It can only read 2k at a time. To overcome this limitation, the
61 * - The ECC strength in BCH mode cannot be tuned. It is fixed 16
66 * - The controller will always treat data bytes, free OOB bytes
71 * - Because of these weird layouts, the Bad Block Markers can be
90 #include <linux/dma-mapping.h>
91 #include <linux/dma/pxa-dma.h>
92 #include <linux/platform_data/mtd-nand-pxa3xx.h>
112 /* System control registers/bits to enable the NAND controller on some SoCs */
124 /* NAND controller data flash control register */
143 /* NAND interface timing parameter 0 register */
157 /* NAND interface timing parameter 1 register */
166 /* NAND controller status register */
173 #define NDSR_CMDD(cs) BIT(8 - cs)
177 /* NAND ECC control register */
181 /* NAND controller data buffer register */
184 /* NAND controller command buffer 0 register */
197 /* NAND controller command buffer 1 register */
202 /* NAND controller command buffer 2 register */
207 /* NAND controller command buffer 3 register */
212 /* NAND controller command buffer 0 register 'type' and 'xtype' fields */
232 * struct marvell_hw_ecc_layout - layout of Marvell ECC
236 * per subpage, and depending on a the desired strength needed by the NAND chip,
245 * @full_chunk_cnt: Number of full-sized chunks, which is the number of
286 /* Layouts explained in AN-379_Marvell_SoC_NFC_ECC */
303 * struct marvell_nand_chip_sel - CS line description
305 * The Nand Flash Controller has up to 4 CE and 2 RB pins. The CE selection
325 * struct marvell_nand_chip - stores NAND chip device related information
327 * @chip: Base NAND chip structure
328 * @node: Used to store NAND chips into a list
329 * @layout: NAND layout when using hardware ECC
330 * @ndcr: Controller register value for this NAND chip
331 * @ndtr0: Timing registers 0 value for this NAND chip
332 * @ndtr1: Timing registers 1 value for this NAND chip
335 * @nsels: Number of CS lines required by the NAND chip
357 *nand) in to_nand_sel()
359 return &nand->sels[nand->selected_die]; in to_nand_sel()
363 * struct marvell_nfc_caps - NAND controller capabilities for distinction
369 * system controller (ie. to enable the NAND controller)
376 * @max_mode_number: Maximum timing mode supported by the controller
389 * struct marvell_nfc - stores Marvell NAND controller information
391 * @controller: Base controller structure
393 * @regs: NAND controller registers
396 * @complete: Completion object to wait for NAND controller events
398 * @chips: List containing all the NAND chips attached to
399 * this NAND controller
401 * @caps: NAND controller capabilities for each compatible string
404 * @dma_buf: 32-bit aligned buffer for DMA transfers (NFCv1 only)
407 struct nand_controller controller; member
426 return container_of(ctrl, struct marvell_nfc, controller); in to_marvell_nfc()
430 * struct marvell_nfc_timings - NAND controller timings expressed in NAND
431 * Controller clock cycles
462 * TO_CYCLES() - Derives a duration in numbers of clock cycles.
464 * @ps: Duration in pico-seconds
465 * @period_ns: Clock period in nano-seconds
467 * Convert the duration in nano-seconds, then divide by the period and
475 * struct marvell_nfc_op - filled during the parsing of the ->exec_op()
512 * The controller has many flags that could generate interrupts, most of them
521 reg = readl_relaxed(nfc->regs + NDCR); in marvell_nfc_disable_int()
522 writel_relaxed(reg | int_mask, nfc->regs + NDCR); in marvell_nfc_disable_int()
530 reg = readl_relaxed(nfc->regs + NDCR); in marvell_nfc_enable_int()
531 writel_relaxed(reg & ~int_mask, nfc->regs + NDCR); in marvell_nfc_enable_int()
538 reg = readl_relaxed(nfc->regs + NDSR); in marvell_nfc_clear_int()
539 writel_relaxed(int_mask, nfc->regs + NDSR); in marvell_nfc_clear_int()
547 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_force_byte_access()
551 * Callers of this function do not verify if the NAND is using a 16-bit in marvell_nfc_force_byte_access()
552 * an 8-bit bus for normal operations, so we need to take care of that in marvell_nfc_force_byte_access()
553 * here by leaving the configuration unchanged if the NAND does not have in marvell_nfc_force_byte_access()
556 if (!(chip->options & NAND_BUSWIDTH_16)) in marvell_nfc_force_byte_access()
559 ndcr = readl_relaxed(nfc->regs + NDCR); in marvell_nfc_force_byte_access()
566 writel_relaxed(ndcr, nfc->regs + NDCR); in marvell_nfc_force_byte_access()
571 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_wait_ndrun()
579 ret = readl_relaxed_poll_timeout(nfc->regs + NDCR, val, in marvell_nfc_wait_ndrun()
583 dev_err(nfc->dev, "Timeout on NAND controller run mode\n"); in marvell_nfc_wait_ndrun()
584 writel_relaxed(readl(nfc->regs + NDCR) & ~NDCR_ND_RUN, in marvell_nfc_wait_ndrun()
585 nfc->regs + NDCR); in marvell_nfc_wait_ndrun()
593 * Any time a command has to be sent to the controller, the following sequence
595 * - call marvell_nfc_prepare_cmd()
596 * -> activate the ND_RUN bit that will kind of 'start a job'
597 * -> wait the signal indicating the NFC is waiting for a command
598 * - send the command (cmd and address cycles)
599 * - enventually send or receive the data
600 * - call marvell_nfc_end_cmd() with the corresponding flag
601 * -> wait the flag to be triggered or cancel the job with a timeout
604 * specialized functions responsible for executing the actual NAND
609 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_prepare_cmd()
616 dev_err(nfc->dev, "Last operation did not succeed\n"); in marvell_nfc_prepare_cmd()
620 ndcr = readl_relaxed(nfc->regs + NDCR); in marvell_nfc_prepare_cmd()
621 writel_relaxed(readl(nfc->regs + NDSR), nfc->regs + NDSR); in marvell_nfc_prepare_cmd()
624 writel_relaxed(ndcr | NDCR_ND_RUN, nfc->regs + NDCR); in marvell_nfc_prepare_cmd()
625 ret = readl_relaxed_poll_timeout(nfc->regs + NDSR, val, in marvell_nfc_prepare_cmd()
629 dev_err(nfc->dev, "Timeout on WRCMDRE\n"); in marvell_nfc_prepare_cmd()
630 return -ETIMEDOUT; in marvell_nfc_prepare_cmd()
634 writel_relaxed(NDSR_WRCMDREQ, nfc->regs + NDSR); in marvell_nfc_prepare_cmd()
643 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_send_cmd()
645 dev_dbg(nfc->dev, "\nNDCR: 0x%08x\n" in marvell_nfc_send_cmd()
647 (u32)readl_relaxed(nfc->regs + NDCR), nfc_op->ndcb[0], in marvell_nfc_send_cmd()
648 nfc_op->ndcb[1], nfc_op->ndcb[2], nfc_op->ndcb[3]); in marvell_nfc_send_cmd()
650 writel_relaxed(to_nand_sel(marvell_nand)->ndcb0_csel | nfc_op->ndcb[0], in marvell_nfc_send_cmd()
651 nfc->regs + NDCB0); in marvell_nfc_send_cmd()
652 writel_relaxed(nfc_op->ndcb[1], nfc->regs + NDCB0); in marvell_nfc_send_cmd()
653 writel(nfc_op->ndcb[2], nfc->regs + NDCB0); in marvell_nfc_send_cmd()
659 if (nfc_op->ndcb[0] & NDCB0_LEN_OVRD || in marvell_nfc_send_cmd()
660 NDCB0_ADDR_GET_NUM_CYC(nfc_op->ndcb[0]) >= 6) { in marvell_nfc_send_cmd()
661 if (!WARN_ON_ONCE(!nfc->caps->is_nfcv2)) in marvell_nfc_send_cmd()
662 writel(nfc_op->ndcb[3], nfc->regs + NDCB0); in marvell_nfc_send_cmd()
669 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_end_cmd()
673 ret = readl_relaxed_poll_timeout(nfc->regs + NDSR, val, in marvell_nfc_end_cmd()
678 dev_err(nfc->dev, "Timeout on %s (NDSR: 0x%08x)\n", in marvell_nfc_end_cmd()
680 if (nfc->dma_chan) in marvell_nfc_end_cmd()
681 dmaengine_terminate_all(nfc->dma_chan); in marvell_nfc_end_cmd()
689 if (nfc->use_dma && (readl_relaxed(nfc->regs + NDCR) & NDCR_DMA_EN)) in marvell_nfc_end_cmd()
692 writel_relaxed(flag, nfc->regs + NDSR); in marvell_nfc_end_cmd()
700 int cs_flag = NDSR_CMDD(to_nand_sel(marvell_nand)->ndcb0_csel); in marvell_nfc_wait_cmdd()
713 st = readl_relaxed(nfc->regs + NDSR); in marvell_nfc_poll_status()
723 return -ETIMEDOUT; in marvell_nfc_poll_status()
728 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_wait_op()
737 if (mtd->oops_panic_write) { in marvell_nfc_wait_op()
742 init_completion(&nfc->complete); in marvell_nfc_wait_op()
745 ret = wait_for_completion_timeout(&nfc->complete, in marvell_nfc_wait_op()
756 dev_err(nfc->dev, "Timeout waiting for RB signal\n"); in marvell_nfc_wait_op()
757 return -ETIMEDOUT; in marvell_nfc_wait_op()
767 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_select_target()
774 ndcr_generic = readl_relaxed(nfc->regs + NDCR) & in marvell_nfc_select_target()
776 writel_relaxed(ndcr_generic | marvell_nand->ndcr, nfc->regs + NDCR); in marvell_nfc_select_target()
781 if (chip == nfc->selected_chip && die_nr == marvell_nand->selected_die) in marvell_nfc_select_target()
784 writel_relaxed(marvell_nand->ndtr0, nfc->regs + NDTR0); in marvell_nfc_select_target()
785 writel_relaxed(marvell_nand->ndtr1, nfc->regs + NDTR1); in marvell_nfc_select_target()
787 nfc->selected_chip = chip; in marvell_nfc_select_target()
788 marvell_nand->selected_die = die_nr; in marvell_nfc_select_target()
794 u32 st = readl_relaxed(nfc->regs + NDSR); in marvell_nfc_isr()
795 u32 ien = (~readl_relaxed(nfc->regs + NDCR)) & NDCR_ALL_INT; in marvell_nfc_isr()
810 complete(&nfc->complete); in marvell_nfc_isr()
818 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_enable_hw_ecc()
819 u32 ndcr = readl_relaxed(nfc->regs + NDCR); in marvell_nfc_enable_hw_ecc()
822 writel_relaxed(ndcr | NDCR_ECC_EN, nfc->regs + NDCR); in marvell_nfc_enable_hw_ecc()
828 if (chip->ecc.algo == NAND_ECC_ALGO_BCH) in marvell_nfc_enable_hw_ecc()
829 writel_relaxed(NDECCCTRL_BCH_EN, nfc->regs + NDECCCTRL); in marvell_nfc_enable_hw_ecc()
835 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_disable_hw_ecc()
836 u32 ndcr = readl_relaxed(nfc->regs + NDCR); in marvell_nfc_disable_hw_ecc()
839 writel_relaxed(ndcr & ~NDCR_ECC_EN, nfc->regs + NDCR); in marvell_nfc_disable_hw_ecc()
840 if (chip->ecc.algo == NAND_ECC_ALGO_BCH) in marvell_nfc_disable_hw_ecc()
841 writel_relaxed(0, nfc->regs + NDECCCTRL); in marvell_nfc_disable_hw_ecc()
850 reg = readl_relaxed(nfc->regs + NDCR); in marvell_nfc_enable_dma()
851 writel_relaxed(reg | NDCR_DMA_EN, nfc->regs + NDCR); in marvell_nfc_enable_dma()
858 reg = readl_relaxed(nfc->regs + NDCR); in marvell_nfc_disable_dma()
859 writel_relaxed(reg & ~NDCR_DMA_EN, nfc->regs + NDCR); in marvell_nfc_disable_dma()
875 sg_init_one(&sg, nfc->dma_buf, dma_len); in marvell_nfc_xfer_data_dma()
876 ret = dma_map_sg(nfc->dma_chan->device->dev, &sg, 1, direction); in marvell_nfc_xfer_data_dma()
878 dev_err(nfc->dev, "Could not map DMA S/G list\n"); in marvell_nfc_xfer_data_dma()
879 return -ENXIO; in marvell_nfc_xfer_data_dma()
882 tx = dmaengine_prep_slave_sg(nfc->dma_chan, &sg, 1, in marvell_nfc_xfer_data_dma()
887 dev_err(nfc->dev, "Could not prepare DMA S/G list\n"); in marvell_nfc_xfer_data_dma()
888 dma_unmap_sg(nfc->dma_chan->device->dev, &sg, 1, direction); in marvell_nfc_xfer_data_dma()
889 return -ENXIO; in marvell_nfc_xfer_data_dma()
896 return -EIO; in marvell_nfc_xfer_data_dma()
898 dma_async_issue_pending(nfc->dma_chan); in marvell_nfc_xfer_data_dma()
899 ret = marvell_nfc_wait_cmdd(nfc->selected_chip); in marvell_nfc_xfer_data_dma()
900 dma_unmap_sg(nfc->dma_chan->device->dev, &sg, 1, direction); in marvell_nfc_xfer_data_dma()
903 dev_err(nfc->dev, "Timeout waiting for DMA (status: %d)\n", in marvell_nfc_xfer_data_dma()
904 dmaengine_tx_status(nfc->dma_chan, cookie, NULL)); in marvell_nfc_xfer_data_dma()
905 dmaengine_terminate_all(nfc->dma_chan); in marvell_nfc_xfer_data_dma()
906 return -ETIMEDOUT; in marvell_nfc_xfer_data_dma()
920 ioread32_rep(nfc->regs + NDDB, in + i, FIFO_REP(FIFO_DEPTH)); in marvell_nfc_xfer_data_in_pio()
925 ioread32_rep(nfc->regs + NDDB, tmp_buf, FIFO_REP(FIFO_DEPTH)); in marvell_nfc_xfer_data_in_pio()
940 iowrite32_rep(nfc->regs + NDDB, out + i, FIFO_REP(FIFO_DEPTH)); in marvell_nfc_xfer_data_out_pio()
946 iowrite32_rep(nfc->regs + NDDB, tmp_buf, FIFO_REP(FIFO_DEPTH)); in marvell_nfc_xfer_data_out_pio()
974 spare, spare_len, chip->ecc.strength); in marvell_nfc_check_empty_chunk()
976 mtd->ecc_stats.failed++; in marvell_nfc_check_empty_chunk()
981 mtd->ecc_stats.corrected += bf; in marvell_nfc_check_empty_chunk()
987 * mtd->ecc_stats.corrected is updated, as well as max_bitflips, however
988 * mtd->ecc_stats.failure is not, the function will instead return a non-zero
996 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_hw_ecc_check_bitflips()
1000 ndsr = readl_relaxed(nfc->regs + NDSR); in marvell_nfc_hw_ecc_check_bitflips()
1004 writel_relaxed(ndsr, nfc->regs + NDSR); in marvell_nfc_hw_ecc_check_bitflips()
1007 * Do not increment ->ecc_stats.failed now, instead, return a in marvell_nfc_hw_ecc_check_bitflips()
1008 * non-zero value to indicate that this chunk was apparently in marvell_nfc_hw_ecc_check_bitflips()
1013 return -EBADMSG; in marvell_nfc_hw_ecc_check_bitflips()
1018 writel_relaxed(ndsr, nfc->regs + NDSR); in marvell_nfc_hw_ecc_check_bitflips()
1020 if (chip->ecc.algo == NAND_ECC_ALGO_BCH) in marvell_nfc_hw_ecc_check_bitflips()
1027 mtd->ecc_stats.corrected += bf; in marvell_nfc_hw_ecc_check_bitflips()
1039 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_hw_ecc_hmg_do_read_page()
1040 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; in marvell_nfc_hw_ecc_hmg_do_read_page()
1043 NDCB0_ADDR_CYC(marvell_nand->addr_cyc) | in marvell_nfc_hw_ecc_hmg_do_read_page()
1050 unsigned int oob_bytes = lt->spare_bytes + (raw ? lt->ecc_bytes : 0); in marvell_nfc_hw_ecc_hmg_do_read_page()
1054 if (nfc->caps->is_nfcv2) in marvell_nfc_hw_ecc_hmg_do_read_page()
1073 if (nfc->use_dma) { in marvell_nfc_hw_ecc_hmg_do_read_page()
1075 lt->data_bytes + oob_bytes); in marvell_nfc_hw_ecc_hmg_do_read_page()
1076 memcpy(data_buf, nfc->dma_buf, lt->data_bytes); in marvell_nfc_hw_ecc_hmg_do_read_page()
1077 memcpy(oob_buf, nfc->dma_buf + lt->data_bytes, oob_bytes); in marvell_nfc_hw_ecc_hmg_do_read_page()
1079 marvell_nfc_xfer_data_in_pio(nfc, data_buf, lt->data_bytes); in marvell_nfc_hw_ecc_hmg_do_read_page()
1090 marvell_nfc_select_target(chip, chip->cur_cs); in marvell_nfc_hw_ecc_hmg_read_page_raw()
1091 return marvell_nfc_hw_ecc_hmg_do_read_page(chip, buf, chip->oob_poi, in marvell_nfc_hw_ecc_hmg_read_page_raw()
1098 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; in marvell_nfc_hw_ecc_hmg_read_page()
1099 unsigned int full_sz = lt->data_bytes + lt->spare_bytes + lt->ecc_bytes; in marvell_nfc_hw_ecc_hmg_read_page()
1103 marvell_nfc_select_target(chip, chip->cur_cs); in marvell_nfc_hw_ecc_hmg_read_page()
1105 marvell_nfc_hw_ecc_hmg_do_read_page(chip, buf, chip->oob_poi, false, in marvell_nfc_hw_ecc_hmg_read_page()
1119 return -ENOMEM; in marvell_nfc_hw_ecc_hmg_read_page()
1122 lt->data_bytes, true, page); in marvell_nfc_hw_ecc_hmg_read_page()
1132 * it appears before the ECC bytes when reading), the ->read_oob_raw() function
1133 * also stands for ->read_oob().
1139 marvell_nfc_select_target(chip, chip->cur_cs); in marvell_nfc_hw_ecc_hmg_read_oob_raw()
1140 return marvell_nfc_hw_ecc_hmg_do_read_page(chip, buf, chip->oob_poi, in marvell_nfc_hw_ecc_hmg_read_oob_raw()
1153 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_hw_ecc_hmg_do_write_page()
1154 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; in marvell_nfc_hw_ecc_hmg_do_write_page()
1157 NDCB0_ADDR_CYC(marvell_nand->addr_cyc) | in marvell_nfc_hw_ecc_hmg_do_write_page()
1164 unsigned int oob_bytes = lt->spare_bytes + (raw ? lt->ecc_bytes : 0); in marvell_nfc_hw_ecc_hmg_do_write_page()
1169 if (nfc->caps->is_nfcv2) in marvell_nfc_hw_ecc_hmg_do_write_page()
1183 if (nfc->use_dma) { in marvell_nfc_hw_ecc_hmg_do_write_page()
1184 memcpy(nfc->dma_buf, data_buf, lt->data_bytes); in marvell_nfc_hw_ecc_hmg_do_write_page()
1185 memcpy(nfc->dma_buf + lt->data_bytes, oob_buf, oob_bytes); in marvell_nfc_hw_ecc_hmg_do_write_page()
1186 marvell_nfc_xfer_data_dma(nfc, DMA_TO_DEVICE, lt->data_bytes + in marvell_nfc_hw_ecc_hmg_do_write_page()
1187 lt->ecc_bytes + lt->spare_bytes); in marvell_nfc_hw_ecc_hmg_do_write_page()
1189 marvell_nfc_xfer_data_out_pio(nfc, data_buf, lt->data_bytes); in marvell_nfc_hw_ecc_hmg_do_write_page()
1198 PSEC_TO_MSEC(sdr->tPROG_max)); in marvell_nfc_hw_ecc_hmg_do_write_page()
1208 return -EIO; in marvell_nfc_hw_ecc_hmg_do_write_page()
1217 marvell_nfc_select_target(chip, chip->cur_cs); in marvell_nfc_hw_ecc_hmg_write_page_raw()
1218 return marvell_nfc_hw_ecc_hmg_do_write_page(chip, buf, chip->oob_poi, in marvell_nfc_hw_ecc_hmg_write_page_raw()
1228 marvell_nfc_select_target(chip, chip->cur_cs); in marvell_nfc_hw_ecc_hmg_write_page()
1230 ret = marvell_nfc_hw_ecc_hmg_do_write_page(chip, buf, chip->oob_poi, in marvell_nfc_hw_ecc_hmg_write_page()
1239 * it appears before the ECC bytes when reading), the ->write_oob_raw() function
1240 * also stands for ->write_oob().
1248 memset(buf, 0xFF, mtd->writesize); in marvell_nfc_hw_ecc_hmg_write_oob_raw()
1250 marvell_nfc_select_target(chip, chip->cur_cs); in marvell_nfc_hw_ecc_hmg_write_oob_raw()
1251 return marvell_nfc_hw_ecc_hmg_do_write_page(chip, buf, chip->oob_poi, in marvell_nfc_hw_ecc_hmg_write_oob_raw()
1260 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; in marvell_nfc_hw_ecc_bch_read_page_raw()
1261 u8 *oob = chip->oob_poi; in marvell_nfc_hw_ecc_bch_read_page_raw()
1262 int chunk_size = lt->data_bytes + lt->spare_bytes + lt->ecc_bytes; in marvell_nfc_hw_ecc_bch_read_page_raw()
1263 int ecc_offset = (lt->full_chunk_cnt * lt->spare_bytes) + in marvell_nfc_hw_ecc_bch_read_page_raw()
1264 lt->last_spare_bytes; in marvell_nfc_hw_ecc_bch_read_page_raw()
1265 int data_len = lt->data_bytes; in marvell_nfc_hw_ecc_bch_read_page_raw()
1266 int spare_len = lt->spare_bytes; in marvell_nfc_hw_ecc_bch_read_page_raw()
1267 int ecc_len = lt->ecc_bytes; in marvell_nfc_hw_ecc_bch_read_page_raw()
1270 marvell_nfc_select_target(chip, chip->cur_cs); in marvell_nfc_hw_ecc_bch_read_page_raw()
1273 memset(chip->oob_poi, 0xFF, mtd->oobsize); in marvell_nfc_hw_ecc_bch_read_page_raw()
1277 for (chunk = 0; chunk < lt->nchunks; chunk++) { in marvell_nfc_hw_ecc_bch_read_page_raw()
1279 if (chunk >= lt->full_chunk_cnt) { in marvell_nfc_hw_ecc_bch_read_page_raw()
1280 data_len = lt->last_data_bytes; in marvell_nfc_hw_ecc_bch_read_page_raw()
1281 spare_len = lt->last_spare_bytes; in marvell_nfc_hw_ecc_bch_read_page_raw()
1282 ecc_len = lt->last_ecc_bytes; in marvell_nfc_hw_ecc_bch_read_page_raw()
1287 buf + (lt->data_bytes * chunk), in marvell_nfc_hw_ecc_bch_read_page_raw()
1291 nand_read_data_op(chip, oob + (lt->spare_bytes * chunk), in marvell_nfc_hw_ecc_bch_read_page_raw()
1296 (ALIGN(lt->ecc_bytes, 32) * chunk), in marvell_nfc_hw_ecc_bch_read_page_raw()
1309 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_hw_ecc_bch_read_chunk()
1310 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; in marvell_nfc_hw_ecc_bch_read_chunk()
1314 NDCB0_ADDR_CYC(marvell_nand->addr_cyc) | in marvell_nfc_hw_ecc_bch_read_chunk()
1336 else if (chunk < lt->nchunks - 1) in marvell_nfc_hw_ecc_bch_read_chunk()
1348 * Drain the FIFO, 8 32-bit reads at a time, and skip in marvell_nfc_hw_ecc_bch_read_chunk()
1375 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; in marvell_nfc_hw_ecc_bch_read_page()
1376 int data_len = lt->data_bytes, spare_len = lt->spare_bytes; in marvell_nfc_hw_ecc_bch_read_page()
1377 u8 *data = buf, *spare = chip->oob_poi; in marvell_nfc_hw_ecc_bch_read_page()
1382 marvell_nfc_select_target(chip, chip->cur_cs); in marvell_nfc_hw_ecc_bch_read_page()
1390 memset(chip->oob_poi, 0xFF, mtd->oobsize); in marvell_nfc_hw_ecc_bch_read_page()
1394 for (chunk = 0; chunk < lt->nchunks; chunk++) { in marvell_nfc_hw_ecc_bch_read_page()
1396 if (chunk >= lt->full_chunk_cnt) { in marvell_nfc_hw_ecc_bch_read_page()
1397 data_len = lt->last_data_bytes; in marvell_nfc_hw_ecc_bch_read_page()
1398 spare_len = lt->last_spare_bytes; in marvell_nfc_hw_ecc_bch_read_page()
1420 * the controller in normal mode and must be re-read in raw mode. To in marvell_nfc_hw_ecc_bch_read_page()
1422 * user should re-read the page in raw mode if ECC bytes are required. in marvell_nfc_hw_ecc_bch_read_page()
1426 * In case there is any subpage read error, we usually re-read only ECC in marvell_nfc_hw_ecc_bch_read_page()
1431 * 2k page, 8b strength per 512B chunk), the controller tries to correct in marvell_nfc_hw_ecc_bch_read_page()
1433 * this strange behavior, the whole page is re-read in raw mode, not in marvell_nfc_hw_ecc_bch_read_page()
1436 for (chunk = 0; chunk < lt->nchunks; chunk++) { in marvell_nfc_hw_ecc_bch_read_page()
1445 data_off_in_page = chunk * (lt->data_bytes + lt->spare_bytes + in marvell_nfc_hw_ecc_bch_read_page()
1446 lt->ecc_bytes); in marvell_nfc_hw_ecc_bch_read_page()
1448 (chunk < lt->full_chunk_cnt ? lt->data_bytes : in marvell_nfc_hw_ecc_bch_read_page()
1449 lt->last_data_bytes); in marvell_nfc_hw_ecc_bch_read_page()
1451 (chunk < lt->full_chunk_cnt ? lt->spare_bytes : in marvell_nfc_hw_ecc_bch_read_page()
1452 lt->last_spare_bytes); in marvell_nfc_hw_ecc_bch_read_page()
1454 data_off = chunk * lt->data_bytes; in marvell_nfc_hw_ecc_bch_read_page()
1455 spare_off = chunk * lt->spare_bytes; in marvell_nfc_hw_ecc_bch_read_page()
1456 ecc_off = (lt->full_chunk_cnt * lt->spare_bytes) + in marvell_nfc_hw_ecc_bch_read_page()
1457 lt->last_spare_bytes + in marvell_nfc_hw_ecc_bch_read_page()
1458 (chunk * (lt->ecc_bytes + 2)); in marvell_nfc_hw_ecc_bch_read_page()
1460 data_len = chunk < lt->full_chunk_cnt ? lt->data_bytes : in marvell_nfc_hw_ecc_bch_read_page()
1461 lt->last_data_bytes; in marvell_nfc_hw_ecc_bch_read_page()
1462 spare_len = chunk < lt->full_chunk_cnt ? lt->spare_bytes : in marvell_nfc_hw_ecc_bch_read_page()
1463 lt->last_spare_bytes; in marvell_nfc_hw_ecc_bch_read_page()
1464 ecc_len = chunk < lt->full_chunk_cnt ? lt->ecc_bytes : in marvell_nfc_hw_ecc_bch_read_page()
1465 lt->last_ecc_bytes; in marvell_nfc_hw_ecc_bch_read_page()
1468 * Only re-read the ECC bytes, unless we are using the 2k/8b in marvell_nfc_hw_ecc_bch_read_page()
1471 * case, re-read the entire page. in marvell_nfc_hw_ecc_bch_read_page()
1473 if (lt->writesize == 2048 && lt->strength == 8) { in marvell_nfc_hw_ecc_bch_read_page()
1478 chip->oob_poi + spare_off, spare_len, in marvell_nfc_hw_ecc_bch_read_page()
1483 chip->oob_poi + ecc_off, ecc_len, in marvell_nfc_hw_ecc_bch_read_page()
1488 chip->oob_poi + spare_off, spare_len, in marvell_nfc_hw_ecc_bch_read_page()
1489 chip->oob_poi + ecc_off, ecc_len, in marvell_nfc_hw_ecc_bch_read_page()
1500 return chip->ecc.read_page_raw(chip, buf, true, page); in marvell_nfc_hw_ecc_bch_read_oob_raw()
1507 return chip->ecc.read_page(chip, buf, true, page); in marvell_nfc_hw_ecc_bch_read_oob()
1515 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; in marvell_nfc_hw_ecc_bch_write_page_raw()
1516 int full_chunk_size = lt->data_bytes + lt->spare_bytes + lt->ecc_bytes; in marvell_nfc_hw_ecc_bch_write_page_raw()
1517 int data_len = lt->data_bytes; in marvell_nfc_hw_ecc_bch_write_page_raw()
1518 int spare_len = lt->spare_bytes; in marvell_nfc_hw_ecc_bch_write_page_raw()
1519 int ecc_len = lt->ecc_bytes; in marvell_nfc_hw_ecc_bch_write_page_raw()
1521 int ecc_offset = (lt->full_chunk_cnt * lt->spare_bytes) + in marvell_nfc_hw_ecc_bch_write_page_raw()
1522 lt->last_spare_bytes; in marvell_nfc_hw_ecc_bch_write_page_raw()
1525 marvell_nfc_select_target(chip, chip->cur_cs); in marvell_nfc_hw_ecc_bch_write_page_raw()
1529 for (chunk = 0; chunk < lt->nchunks; chunk++) { in marvell_nfc_hw_ecc_bch_write_page_raw()
1530 if (chunk >= lt->full_chunk_cnt) { in marvell_nfc_hw_ecc_bch_write_page_raw()
1531 data_len = lt->last_data_bytes; in marvell_nfc_hw_ecc_bch_write_page_raw()
1532 spare_len = lt->last_spare_bytes; in marvell_nfc_hw_ecc_bch_write_page_raw()
1533 ecc_len = lt->last_ecc_bytes; in marvell_nfc_hw_ecc_bch_write_page_raw()
1541 nand_write_data_op(chip, buf + (chunk * lt->data_bytes), in marvell_nfc_hw_ecc_bch_write_page_raw()
1549 nand_write_data_op(chip, chip->oob_poi + spare_offset, in marvell_nfc_hw_ecc_bch_write_page_raw()
1554 nand_write_data_op(chip, chip->oob_poi + ecc_offset, in marvell_nfc_hw_ecc_bch_write_page_raw()
1571 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_hw_ecc_bch_write_chunk()
1572 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; in marvell_nfc_hw_ecc_bch_write_chunk()
1589 if (lt->nchunks == 1) in marvell_nfc_hw_ecc_bch_write_chunk()
1595 NDCB0_ADDR_CYC(marvell_nand->addr_cyc) | in marvell_nfc_hw_ecc_bch_write_chunk()
1599 } else if (chunk < lt->nchunks - 1) { in marvell_nfc_hw_ecc_bch_write_chunk()
1606 if (chunk == lt->nchunks - 1) in marvell_nfc_hw_ecc_bch_write_chunk()
1620 iowrite32_rep(nfc->regs + NDDB, data, FIFO_REP(data_len)); in marvell_nfc_hw_ecc_bch_write_chunk()
1621 iowrite32_rep(nfc->regs + NDDB, spare, FIFO_REP(spare_len)); in marvell_nfc_hw_ecc_bch_write_chunk()
1633 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; in marvell_nfc_hw_ecc_bch_write_page()
1635 const u8 *spare = chip->oob_poi; in marvell_nfc_hw_ecc_bch_write_page()
1636 int data_len = lt->data_bytes; in marvell_nfc_hw_ecc_bch_write_page()
1637 int spare_len = lt->spare_bytes; in marvell_nfc_hw_ecc_bch_write_page()
1641 marvell_nfc_select_target(chip, chip->cur_cs); in marvell_nfc_hw_ecc_bch_write_page()
1645 memset(chip->oob_poi, 0xFF, mtd->oobsize); in marvell_nfc_hw_ecc_bch_write_page()
1649 for (chunk = 0; chunk < lt->nchunks; chunk++) { in marvell_nfc_hw_ecc_bch_write_page()
1650 if (chunk >= lt->full_chunk_cnt) { in marvell_nfc_hw_ecc_bch_write_page()
1651 data_len = lt->last_data_bytes; in marvell_nfc_hw_ecc_bch_write_page()
1652 spare_len = lt->last_spare_bytes; in marvell_nfc_hw_ecc_bch_write_page()
1669 ret = marvell_nfc_wait_op(chip, PSEC_TO_MSEC(sdr->tPROG_max)); in marvell_nfc_hw_ecc_bch_write_page()
1682 return -EIO; in marvell_nfc_hw_ecc_bch_write_page()
1693 memset(buf, 0xFF, mtd->writesize); in marvell_nfc_hw_ecc_bch_write_oob_raw()
1695 return chip->ecc.write_page_raw(chip, buf, true, page); in marvell_nfc_hw_ecc_bch_write_oob_raw()
1703 memset(buf, 0xFF, mtd->writesize); in marvell_nfc_hw_ecc_bch_write_oob()
1705 return chip->ecc.write_page(chip, buf, true, page); in marvell_nfc_hw_ecc_bch_write_oob()
1708 /* NAND framework ->exec_op() hooks and related helpers */
1714 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_parse_instructions()
1722 for (op_id = 0; op_id < subop->ninstrs; op_id++) { in marvell_nfc_parse_instructions()
1727 instr = &subop->instrs[op_id]; in marvell_nfc_parse_instructions()
1729 switch (instr->type) { in marvell_nfc_parse_instructions()
1732 nfc_op->ndcb[0] |= in marvell_nfc_parse_instructions()
1733 NDCB0_CMD1(instr->ctx.cmd.opcode); in marvell_nfc_parse_instructions()
1735 nfc_op->ndcb[0] |= in marvell_nfc_parse_instructions()
1736 NDCB0_CMD2(instr->ctx.cmd.opcode) | in marvell_nfc_parse_instructions()
1739 nfc_op->cle_ale_delay_ns = instr->delay_ns; in marvell_nfc_parse_instructions()
1746 addrs = &instr->ctx.addr.addrs[offset]; in marvell_nfc_parse_instructions()
1748 nfc_op->ndcb[0] |= NDCB0_ADDR_CYC(naddrs); in marvell_nfc_parse_instructions()
1751 nfc_op->ndcb[1] |= addrs[i] << (8 * i); in marvell_nfc_parse_instructions()
1754 nfc_op->ndcb[2] |= NDCB2_ADDR5_CYC(addrs[4]); in marvell_nfc_parse_instructions()
1756 nfc_op->ndcb[3] |= NDCB3_ADDR6_CYC(addrs[5]); in marvell_nfc_parse_instructions()
1758 nfc_op->ndcb[3] |= NDCB3_ADDR7_CYC(addrs[6]); in marvell_nfc_parse_instructions()
1760 nfc_op->cle_ale_delay_ns = instr->delay_ns; in marvell_nfc_parse_instructions()
1764 nfc_op->data_instr = instr; in marvell_nfc_parse_instructions()
1765 nfc_op->data_instr_idx = op_id; in marvell_nfc_parse_instructions()
1766 nfc_op->ndcb[0] |= NDCB0_CMD_TYPE(TYPE_READ); in marvell_nfc_parse_instructions()
1767 if (nfc->caps->is_nfcv2) { in marvell_nfc_parse_instructions()
1768 nfc_op->ndcb[0] |= in marvell_nfc_parse_instructions()
1772 nfc_op->ndcb[3] |= round_up(len, FIFO_DEPTH); in marvell_nfc_parse_instructions()
1774 nfc_op->data_delay_ns = instr->delay_ns; in marvell_nfc_parse_instructions()
1778 nfc_op->data_instr = instr; in marvell_nfc_parse_instructions()
1779 nfc_op->data_instr_idx = op_id; in marvell_nfc_parse_instructions()
1780 nfc_op->ndcb[0] |= NDCB0_CMD_TYPE(TYPE_WRITE); in marvell_nfc_parse_instructions()
1781 if (nfc->caps->is_nfcv2) { in marvell_nfc_parse_instructions()
1782 nfc_op->ndcb[0] |= in marvell_nfc_parse_instructions()
1786 nfc_op->ndcb[3] |= round_up(len, FIFO_DEPTH); in marvell_nfc_parse_instructions()
1788 nfc_op->data_delay_ns = instr->delay_ns; in marvell_nfc_parse_instructions()
1792 nfc_op->rdy_timeout_ms = instr->ctx.waitrdy.timeout_ms; in marvell_nfc_parse_instructions()
1793 nfc_op->rdy_delay_ns = instr->delay_ns; in marvell_nfc_parse_instructions()
1803 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_xfer_data_pio()
1804 const struct nand_op_instr *instr = nfc_op->data_instr; in marvell_nfc_xfer_data_pio()
1805 unsigned int op_id = nfc_op->data_instr_idx; in marvell_nfc_xfer_data_pio()
1808 bool reading = (instr->type == NAND_OP_DATA_IN_INSTR); in marvell_nfc_xfer_data_pio()
1811 if (instr->ctx.data.force_8bit) in marvell_nfc_xfer_data_pio()
1815 u8 *in = instr->ctx.data.buf.in + offset; in marvell_nfc_xfer_data_pio()
1819 const u8 *out = instr->ctx.data.buf.out + offset; in marvell_nfc_xfer_data_pio()
1824 if (instr->ctx.data.force_8bit) in marvell_nfc_xfer_data_pio()
1838 reading = (nfc_op.data_instr->type == NAND_OP_DATA_IN_INSTR); in marvell_nfc_monolithic_access_exec()
1885 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_monolithic_access_exec()
1887 writel_relaxed(readl(nfc->regs + NDCR) & ~NDCR_ND_RUN, in marvell_nfc_monolithic_access_exec()
1888 nfc->regs + NDCR); in marvell_nfc_monolithic_access_exec()
1904 * by the controller. Reset the controller registers fields that inform in marvell_nfc_naked_access_exec()
1909 switch (subop->instrs[0].type) { in marvell_nfc_naked_access_exec()
1956 if (subop->instrs[0].type == NAND_OP_DATA_OUT_INSTR) { in marvell_nfc_naked_access_exec()
1957 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_naked_access_exec()
1959 writel_relaxed(readl(nfc->regs + NDCR) & ~NDCR_ND_RUN, in marvell_nfc_naked_access_exec()
1960 nfc->regs + NDCR); in marvell_nfc_naked_access_exec()
2182 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_exec_op()
2185 marvell_nfc_select_target(chip, op->cs); in marvell_nfc_exec_op()
2187 if (nfc->caps->is_nfcv2) in marvell_nfc_exec_op()
2203 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; in marvell_nand_ooblayout_ecc()
2206 return -ERANGE; in marvell_nand_ooblayout_ecc()
2208 oobregion->length = (lt->full_chunk_cnt * lt->ecc_bytes) + in marvell_nand_ooblayout_ecc()
2209 lt->last_ecc_bytes; in marvell_nand_ooblayout_ecc()
2210 oobregion->offset = mtd->oobsize - oobregion->length; in marvell_nand_ooblayout_ecc()
2219 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; in marvell_nand_ooblayout_free()
2222 return -ERANGE; in marvell_nand_ooblayout_free()
2228 if (mtd->writesize == SZ_4K && lt->data_bytes == SZ_2K) in marvell_nand_ooblayout_free()
2229 oobregion->offset = 6; in marvell_nand_ooblayout_free()
2231 oobregion->offset = 2; in marvell_nand_ooblayout_free()
2233 oobregion->length = (lt->full_chunk_cnt * lt->spare_bytes) + in marvell_nand_ooblayout_free()
2234 lt->last_spare_bytes - oobregion->offset; in marvell_nand_ooblayout_free()
2248 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nand_hw_ecc_controller_init()
2252 if (!nfc->caps->is_nfcv2 && in marvell_nand_hw_ecc_controller_init()
2253 (mtd->writesize + mtd->oobsize > MAX_CHUNK_SIZE)) { in marvell_nand_hw_ecc_controller_init()
2254 dev_err(nfc->dev, in marvell_nand_hw_ecc_controller_init()
2256 mtd->writesize, MAX_CHUNK_SIZE - mtd->oobsize); in marvell_nand_hw_ecc_controller_init()
2257 return -ENOTSUPP; in marvell_nand_hw_ecc_controller_init()
2260 to_marvell_nand(chip)->layout = NULL; in marvell_nand_hw_ecc_controller_init()
2263 if (mtd->writesize == l->writesize && in marvell_nand_hw_ecc_controller_init()
2264 ecc->size == l->chunk && ecc->strength == l->strength) { in marvell_nand_hw_ecc_controller_init()
2265 to_marvell_nand(chip)->layout = l; in marvell_nand_hw_ecc_controller_init()
2270 if (!to_marvell_nand(chip)->layout || in marvell_nand_hw_ecc_controller_init()
2271 (!nfc->caps->is_nfcv2 && ecc->strength > 1)) { in marvell_nand_hw_ecc_controller_init()
2272 dev_err(nfc->dev, in marvell_nand_hw_ecc_controller_init()
2274 ecc->strength, mtd->writesize); in marvell_nand_hw_ecc_controller_init()
2275 return -ENOTSUPP; in marvell_nand_hw_ecc_controller_init()
2278 /* Special care for the layout 2k/8-bit/512B */ in marvell_nand_hw_ecc_controller_init()
2279 if (l->writesize == 2048 && l->strength == 8) { in marvell_nand_hw_ecc_controller_init()
2280 if (mtd->oobsize < 128) { in marvell_nand_hw_ecc_controller_init()
2281 dev_err(nfc->dev, "Requested layout needs at least 128 OOB bytes\n"); in marvell_nand_hw_ecc_controller_init()
2282 return -ENOTSUPP; in marvell_nand_hw_ecc_controller_init()
2284 chip->bbt_options |= NAND_BBT_NO_OOB_BBM; in marvell_nand_hw_ecc_controller_init()
2289 ecc->steps = l->nchunks; in marvell_nand_hw_ecc_controller_init()
2290 ecc->size = l->data_bytes; in marvell_nand_hw_ecc_controller_init()
2292 if (ecc->strength == 1) { in marvell_nand_hw_ecc_controller_init()
2293 chip->ecc.algo = NAND_ECC_ALGO_HAMMING; in marvell_nand_hw_ecc_controller_init()
2294 ecc->read_page_raw = marvell_nfc_hw_ecc_hmg_read_page_raw; in marvell_nand_hw_ecc_controller_init()
2295 ecc->read_page = marvell_nfc_hw_ecc_hmg_read_page; in marvell_nand_hw_ecc_controller_init()
2296 ecc->read_oob_raw = marvell_nfc_hw_ecc_hmg_read_oob_raw; in marvell_nand_hw_ecc_controller_init()
2297 ecc->read_oob = ecc->read_oob_raw; in marvell_nand_hw_ecc_controller_init()
2298 ecc->write_page_raw = marvell_nfc_hw_ecc_hmg_write_page_raw; in marvell_nand_hw_ecc_controller_init()
2299 ecc->write_page = marvell_nfc_hw_ecc_hmg_write_page; in marvell_nand_hw_ecc_controller_init()
2300 ecc->write_oob_raw = marvell_nfc_hw_ecc_hmg_write_oob_raw; in marvell_nand_hw_ecc_controller_init()
2301 ecc->write_oob = ecc->write_oob_raw; in marvell_nand_hw_ecc_controller_init()
2303 chip->ecc.algo = NAND_ECC_ALGO_BCH; in marvell_nand_hw_ecc_controller_init()
2304 ecc->strength = 16; in marvell_nand_hw_ecc_controller_init()
2305 ecc->read_page_raw = marvell_nfc_hw_ecc_bch_read_page_raw; in marvell_nand_hw_ecc_controller_init()
2306 ecc->read_page = marvell_nfc_hw_ecc_bch_read_page; in marvell_nand_hw_ecc_controller_init()
2307 ecc->read_oob_raw = marvell_nfc_hw_ecc_bch_read_oob_raw; in marvell_nand_hw_ecc_controller_init()
2308 ecc->read_oob = marvell_nfc_hw_ecc_bch_read_oob; in marvell_nand_hw_ecc_controller_init()
2309 ecc->write_page_raw = marvell_nfc_hw_ecc_bch_write_page_raw; in marvell_nand_hw_ecc_controller_init()
2310 ecc->write_page = marvell_nfc_hw_ecc_bch_write_page; in marvell_nand_hw_ecc_controller_init()
2311 ecc->write_oob_raw = marvell_nfc_hw_ecc_bch_write_oob_raw; in marvell_nand_hw_ecc_controller_init()
2312 ecc->write_oob = marvell_nfc_hw_ecc_bch_write_oob; in marvell_nand_hw_ecc_controller_init()
2323 nanddev_get_ecc_requirements(&chip->base); in marvell_nand_ecc_init()
2324 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nand_ecc_init()
2327 if (ecc->engine_type != NAND_ECC_ENGINE_TYPE_NONE && in marvell_nand_ecc_init()
2328 (!ecc->size || !ecc->strength)) { in marvell_nand_ecc_init()
2329 if (requirements->step_size && requirements->strength) { in marvell_nand_ecc_init()
2330 ecc->size = requirements->step_size; in marvell_nand_ecc_init()
2331 ecc->strength = requirements->strength; in marvell_nand_ecc_init()
2333 dev_info(nfc->dev, in marvell_nand_ecc_init()
2335 ecc->size = 512; in marvell_nand_ecc_init()
2336 ecc->strength = 1; in marvell_nand_ecc_init()
2340 switch (ecc->engine_type) { in marvell_nand_ecc_init()
2349 if (!nfc->caps->is_nfcv2 && mtd->writesize != SZ_512 && in marvell_nand_ecc_init()
2350 mtd->writesize != SZ_2K) { in marvell_nand_ecc_init()
2351 dev_err(nfc->dev, "NFCv1 cannot write %d bytes pages\n", in marvell_nand_ecc_init()
2352 mtd->writesize); in marvell_nand_ecc_init()
2353 return -EINVAL; in marvell_nand_ecc_init()
2357 return -EINVAL; in marvell_nand_ecc_init()
2390 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nfc_setup_interface()
2391 unsigned int period_ns = 1000000000 / clk_get_rate(nfc->core_clk) * 2; in marvell_nfc_setup_interface()
2400 if (nfc->caps->max_mode_number && nfc->caps->max_mode_number < conf->timings.mode) in marvell_nfc_setup_interface()
2401 return -EOPNOTSUPP; in marvell_nfc_setup_interface()
2404 * SDR timings are given in pico-seconds while NFC timings must be in marvell_nfc_setup_interface()
2405 * expressed in NAND controller clock cycles, which is half of the in marvell_nfc_setup_interface()
2414 nfc_tmg.tRP = TO_CYCLES(DIV_ROUND_UP(sdr->tRC_min, 2), period_ns) - 1; in marvell_nfc_setup_interface()
2416 nfc_tmg.tWP = TO_CYCLES(DIV_ROUND_UP(sdr->tWC_min, 2), period_ns) - 1; in marvell_nfc_setup_interface()
2418 nfc_tmg.tCS = TO_CYCLES(sdr->tCS_min, period_ns); in marvell_nfc_setup_interface()
2419 nfc_tmg.tCH = TO_CYCLES(sdr->tCH_min, period_ns) - 1; in marvell_nfc_setup_interface()
2420 nfc_tmg.tADL = TO_CYCLES(sdr->tADL_min, period_ns); in marvell_nfc_setup_interface()
2423 * logic. With non-EDO timings, this is MIN_RD_DEL_CNT clock cycles. In in marvell_nfc_setup_interface()
2427 read_delay = sdr->tRC_min >= 30000 ? in marvell_nfc_setup_interface()
2430 nfc_tmg.tAR = TO_CYCLES(sdr->tAR_min, period_ns); in marvell_nfc_setup_interface()
2436 nfc_tmg.tWHR = TO_CYCLES(max_t(int, sdr->tWHR_min, sdr->tCCS_min), in marvell_nfc_setup_interface()
2437 period_ns) - 2; in marvell_nfc_setup_interface()
2438 nfc_tmg.tRHW = TO_CYCLES(max_t(int, sdr->tRHW_min, sdr->tCCS_min), in marvell_nfc_setup_interface()
2445 if (nfc->caps->is_nfcv2) { in marvell_nfc_setup_interface()
2446 nfc_tmg.tR = TO_CYCLES(sdr->tWB_max, period_ns); in marvell_nfc_setup_interface()
2448 nfc_tmg.tR = TO_CYCLES64(sdr->tWB_max + sdr->tR_max, in marvell_nfc_setup_interface()
2451 nfc_tmg.tR = nfc_tmg.tCH - 3; in marvell_nfc_setup_interface()
2459 marvell_nand->ndtr0 = in marvell_nfc_setup_interface()
2468 marvell_nand->ndtr1 = in marvell_nfc_setup_interface()
2473 if (nfc->caps->is_nfcv2) { in marvell_nfc_setup_interface()
2474 marvell_nand->ndtr0 |= in marvell_nfc_setup_interface()
2479 marvell_nand->ndtr1 |= in marvell_nfc_setup_interface()
2485 * Reset nfc->selected_chip so the next command will cause the timing in marvell_nfc_setup_interface()
2488 nfc->selected_chip = NULL; in marvell_nfc_setup_interface()
2497 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); in marvell_nand_attach_chip()
2498 struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(nfc->dev); in marvell_nand_attach_chip()
2501 if (pdata && pdata->flash_bbt) in marvell_nand_attach_chip()
2502 chip->bbt_options |= NAND_BBT_USE_FLASH; in marvell_nand_attach_chip()
2504 if (chip->bbt_options & NAND_BBT_USE_FLASH) { in marvell_nand_attach_chip()
2506 * We'll use a bad block table stored in-flash and don't in marvell_nand_attach_chip()
2509 chip->bbt_options |= NAND_BBT_NO_OOB_BBM; in marvell_nand_attach_chip()
2510 chip->bbt_td = &bbt_main_descr; in marvell_nand_attach_chip()
2511 chip->bbt_md = &bbt_mirror_descr; in marvell_nand_attach_chip()
2514 /* Save the chip-specific fields of NDCR */ in marvell_nand_attach_chip()
2515 marvell_nand->ndcr = NDCR_PAGE_SZ(mtd->writesize); in marvell_nand_attach_chip()
2516 if (chip->options & NAND_BUSWIDTH_16) in marvell_nand_attach_chip()
2517 marvell_nand->ndcr |= NDCR_DWIDTH_M | NDCR_DWIDTH_C; in marvell_nand_attach_chip()
2523 if (mtd->writesize <= 512) { in marvell_nand_attach_chip()
2524 marvell_nand->addr_cyc = 1; in marvell_nand_attach_chip()
2526 marvell_nand->addr_cyc = 2; in marvell_nand_attach_chip()
2527 marvell_nand->ndcr |= NDCR_RA_START; in marvell_nand_attach_chip()
2538 if (chip->options & NAND_ROW_ADDR_3) in marvell_nand_attach_chip()
2539 marvell_nand->addr_cyc += 3; in marvell_nand_attach_chip()
2541 marvell_nand->addr_cyc += 2; in marvell_nand_attach_chip()
2544 chip->ecc.size = pdata->ecc_step_size; in marvell_nand_attach_chip()
2545 chip->ecc.strength = pdata->ecc_strength; in marvell_nand_attach_chip()
2548 ret = marvell_nand_ecc_init(mtd, &chip->ecc); in marvell_nand_attach_chip()
2550 dev_err(nfc->dev, "ECC init failed: %d\n", ret); in marvell_nand_attach_chip()
2554 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) { in marvell_nand_attach_chip()
2561 chip->options |= NAND_NO_SUBPAGE_WRITE; in marvell_nand_attach_chip()
2564 if (pdata || nfc->caps->legacy_of_bindings) { in marvell_nand_attach_chip()
2570 mtd->name = "pxa3xx_nand-0"; in marvell_nand_attach_chip()
2571 } else if (!mtd->name) { in marvell_nand_attach_chip()
2575 * should define the following property in your NAND node, ie: in marvell_nand_attach_chip()
2577 * label = "main-storage"; in marvell_nand_attach_chip()
2579 * This way, mtd->name will be set by the core when in marvell_nand_attach_chip()
2582 mtd->name = devm_kasprintf(nfc->dev, GFP_KERNEL, in marvell_nand_attach_chip()
2583 "%s:nand.%d", dev_name(nfc->dev), in marvell_nand_attach_chip()
2584 marvell_nand->sels[0].cs); in marvell_nand_attach_chip()
2585 if (!mtd->name) { in marvell_nand_attach_chip()
2586 dev_err(nfc->dev, "Failed to allocate mtd->name\n"); in marvell_nand_attach_chip()
2587 return -ENOMEM; in marvell_nand_attach_chip()
2611 * The legacy "num-cs" property indicates the number of CS on the only in marvell_nand_chip_init()
2612 * chip connected to the controller (legacy bindings does not support in marvell_nand_chip_init()
2615 * When not using legacy bindings, a couple of "reg" and "nand-rb" in marvell_nand_chip_init()
2617 * "reg" points to the CS lines and "nand-rb" to the RB line. in marvell_nand_chip_init()
2619 if (pdata || nfc->caps->legacy_of_bindings) { in marvell_nand_chip_init()
2625 return -EINVAL; in marvell_nand_chip_init()
2629 /* Alloc the nand chip structure */ in marvell_nand_chip_init()
2635 return -ENOMEM; in marvell_nand_chip_init()
2638 marvell_nand->nsels = nsels; in marvell_nand_chip_init()
2639 marvell_nand->selected_die = -1; in marvell_nand_chip_init()
2642 if (pdata || nfc->caps->legacy_of_bindings) { in marvell_nand_chip_init()
2658 if (cs >= nfc->caps->max_cs_nb) { in marvell_nand_chip_init()
2660 cs, nfc->caps->max_cs_nb); in marvell_nand_chip_init()
2661 return -EINVAL; in marvell_nand_chip_init()
2664 if (test_and_set_bit(cs, &nfc->assigned_cs)) { in marvell_nand_chip_init()
2666 return -EINVAL; in marvell_nand_chip_init()
2677 marvell_nand->sels[i].cs = cs; in marvell_nand_chip_init()
2681 marvell_nand->sels[i].ndcb0_csel = 0; in marvell_nand_chip_init()
2685 marvell_nand->sels[i].ndcb0_csel = NDCB0_CSEL; in marvell_nand_chip_init()
2688 return -EINVAL; in marvell_nand_chip_init()
2692 if (pdata || nfc->caps->legacy_of_bindings) { in marvell_nand_chip_init()
2696 ret = of_property_read_u32_index(np, "nand-rb", i, in marvell_nand_chip_init()
2706 if (rb >= nfc->caps->max_rb_nb) { in marvell_nand_chip_init()
2708 rb, nfc->caps->max_rb_nb); in marvell_nand_chip_init()
2709 return -EINVAL; in marvell_nand_chip_init()
2712 marvell_nand->sels[i].rb = rb; in marvell_nand_chip_init()
2715 chip = &marvell_nand->chip; in marvell_nand_chip_init()
2716 chip->controller = &nfc->controller; in marvell_nand_chip_init()
2719 if (of_property_read_bool(np, "marvell,nand-keep-config")) in marvell_nand_chip_init()
2720 chip->options |= NAND_KEEP_TIMINGS; in marvell_nand_chip_init()
2723 mtd->dev.parent = dev; in marvell_nand_chip_init()
2727 * ->setup_interface() is called. in marvell_nand_chip_init()
2729 marvell_nand->ndtr0 = readl_relaxed(nfc->regs + NDTR0); in marvell_nand_chip_init()
2730 marvell_nand->ndtr1 = readl_relaxed(nfc->regs + NDTR1); in marvell_nand_chip_init()
2732 chip->options |= NAND_BUSWIDTH_AUTO; in marvell_nand_chip_init()
2734 ret = nand_scan(chip, marvell_nand->nsels); in marvell_nand_chip_init()
2736 dev_err(dev, "could not scan the nand chip\n"); in marvell_nand_chip_init()
2742 ret = mtd_device_register(mtd, pdata->parts, pdata->nr_parts); in marvell_nand_chip_init()
2751 list_add_tail(&marvell_nand->node, &nfc->chips); in marvell_nand_chip_init()
2762 list_for_each_entry_safe(entry, temp, &nfc->chips, node) { in marvell_nand_chips_cleanup()
2763 chip = &entry->chip; in marvell_nand_chips_cleanup()
2767 list_del(&entry->node); in marvell_nand_chips_cleanup()
2773 struct device_node *np = dev->of_node; in marvell_nand_chips_init()
2774 int max_cs = nfc->caps->max_cs_nb; in marvell_nand_chips_init()
2784 dev_err(dev, "too many NAND chips: %d (max = %d CS)\n", nchips, in marvell_nand_chips_init()
2786 return -EINVAL; in marvell_nand_chips_init()
2790 * Legacy bindings do not use child nodes to exhibit NAND chip in marvell_nand_chips_init()
2791 * properties and layout. Instead, NAND properties are mixed with the in marvell_nand_chips_init()
2792 * controller ones, and partitions are defined as direct subnodes of the in marvell_nand_chips_init()
2793 * NAND controller node. in marvell_nand_chips_init()
2795 if (nfc->caps->legacy_of_bindings) { in marvell_nand_chips_init()
2813 struct platform_device *pdev = container_of(nfc->dev, in marvell_nfc_init_dma()
2821 dev_warn(nfc->dev, in marvell_nfc_init_dma()
2823 return -ENOTSUPP; in marvell_nfc_init_dma()
2826 ret = dma_set_mask_and_coherent(nfc->dev, DMA_BIT_MASK(32)); in marvell_nfc_init_dma()
2830 nfc->dma_chan = dma_request_chan(nfc->dev, "data"); in marvell_nfc_init_dma()
2831 if (IS_ERR(nfc->dma_chan)) { in marvell_nfc_init_dma()
2832 ret = PTR_ERR(nfc->dma_chan); in marvell_nfc_init_dma()
2833 nfc->dma_chan = NULL; in marvell_nfc_init_dma()
2834 return dev_err_probe(nfc->dev, ret, "DMA channel request failed\n"); in marvell_nfc_init_dma()
2839 ret = -ENXIO; in marvell_nfc_init_dma()
2845 config.src_addr = r->start + NDDB; in marvell_nfc_init_dma()
2846 config.dst_addr = r->start + NDDB; in marvell_nfc_init_dma()
2849 ret = dmaengine_slave_config(nfc->dma_chan, &config); in marvell_nfc_init_dma()
2851 dev_err(nfc->dev, "Failed to configure DMA channel\n"); in marvell_nfc_init_dma()
2861 nfc->dma_buf = kmalloc(MAX_CHUNK_SIZE, GFP_KERNEL | GFP_DMA); in marvell_nfc_init_dma()
2862 if (!nfc->dma_buf) { in marvell_nfc_init_dma()
2863 ret = -ENOMEM; in marvell_nfc_init_dma()
2867 nfc->use_dma = true; in marvell_nfc_init_dma()
2872 dma_release_channel(nfc->dma_chan); in marvell_nfc_init_dma()
2873 nfc->dma_chan = NULL; in marvell_nfc_init_dma()
2888 NDCR_RD_ID_CNT(NFCV1_READID_LEN), nfc->regs + NDCR); in marvell_nfc_reset()
2889 writel_relaxed(0xFFFFFFFF, nfc->regs + NDSR); in marvell_nfc_reset()
2890 writel_relaxed(0, nfc->regs + NDECCCTRL); in marvell_nfc_reset()
2895 struct device_node *np = nfc->dev->of_node; in marvell_nfc_init()
2898 * Some SoCs like A7k/A8k need to enable manually the NAND in marvell_nfc_init()
2899 * controller, gated clocks and reset bits to avoid being bootloader in marvell_nfc_init()
2903 if (nfc->caps->need_system_controller) { in marvell_nfc_init()
2906 "marvell,system-controller"); in marvell_nfc_init()
2924 if (!nfc->caps->is_nfcv2) in marvell_nfc_init()
2934 struct device *dev = &pdev->dev; in marvell_nfc_probe()
2939 nfc = devm_kzalloc(&pdev->dev, sizeof(struct marvell_nfc), in marvell_nfc_probe()
2942 return -ENOMEM; in marvell_nfc_probe()
2944 nfc->dev = dev; in marvell_nfc_probe()
2945 nand_controller_init(&nfc->controller); in marvell_nfc_probe()
2946 nfc->controller.ops = &marvell_nand_controller_ops; in marvell_nfc_probe()
2947 INIT_LIST_HEAD(&nfc->chips); in marvell_nfc_probe()
2949 nfc->regs = devm_platform_ioremap_resource(pdev, 0); in marvell_nfc_probe()
2950 if (IS_ERR(nfc->regs)) in marvell_nfc_probe()
2951 return PTR_ERR(nfc->regs); in marvell_nfc_probe()
2957 nfc->core_clk = devm_clk_get(&pdev->dev, "core"); in marvell_nfc_probe()
2960 if (nfc->core_clk == ERR_PTR(-ENOENT)) in marvell_nfc_probe()
2961 nfc->core_clk = devm_clk_get(&pdev->dev, NULL); in marvell_nfc_probe()
2963 if (IS_ERR(nfc->core_clk)) in marvell_nfc_probe()
2964 return PTR_ERR(nfc->core_clk); in marvell_nfc_probe()
2966 ret = clk_prepare_enable(nfc->core_clk); in marvell_nfc_probe()
2970 nfc->reg_clk = devm_clk_get(&pdev->dev, "reg"); in marvell_nfc_probe()
2971 if (IS_ERR(nfc->reg_clk)) { in marvell_nfc_probe()
2972 if (PTR_ERR(nfc->reg_clk) != -ENOENT) { in marvell_nfc_probe()
2973 ret = PTR_ERR(nfc->reg_clk); in marvell_nfc_probe()
2977 nfc->reg_clk = NULL; in marvell_nfc_probe()
2980 ret = clk_prepare_enable(nfc->reg_clk); in marvell_nfc_probe()
2987 0, "marvell-nfc", nfc); in marvell_nfc_probe()
2991 /* Get NAND controller capabilities */ in marvell_nfc_probe()
2992 if (pdev->id_entry) in marvell_nfc_probe()
2993 nfc->caps = (void *)pdev->id_entry->driver_data; in marvell_nfc_probe()
2995 nfc->caps = of_device_get_match_data(&pdev->dev); in marvell_nfc_probe()
2997 if (!nfc->caps) { in marvell_nfc_probe()
2999 ret = -EINVAL; in marvell_nfc_probe()
3003 /* Init the controller and then probe the chips */ in marvell_nfc_probe()
3017 if (nfc->use_dma) in marvell_nfc_probe()
3018 dma_release_channel(nfc->dma_chan); in marvell_nfc_probe()
3020 clk_disable_unprepare(nfc->reg_clk); in marvell_nfc_probe()
3022 clk_disable_unprepare(nfc->core_clk); in marvell_nfc_probe()
3033 if (nfc->use_dma) { in marvell_nfc_remove()
3034 dmaengine_terminate_all(nfc->dma_chan); in marvell_nfc_remove()
3035 dma_release_channel(nfc->dma_chan); in marvell_nfc_remove()
3038 clk_disable_unprepare(nfc->reg_clk); in marvell_nfc_remove()
3039 clk_disable_unprepare(nfc->core_clk); in marvell_nfc_remove()
3047 list_for_each_entry(chip, &nfc->chips, node) in marvell_nfc_suspend()
3048 marvell_nfc_wait_ndrun(&chip->chip); in marvell_nfc_suspend()
3050 clk_disable_unprepare(nfc->reg_clk); in marvell_nfc_suspend()
3051 clk_disable_unprepare(nfc->core_clk); in marvell_nfc_suspend()
3061 ret = clk_prepare_enable(nfc->core_clk); in marvell_nfc_resume()
3065 ret = clk_prepare_enable(nfc->reg_clk); in marvell_nfc_resume()
3067 clk_disable_unprepare(nfc->core_clk); in marvell_nfc_resume()
3072 * Reset nfc->selected_chip so the next command will cause the timing in marvell_nfc_resume()
3075 nfc->selected_chip = NULL; in marvell_nfc_resume()
3137 .name = "pxa3xx-nand",
3146 .compatible = "marvell,armada-8k-nand-controller",
3150 .compatible = "marvell,ac5-nand-controller",
3154 .compatible = "marvell,armada370-nand-controller",
3158 .compatible = "marvell,pxa3xx-nand-controller",
3163 .compatible = "marvell,armada-8k-nand",
3167 .compatible = "marvell,armada370-nand",
3171 .compatible = "marvell,pxa3xx-nand",
3180 .name = "marvell-nfc",
3191 MODULE_DESCRIPTION("Marvell NAND controller driver");