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/linux/arch/arm/boot/dts/rockchip/
H A Drv1126.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rockchip,rv1126-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rockchip,rv1126-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
15 #address-cells = <1>;
16 #size-cells = <1>;
[all …]
H A Drv1108.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/rv1108-cru.h>
7 #include <dt-bindings/pinctrl/rockchip.h>
8 #include <dt-bindings/thermal/thermal.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
15 interrupt-parent = <&gic>;
[all …]
/linux/Documentation/devicetree/bindings/pwm/
H A Dpwm.txt1 Specifying PWM information for devices
4 1) PWM user nodes
5 -----------------
7 PWM users should specify a list of PWM devices that they want to use
8 with a property containing a 'pwm-list':
10 pwm-list ::= <single-pwm> [pwm-list]
11 single-pwm ::= <pwm-phandle> <pwm-specifier>
12 pwm-phandle : phandle to PWM controller node
13 pwm-specifier : array of #pwm-cells specifying the given PWM
16 PWM properties should be named "pwms". The exact meaning of each pwms
[all …]
H A Dpwm-amlogic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pwm/pwm-amlogic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Amlogic PWM
10 - Heiner Kallweit <hkallweit1@gmail.com>
15 - enum:
16 - amlogic,meson8b-pwm
17 - amlogic,meson-gxbb-pwm
18 - amlogic,meson-gxbb-ao-pwm
[all …]
H A Dnvidia,tegra20-pwm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pwm/nvidia,tegra20-pwm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - enum:
17 - nvidia,tegra20-pwm
18 - nvidia,tegra186-pwm
20 - items:
[all …]
H A Dpwm-st.txt1 STMicroelectronics PWM driver bindings
2 --------------------------------------
5 - compatible : "st,pwm"
6 - #pwm-cells : Number of cells used to specify a PWM. First cell
7 specifies the per-chip index of the PWM to use and the
8 second cell is the period in nanoseconds - fixed to 2
10 - reg : Physical base address and length of the controller's
12 - pinctrl-names: Set to "default".
13 - pinctrl-0: List of phandles pointing to pin configuration nodes
14 for PWM module.
[all …]
H A Dimx-pwm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pwm/imx-pwm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX PWM controller
10 - Philipp Zabel <p.zabel@pengutronix.de>
13 - $ref: pwm.yaml#
16 "#pwm-cells":
19 PWM_POLARITY_INVERTED. fsl,imx1-pwm does not support this flags.
24 - enum:
[all …]
H A Dimg-pwm.txt1 *Imagination Technologies PWM DAC driver
4 - compatible: Should be "img,pistachio-pwm"
5 - reg: Should contain physical base address and length of pwm registers.
6 - clocks: Must contain an entry for each entry in clock-names.
7 See ../clock/clock-bindings.txt for details.
8 - clock-names: Must include the following entries.
9 - pwm: PWM operating clock.
10 - sys: PWM system interface clock.
11 - #pwm-cells: Should be 2. See pwm.yaml in this directory for the
13 - img,cr-periph: Must contain a phandle to the peripheral control
[all …]
H A Dmediatek,pwm-disp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pwm/mediatek,pwm-disp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jitao Shi <jitao.shi@mediatek.com>
13 - $ref: pwm.yaml#
18 - enum:
19 - mediatek,mt2701-disp-pwm
20 - mediatek,mt6595-disp-pwm
21 - mediatek,mt8173-disp-pwm
[all …]
H A Dmediatek,mt2712-pwm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pwm/mediatek,mt2712-pwm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek PWM Controller
10 - John Crispin <john@phrozen.org>
13 - $ref: pwm.yaml#
18 - enum:
19 - mediatek,mt2712-pwm
20 - mediatek,mt6795-pwm
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3562.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rockchip,rk3562-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/power/rockchip,rk3562-power.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/reset/rockchip,rk3562-cru.h>
13 #include <dt-bindings/soc/rockchip,boot-mode.h>
14 #include <dt-bindings/thermal/thermal.h>
[all …]
H A Drk356x-base.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3568-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3568-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
[all …]
H A Drk3308.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/clock/rk3308-cru.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
[all …]
H A Drk3528.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/phy/phy.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/clock/rockchip,rk3528-cru.h>
13 #include <dt-bindings/power/rockchip,rk3528-power.h>
14 #include <dt-bindings/reset/rockchip,rk3528-cru.h>
19 interrupt-parent = <&gic>;
[all …]
H A Drk3588-base.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rockchip,rk3588-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/power/rk3588-power.h>
11 #include <dt-bindings/reset/rockchip,rk3588-cru.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/ata/ahci.h>
14 #include <dt-bindings/thermal/thermal.h>
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dnvidia,tegra124-dfll.txt4 Documentation/devicetree/bindings/clock/clock-bindings.txt
7 the fast CPU cluster. It consists of a free-running voltage controlled
10 communicating with an off-chip PMIC either via an I2C bus or via PWM signals.
13 - compatible : should be one of:
14 - "nvidia,tegra124-dfll": for Tegra124
15 - "nvidia,tegra210-dfll": for Tegra210
16 - reg : Defines the following set of registers, in the order listed:
17 - registers for the DFLL control logic.
18 - registers for the I2C output logic.
19 - registers for the integrated I2C master controller.
[all …]
/linux/Documentation/devicetree/bindings/timer/
H A Dingenic,tcu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 Documentation/arch/mips/ingenic-tcu.rst.
14 - Paul Cercueil <paul@crapouillou.net>
21 - ingenic,jz4740-tcu
22 - ingenic,jz4725b-tcu
23 - ingenic,jz4760-tcu
24 - ingenic,jz4760b-tcu
25 - ingenic,jz4770-tcu
[all …]
/linux/arch/arm64/boot/dts/amlogic/
H A Damlogic-c3.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/reset/amlogic,c3-reset.h>
10 #include <dt-bindings/clock/amlogic,c3-pll-clkc.h>
11 #include <dt-bindings/clock/amlogic,c3-scmi-clkc.h>
12 #include <dt-bindings/clock/amlogic,c3-peripherals-clkc.h>
13 #include <dt-bindings/power/amlogic,c3-pwrc.h>
14 #include <dt-bindings/gpio/amlogic-c3-gpio.h>
[all …]
/linux/Documentation/devicetree/bindings/hwmon/
H A Dnpcm750-pwm-fan.txt1 Nuvoton NPCM PWM and Fan Tacho controller device
3 The Nuvoton BMC NPCM7XX supports 8 Pulse-width modulation (PWM)
6 The Nuvoton BMC NPCM8XX supports 12 Pulse-width modulation (PWM)
9 Required properties for pwm-fan node
10 - #address-cells : should be 1.
11 - #size-cells : should be 0.
12 - compatible : "nuvoton,npcm750-pwm-fan" for Poleg NPCM7XX.
13 : "nuvoton,npcm845-pwm-fan" for Arbel NPCM8XX.
14 - reg : specifies physical base address and size of the registers.
15 - reg-names : must contain:
[all …]
/linux/arch/arm/boot/dts/st/
H A Dstm32f429.dtsi2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
22 * MA 02110-1301 USA
48 #include "../armv7-m.dtsi"
49 #include <dt-bindings/clock/stm32fx-clock.h>
50 #include <dt-bindings/mfd/stm32f4-rcc.h>
53 #address-cells = <1>;
54 #size-cells = <1>;
57 clk_hse: clk-hse {
58 #clock-cells = <0>;
[all …]
H A Dstm32f746.dtsi2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
43 #include "../armv7-m.dtsi"
44 #include <dt-bindings/clock/stm32fx-clock.h>
45 #include <dt-bindings/mfd/stm32f7-rcc.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
49 #address-cells = <1>;
50 #size-cells = <1>;
53 clk_hse: clk-hse {
54 #clock-cells = <0>;
[all …]
H A Dstm32mp131.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/stm32mp13-clks.h>
8 #include <dt-bindings/reset/stm32mp13-resets.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a7";
[all …]
/linux/arch/riscv/boot/dts/spacemit/
H A Dk1.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 #include <dt-bindings/clock/spacemit,k1-syscon.h>
8 /dts-v1/;
10 #address-cells = <2>;
11 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
18 timebase-frequency = <24000000>;
20 cpu-map {
57 riscv,isa-base = "rv64i";
[all …]
/linux/arch/loongarch/boot/dts/
H A Dloongson-2k0500.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/clock/loongson,ls2k-clk.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
27 ref_100m: clock-ref-100m {
28 compatible = "fixed-clock";
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6ul.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/clock/imx6ul-clock.h>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include "imx6ul-pinfunc.h"
12 #address-cells = <1>;
13 #size-cells = <1>;
16 * pre-existing /chosen node to be available to insert the
57 #address-cells = <1>;
[all …]

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