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/linux/Documentation/devicetree/bindings/net/
H A Dintel,ixp46x-ptp-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/intel,ixp46x-ptp-timer.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Intel IXP46x PTP Timer (TSYNC)
11 - Linus Walleij <linusw@kernel.org>
14 The Intel IXP46x PTP timer is known in the manual as IEEE1588 Hardware
15 Assist and Time Synchronization Hardware Assist TSYNC provides a PTP
16 timer. It exists in the Intel IXP45x and IXP46x XScale SoCs.
20 const: intel,ixp46x-ptp-timer
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H A Dfsl,fman.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
13 Due to the fact that the FMan is an aggregation of sub-engines (ports, MACs,
19 - fsl,fman
26 cell-index:
31 The cell-index value may be used by the SoC, to identify the
33 there's a description of the cell-index use in each SoC:
35 - P1023:
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/linux/drivers/ptp/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # PTP clock support configuration
6 menu "PTP clock support"
9 tristate "PTP clock support"
17 standard defines a Precision Time Protocol (PTP), which can
23 This driver adds support for PTP clocks as character
24 devices. If you want to use a PTP clock, then you should
28 will be called ptp.
37 into vmlinux while the PTP support itself is in a loadable
39 If PTP support is disabled, this dependency will still be
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H A Dptp_netc.c1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * NXP NETC V4 Timer driver
24 #define TMR_CTRL_PPL(i) BIT(27 - (i))
28 #define TMR_TEVNET_PPEN(i) BIT(7 - (i))
85 /* 1588 timer reference clock source select */
115 /* High 32-bit is integer part, low 32-bit is fractional part */
128 #define netc_timer_rd(p, o) netc_read((p)->base + (o))
129 #define netc_timer_wr(p, o, v) netc_write((p)->base + (o), v)
130 #define ptp_to_netc_timer(ptp) container_of((ptp), struct netc_timer, caps) argument
222 divisor = mul_u32_u32(2 * NSEC_PER_SEC, priv->oclk_prsc); in netc_timer_calculate_fiper_pw()
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H A Dptp_qoriq.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * PTP 1588 clock for Freescale QorIQ 1588 timer
26 /* Caller must hold ptp_qoriq->lock. */
29 struct ptp_qoriq_registers *regs = &ptp_qoriq->regs; in tmr_cnt_read()
33 lo = ptp_qoriq->read(&regs->ctrl_regs->tmr_cnt_l); in tmr_cnt_read()
34 hi = ptp_qoriq->read(&regs->ctrl_regs->tmr_cnt_h); in tmr_cnt_read()
40 /* Caller must hold ptp_qoriq->lock. */
43 struct ptp_qoriq_registers *regs = &ptp_qoriq->regs; in tmr_cnt_write()
47 ptp_qoriq->write(&regs->ctrl_regs->tmr_cnt_l, lo); in tmr_cnt_write()
48 ptp_qoriq->write(&regs->ctrl_regs->tmr_cnt_h, hi); in tmr_cnt_write()
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H A Dptp_dte.c1 // SPDX-License-Identifier: GPL-2.0-only
39 /* ptp dte priv structure */
90 ns = dte_read_nco(ptp_dte->regs); in dte_write_nco_delta()
94 if (ptp_dte->ts_wrap_cnt) { in dte_write_nco_delta()
96 ptp_dte->ts_wrap_cnt--; in dte_write_nco_delta()
103 ptp_dte->ts_wrap_cnt++; in dte_write_nco_delta()
104 ns -= DTE_NCO_MAX_NS; in dte_write_nco_delta()
108 dte_write_nco(ptp_dte->regs, ns); in dte_write_nco_delta()
110 ptp_dte->ts_ovf_last = (ns >> DTE_NCO_TS_WRAP_LSHIFT) & in dte_write_nco_delta()
119 ns = dte_read_nco(ptp_dte->regs); in dte_read_nco_with_ovf()
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/linux/drivers/net/ethernet/freescale/
H A Dfec_ptp.c1 // SPDX-License-Identifier: GPL-2.0
3 * Fast Ethernet Controller (ENET) PTP driver for MX6x.
92 * fec_ptp_read - read raw cycle counter (to be used by time counter)
105 tempval = readl(fep->hwp + FEC_ATIME_CTRL); in fec_ptp_read()
107 writel(tempval, fep->hwp + FEC_ATIME_CTRL); in fec_ptp_read()
109 if (fep->quirks & FEC_QUIRK_BUG_CAPTURE) in fec_ptp_read()
112 return readl(fep->hwp + FEC_ATIME); in fec_ptp_read()
120 * This function enables the PPS output on the timer channel.
129 spin_lock_irqsave(&fep->tmreg_lock, flags); in fec_ptp_enable_pps()
131 if (fep->perout_enable) { in fec_ptp_enable_pps()
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/linux/drivers/net/ethernet/cadence/
H A Dmacb_ptp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * 1588 PTP support for Cadence GEM device.
5 * Copyright (C) 2017 Cadence Design Systems - https://www.cadence.com
26 #define GEM_PTP_TIMER_NAME "gem-ptp-timer"
43 static int gem_tsu_get_time(struct ptp_clock_info *ptp, struct timespec64 *ts, in gem_tsu_get_time() argument
46 struct macb *bp = container_of(ptp, struct macb, ptp_clock_info); in gem_tsu_get_time()
51 spin_lock_irqsave(&bp->tsu_clk_lock, flags); in gem_tsu_get_time()
66 /* if so, use later read & re-read seconds in gem_tsu_get_time()
72 ts->tv_nsec = gem_readl(bp, TN); in gem_tsu_get_time()
79 ts->tv_nsec = first; in gem_tsu_get_time()
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H A Dmacb.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2004-2006 Atmel Corporation
96 #define GEM_RXPTPUNI 0x00D4 /* PTP RX Unicast address */
97 #define GEM_TXPTPUNI 0x00D8 /* PTP TX Unicast address */
98 #define GEM_EFTSH 0x00e8 /* PTP Event Frame Transmitted Seconds Register 47:32 */
99 #define GEM_EFRSH 0x00ec /* PTP Event Frame Received Seconds Register 47:32 */
100 #define GEM_PEFTSH 0x00f0 /* PTP Peer Event Frame Transmitted Seconds Register 47:32 */
101 #define GEM_PEFRSH 0x00f4 /* PTP Peer Event Frame Received Seconds Register 47:32 */
110 #define GEM_TX65CNT 0x011c /* 65-127 byte Frames TX counter */
111 #define GEM_TX128CNT 0x0120 /* 128-255 byte Frames TX counter */
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/linux/drivers/net/ethernet/mellanox/mlx4/
H A Den_clock.c14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
39 /* mlx4_en_read_clock - read raw cycle counter (to be used by time counter)
45 struct mlx4_dev *dev = mdev->dev; in mlx4_en_read_clock()
47 return mlx4_read_clock(dev) & tc->mask; in mlx4_en_read_clock()
55 lo = (u64)be16_to_cpu(ts_cqe->timestamp_lo); in mlx4_en_get_cqe_ts()
56 hi = ((u64)be32_to_cpu(ts_cqe->timestamp_hi) + !lo) << 16; in mlx4_en_get_cqe_ts()
67 seq = read_seqbegin(&mdev->clock_lock); in mlx4_en_get_hwtstamp()
68 nsec = timecounter_cyc2time(&mdev->clock, timestamp); in mlx4_en_get_hwtstamp()
69 } while (read_seqretry(&mdev->clock_lock, seq)); in mlx4_en_get_hwtstamp()
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/linux/drivers/net/ethernet/intel/ice/
H A Dice_ptp_hw.c1 // SPDX-License-Identifier: GPL-2.0
24 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR,
26 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR,
28 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, 0, },
29 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, 0, },
34 { "GNSS-1PPS", ZL_REF4P, DPLL_PIN_TYPE_GNSS,
39 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR,
41 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR,
43 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, },
44 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, },
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H A Dice_ptp.c1 // SPDX-License-Identifier: GPL-2.0
20 { TIME_SYNC, { 4, -1 }, { 0, 0 }},
21 { ONE_PPS, { -1, 5 }, { 0, 11 }},
30 { TIME_SYNC, { 4, -1 }, { 11, 0 }},
31 { ONE_PPS, { -1, 5 }, { 0, 9 }},
40 { ONE_PPS, { -1, 5 }, { 0, 1 }},
52 { SDP0, { -1, 0 }, { 0, 1 }},
53 { SDP1, { 1, -1 }, { 0, 0 }},
54 { SDP2, { -1, 2 }, { 0, 1 }},
55 { SDP3, { 3, -1 }, { 0, 0 }},
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/linux/drivers/net/ethernet/xscale/
H A Dptp_ixp46x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * PTP 1588 clock using the IXP46X
45 lo = __raw_readl(&regs->systime_lo); in ixp_systime_read()
46 hi = __raw_readl(&regs->systime_hi); in ixp_systime_read()
63 __raw_writel(lo, &regs->systime_lo); in ixp_systime_write()
64 __raw_writel(hi, &regs->systime_hi); in ixp_systime_write()
74 struct ixp46x_ts_regs *regs = ixp_clock->regs; in isr()
78 val = __raw_readl(&regs->event); in isr()
82 if (ixp_clock->exts0_enabled) { in isr()
83 hi = __raw_readl(&regs->asms_hi); in isr()
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/linux/drivers/net/ethernet/intel/idpf/
H A Didpf_ptp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
10 * struct idpf_ptp_cmd - PTP command masks
19 /* struct idpf_ptp_dev_clk_regs - PTP device registers
34 * @cmd: PTP command register
36 * @cmd_sync: PTP command synchronization register
43 /* PHY timer */
51 /* Main timer adjustments */
57 /* PHY timer adjustments */
70 * enum idpf_ptp_access - the type of access to PTP operations
82 * struct idpf_ptp_secondary_mbx - PTP secondary mailbox
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/linux/drivers/net/ethernet/chelsio/cxgb4/
H A Dcxgb4_ptp.c2 * cxgb4_ptp.c:Chelsio PTP support for T5/T6
4 * Copyright (c) 2003-2017 Chelsio Communications, Inc. All rights reserved.
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
54 * cxgb4_ptp_is_ptp_tx - determine whether TX packet is PTP or not
55 * @skb: skb of outgoing ptp request
63 return skb->len >= PTP_MIN_LENGTH && in cxgb4_ptp_is_ptp_tx()
64 skb->len <= PTP_IN_TRANSMIT_PACKET_MAXNUM && in cxgb4_ptp_is_ptp_tx()
65 likely(skb->protocol == htons(ETH_P_IP)) && in cxgb4_ptp_is_ptp_tx()
66 ip_hdr(skb)->protocol == IPPROTO_UDP && in cxgb4_ptp_is_ptp_tx()
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/linux/drivers/net/ethernet/intel/e1000e/
H A Dptp.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
4 /* PTP 1588 Hardware Clock (PHC)
5 * Derived from PTP Hardware Clock driver for Intel 82576 and 82580 (igb)
18 * e1000e_phc_adjfine - adjust the frequency of the hardware clock
19 * @ptp: ptp clock structure
27 static int e1000e_phc_adjfine(struct ptp_clock_info *ptp, long delta) in e1000e_phc_adjfine() argument
29 struct e1000_adapter *adapter = container_of(ptp, struct e1000_adapter, in e1000e_phc_adjfine()
31 struct e1000_hw *hw = &adapter->hw; in e1000e_phc_adjfine()
42 spin_lock_irqsave(&adapter->systim_lock, flags); in e1000e_phc_adjfine()
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/linux/arch/arm/boot/dts/intel/ixp/
H A Dintel-ixp45x-ixp46x.dtsi1 // SPDX-License-Identifier: ISC
8 #include "intel-ixp4xx.dtsi"
13 compatible = "intel,ixp46x-expansion-bus-controller", "syscon";
19 compatible = "intel,ixp46x-rng";
23 interrupt-controller@c8003000 {
24 compatible = "intel,ixp43x-interrupt";
32 compatible = "intel,ixp4xx-udc";
39 compatible = "intel,ixp4xx-i2c";
47 compatible = "intel,ixp4xx-ethernet";
52 queue-rx = <&qmgr 0>;
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/linux/arch/arm64/boot/dts/freescale/
H A Dqoriq-fman3-0.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
5 * Copyright 2012-2015 Freescale Semiconductor Inc.
9 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
14 cell-index = <0>;
21 clock-names = "fmanclk";
22 fsl,qman-channel-range = <0x800 0x10>;
23 ptimer-handle = <&ptp_timer0>;
24 dma-coherent;
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/linux/drivers/net/ethernet/renesas/
H A Dravb_ptp.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* PTP 1588 clock using the Renesas Ethernet AVB
4 * Copyright (C) 2013-2015 Renesas Electronics Corporation
6 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com>
13 struct net_device *ndev = priv->ndev; in ravb_ptp_tcr_request()
27 struct net_device *ndev = priv->ndev; in ravb_ptp_time_read()
34 ts->tv_nsec = ravb_read(ndev, GCT0); in ravb_ptp_time_read()
35 ts->tv_sec = ravb_read(ndev, GCT1) | in ravb_ptp_time_read()
45 struct net_device *ndev = priv->ndev; in ravb_ptp_time_write()
55 return -EBUSY; in ravb_ptp_time_write()
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/linux/include/linux/net/intel/
H A Dvirtchnl2.h1 /* SPDX-License-Identifier: GPL-2.0-only */
16 * all the structures in this header follow little-endian format.
90 * enum virtchnl2_vport_type - Type of virtual port.
98 * enum virtchnl2_queue_model - Type of queue model.
230 * enum virtchnl2_action_types - Available actions for sideband flow steering
254 * enum virtchnl2_txq_sched_mode - Transmit Queue Scheduling Modes.
269 * enum virtchnl2_rxq_flags - Receive Queue Feature flags.
302 * models. With Split Queue model, 2 additional types are introduced -
325 * enum virtchnl2_mac_addr_type - MAC address types.
436 * 32768 - 65534 are used for user defined protocol ids.
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/linux/arch/powerpc/boot/dts/fsl/
H A Dqoriq-fman3-1.dtsi4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
36 #address-cells = <1>;
37 #size-cells = <1>;
38 cell-index = <1>;
44 clock-names = "fmanclk";
45 fsl,qman-channel-range = <0x820 0x10>;
46 ptimer-handle = <&ptp_timer1>;
49 compatible = "fsl,fman-muram";
54 cell-index = <0x2>;
55 compatible = "fsl,fman-v3-port-oh";
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H A Dqoriq-fman-1.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
36 #address-cells = <1>;
37 #size-cells = <1>;
38 cell-index = <1>;
44 clock-names = "fmanclk";
45 fsl,qman-channel-range = <0x60 0xc>;
46 ptimer-handle = <&ptp_timer1>;
49 compatible = "fsl,fman-muram";
54 cell-index = <0x1>;
55 compatible = "fsl,fman-v2-port-oh";
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H A Dqoriq-fman3l-0.dtsi4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
36 #address-cells = <1>;
37 #size-cells = <1>;
38 cell-index = <0>;
44 clock-names = "fmanclk";
45 fsl,qman-channel-range = <0x800 0x10>;
46 ptimer-handle = <&ptp_timer0>;
49 compatible = "fsl,fman-muram";
54 cell-index = <0x2>;
55 compatible = "fsl,fman-v3-port-oh";
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H A Dqoriq-fman-0.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
36 #address-cells = <1>;
37 #size-cells = <1>;
38 cell-index = <0>;
44 clock-names = "fmanclk";
45 fsl,qman-channel-range = <0x40 0xc>;
46 ptimer-handle = <&ptp_timer0>;
49 compatible = "fsl,fman-muram";
54 cell-index = <0x1>;
55 compatible = "fsl,fman-v2-port-oh";
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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmarvell,armada-xp-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,mv78230-pinctrl", "marvell,mv78260-pinctrl",
8 "marvell,mv78460-pinctrl"
9 - reg: register specifier of MPP registers
39 mpp18 18 gpio, ge0(rxerr), ge1(rxd0), lcd(d18), ptp(trig)
40 mpp19 19 gpio, ge0(crs), ge1(rxd1), lcd(d19), ptp(evreq)
41 mpp20 20 gpio, ge0(rxd4), ge1(rxd2), lcd(d20), ptp(clk)
48 mpp27 27 gpio, lcd(e), tdm(dtx), ptp(trig)
49 mpp28 28 gpio, lcd(pwm), tdm(drx), ptp(evreq)
50 mpp29 29 gpio, lcd(ref-clk), tdm(int0), ptp(clk)
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