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/linux/Documentation/devicetree/bindings/net/
H A Dintel,ixp46x-ptp-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/intel,ixp46x-ptp-timer.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Intel IXP46x PTP Timer (TSYNC)
11 - Linus Walleij <linus.walleij@linaro.org>
14 The Intel IXP46x PTP timer is known in the manual as IEEE1588 Hardware
15 Assist and Time Synchronization Hardware Assist TSYNC provides a PTP
16 timer. It exists in the Intel IXP45x and IXP46x XScale SoCs.
20 const: intel,ixp46x-ptp-timer
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H A Dfsl,fman.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
13 Due to the fact that the FMan is an aggregation of sub-engines (ports, MACs,
19 - fsl,fman
26 cell-index:
31 The cell-index value may be used by the SoC, to identify the
33 there's a description of the cell-index use in each SoC:
35 - P1023:
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/linux/drivers/net/ethernet/mellanox/mlx5/core/lib/
H A Dclock.c14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
37 #include <rdma/mlx5-abi.h>
78 MLX5_MTUTC_OPERATION_ADJUST_TIME_EXTENDED_MIN = -200000,
92 struct mutex lock; /* protect mdev and used in PTP callbacks */
103 if (!clock->shared) in mlx5_clock_lockdep_assert()
106 lockdep_assert(lockdep_is_held(&clock_priv(clock)->lock)); in mlx5_clock_lockdep_assert()
113 return clock_priv(clock)->mdev; in mlx5_clock_mdev_get()
118 if (!clock->shared) in mlx5_clock_lock()
121 mutex_lock(&clock_priv(clock)->lock); in mlx5_clock_lock()
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H A Dclock.h14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
58 struct ptp_clock *ptp; member
61 struct mlx5_timer timer; member
93 return mdev->clock->ptp ? ptp_clock_index(mdev->clock->ptp) : -1; in mlx5_clock_get_ptp_index()
99 struct mlx5_timer *timer = &clock->timer; in mlx5_timecounter_cyc2time() local
104 seq = read_seqbegin(&clock->lock); in mlx5_timecounter_cyc2time()
105 nsec = timecounter_cyc2time(&timer->tc, timestamp); in mlx5_timecounter_cyc2time()
106 } while (read_seqretry(&clock->lock, seq)); in mlx5_timecounter_cyc2time()
127 return -1; in mlx5_clock_get_ptp_index()
/linux/Documentation/devicetree/bindings/ptp/
H A Dfsl,ptp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ptp/fsl,ptp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale QorIQ 1588 timer based PTP clock
10 - Frank Li <Frank.Li@nxp.com>
15 - enum:
16 - fsl,etsec-ptp
17 - fsl,fman-ptp-timer
18 - fsl,dpaa2-ptp
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/linux/drivers/net/ethernet/freescale/
H A Dfec_ptp.c1 // SPDX-License-Identifier: GPL-2.0
3 * Fast Ethernet Controller (ENET) PTP driver for MX6x.
92 * fec_ptp_read - read raw cycle counter (to be used by time counter)
105 tempval = readl(fep->hwp + FEC_ATIME_CTRL); in fec_ptp_read()
107 writel(tempval, fep->hwp + FEC_ATIME_CTRL); in fec_ptp_read()
109 if (fep->quirks & FEC_QUIRK_BUG_CAPTURE) in fec_ptp_read()
112 return readl(fep->hwp + FEC_ATIME); in fec_ptp_read()
120 * This function enables the PPS output on the timer channel.
129 spin_lock_irqsave(&fep->tmreg_lock, flags); in fec_ptp_enable_pps()
131 if (fep->pps_enable == enable) { in fec_ptp_enable_pps()
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/linux/drivers/net/ethernet/intel/idpf/
H A Didpf_ptp.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * idpf_ptp_get_access - Determine the access type of the PTP features
13 * Return: the type of supported access for the PTP feature.
18 if (adapter->ptp->caps & direct) in idpf_ptp_get_access()
20 else if (adapter->ptp->caps & mailbox) in idpf_ptp_get_access()
27 * idpf_ptp_get_features_access - Determine the access type of PTP features
30 * Fulfill the adapter structure with type of the supported PTP features
35 struct idpf_ptp *ptp = adapter->ptp; in idpf_ptp_get_features_access() local
41 ptp->get_dev_clk_time_access = idpf_ptp_get_access(adapter, in idpf_ptp_get_features_access()
48 ptp->get_cross_tstamp_access = idpf_ptp_get_access(adapter, in idpf_ptp_get_features_access()
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H A Didpf_ptp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
10 * struct idpf_ptp_cmd - PTP command masks
19 /* struct idpf_ptp_dev_clk_regs - PTP device registers
34 * @cmd: PTP command register
36 * @cmd_sync: PTP command synchronization register
43 /* PHY timer */
51 /* Main timer adjustments */
57 /* PHY timer adjustments */
70 * enum idpf_ptp_access - the type of access to PTP operations
82 * struct idpf_ptp_secondary_mbx - PTP secondary mailbox
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H A Dvirtchnl2.h1 /* SPDX-License-Identifier: GPL-2.0-only */
16 * all the structures in this header follow little-endian format.
90 * enum virtchnl2_vport_type - Type of virtual port.
98 * enum virtchnl2_queue_model - Type of queue model.
230 * enum virtchnl2_action_types - Available actions for sideband flow steering
254 * enum virtchnl2_txq_sched_mode - Transmit Queue Scheduling Modes.
269 * enum virtchnl2_rxq_flags - Receive Queue Feature flags.
302 * models. With Split Queue model, 2 additional types are introduced -
325 * enum virtchnl2_mac_addr_type - MAC address types.
436 * 32768 - 65534 are used for user defined protocol ids.
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/linux/drivers/net/ethernet/intel/ice/
H A Dice_ptp_hw.c1 // SPDX-License-Identifier: GPL-2.0
24 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR,
26 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR,
28 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, 0, },
29 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, 0, },
34 { "GNSS-1PPS", ZL_REF4P, DPLL_PIN_TYPE_GNSS,
39 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR,
41 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR,
43 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, },
44 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, },
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H A Dice_ptp.c1 // SPDX-License-Identifier: GPL-2.0
19 { TIME_SYNC, { 4, -1 }, { 0, 0 }},
20 { ONE_PPS, { -1, 5 }, { 0, 11 }},
29 { TIME_SYNC, { 4, -1 }, { 11, 0 }},
30 { ONE_PPS, { -1, 5 }, { 0, 9 }},
39 { ONE_PPS, { -1, 5 }, { 0, 1 }},
51 { SDP0, { -1, 0 }, { 0, 1 }},
52 { SDP1, { 1, -1 }, { 0, 0 }},
53 { SDP2, { -1, 2 }, { 0, 1 }},
54 { SDP3, { 3, -1 }, { 0, 0 }},
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/linux/drivers/net/ethernet/cadence/
H A Dmacb_ptp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * 1588 PTP support for Cadence GEM device.
5 * Copyright (C) 2017 Cadence Design Systems - https://www.cadence.com
26 #define GEM_PTP_TIMER_NAME "gem-ptp-timer"
31 if (bp->hw_dma_cap == HW_DMA_CAP_PTP) in macb_ptp_desc()
34 if (bp->hw_dma_cap == HW_DMA_CAP_64B_PTP) in macb_ptp_desc()
41 static int gem_tsu_get_time(struct ptp_clock_info *ptp, struct timespec64 *ts, in gem_tsu_get_time() argument
44 struct macb *bp = container_of(ptp, struct macb, ptp_clock_info); in gem_tsu_get_time()
49 spin_lock_irqsave(&bp->tsu_clk_lock, flags); in gem_tsu_get_time()
59 /* if so, use later read & re-read seconds in gem_tsu_get_time()
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/linux/drivers/net/ethernet/mellanox/mlx4/
H A Den_clock.c14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
39 /* mlx4_en_read_clock - read raw cycle counter (to be used by time counter)
45 struct mlx4_dev *dev = mdev->dev; in mlx4_en_read_clock()
47 return mlx4_read_clock(dev) & tc->mask; in mlx4_en_read_clock()
55 lo = (u64)be16_to_cpu(ts_cqe->timestamp_lo); in mlx4_en_get_cqe_ts()
56 hi = ((u64)be32_to_cpu(ts_cqe->timestamp_hi) + !lo) << 16; in mlx4_en_get_cqe_ts()
67 seq = read_seqbegin(&mdev->clock_lock); in mlx4_en_get_hwtstamp()
68 nsec = timecounter_cyc2time(&mdev->clock, timestamp); in mlx4_en_get_hwtstamp()
69 } while (read_seqretry(&mdev->clock_lock, seq)); in mlx4_en_get_hwtstamp()
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/linux/drivers/net/ethernet/xscale/
H A Dptp_ixp46x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * PTP 1588 clock using the IXP46X
46 lo = __raw_readl(&regs->systime_lo); in ixp_systime_read()
47 hi = __raw_readl(&regs->systime_hi); in ixp_systime_read()
64 __raw_writel(lo, &regs->systime_lo); in ixp_systime_write()
65 __raw_writel(hi, &regs->systime_hi); in ixp_systime_write()
75 struct ixp46x_ts_regs *regs = ixp_clock->regs; in isr()
79 val = __raw_readl(&regs->event); in isr()
83 if (ixp_clock->exts0_enabled) { in isr()
84 hi = __raw_readl(&regs->asms_hi); in isr()
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/linux/drivers/net/ethernet/chelsio/cxgb4/
H A Dcxgb4_ptp.c2 * cxgb4_ptp.c:Chelsio PTP support for T5/T6
4 * Copyright (c) 2003-2017 Chelsio Communications, Inc. All rights reserved.
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
54 * cxgb4_ptp_is_ptp_tx - determine whether TX packet is PTP or not
55 * @skb: skb of outgoing ptp request
63 return skb->len >= PTP_MIN_LENGTH && in cxgb4_ptp_is_ptp_tx()
64 skb->len <= PTP_IN_TRANSMIT_PACKET_MAXNUM && in cxgb4_ptp_is_ptp_tx()
65 likely(skb->protocol == htons(ETH_P_IP)) && in cxgb4_ptp_is_ptp_tx()
66 ip_hdr(skb)->protocol == IPPROTO_UDP && in cxgb4_ptp_is_ptp_tx()
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/linux/drivers/net/ethernet/intel/e1000e/
H A Dptp.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
4 /* PTP 1588 Hardware Clock (PHC)
5 * Derived from PTP Hardware Clock driver for Intel 82576 and 82580 (igb)
18 * e1000e_phc_adjfine - adjust the frequency of the hardware clock
19 * @ptp: ptp clock structure
27 static int e1000e_phc_adjfine(struct ptp_clock_info *ptp, long delta) in e1000e_phc_adjfine() argument
29 struct e1000_adapter *adapter = container_of(ptp, struct e1000_adapter, in e1000e_phc_adjfine()
31 struct e1000_hw *hw = &adapter->hw; in e1000e_phc_adjfine()
42 spin_lock_irqsave(&adapter->systim_lock, flags); in e1000e_phc_adjfine()
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/linux/drivers/net/ethernet/intel/igc/
H A Digc_ptp.c1 // SPDX-License-Identifier: GPL-2.0
27 struct igc_hw *hw = &adapter->hw; in igc_ptp_read()
34 ts->tv_sec = sec; in igc_ptp_read()
35 ts->tv_nsec = nsec; in igc_ptp_read()
41 struct igc_hw *hw = &adapter->hw; in igc_ptp_write_i225()
43 wr32(IGC_SYSTIML, ts->tv_nsec); in igc_ptp_write_i225()
44 wr32(IGC_SYSTIMH, ts->tv_sec); in igc_ptp_write_i225()
47 static int igc_ptp_adjfine_i225(struct ptp_clock_info *ptp, long scaled_ppm) in igc_ptp_adjfine_i225() argument
49 struct igc_adapter *igc = container_of(ptp, struct igc_adapter, in igc_ptp_adjfine_i225()
51 struct igc_hw *hw = &igc->hw; in igc_ptp_adjfine_i225()
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/linux/drivers/virtio/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
78 If disabled, you get a slightly smaller, non-transitional driver,
106 This driver provides access to virtio-pmem devices, storage devices
107 that are mapped into the physical address space - similar to NVDIMMs
108 - with a virtio-based flushing interface.
132 This driver provides access to virtio-mem paravirtualized memory
135 This driver currently supports x86-64, arm64, riscv and s390.
137 memory hot(un)plug, architecture-specific and/or common
138 code changes may be required for virtio-mem, kdump and kexec to
167 Allow virtio-mmio devices instantiation via the kernel command line
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/linux/arch/arm/boot/dts/intel/ixp/
H A Dintel-ixp45x-ixp46x.dtsi1 // SPDX-License-Identifier: ISC
8 #include "intel-ixp4xx.dtsi"
13 compatible = "intel,ixp46x-expansion-bus-controller", "syscon";
19 compatible = "intel,ixp46x-rng";
23 interrupt-controller@c8003000 {
24 compatible = "intel,ixp43x-interrupt";
32 compatible = "intel,ixp4xx-udc";
39 compatible = "intel,ixp4xx-i2c";
47 compatible = "intel,ixp4xx-ethernet";
52 queue-rx = <&qmgr 0>;
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/linux/arch/arm64/boot/dts/freescale/
H A Dqoriq-fman3-0.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
5 * Copyright 2012-2015 Freescale Semiconductor Inc.
9 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
14 cell-index = <0>;
21 clock-names = "fmanclk";
22 fsl,qman-channel-range = <0x800 0x10>;
23 ptimer-handle = <&ptp_timer0>;
24 dma-coherent;
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/linux/drivers/net/ethernet/freescale/dpaa2/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
21 Enable Priority-Based Flow Control (PFC) support for DPAA2 Ethernet
26 tristate "Freescale DPAA2 PTP Clock"
30 This driver adds support for using the DPAA2 1588 timer module
31 as a PTP clock.
/linux/drivers/ptp/
H A Dptp_dte.c1 // SPDX-License-Identifier: GPL-2.0-only
40 /* ptp dte priv structure */
91 ns = dte_read_nco(ptp_dte->regs); in dte_write_nco_delta()
95 if (ptp_dte->ts_wrap_cnt) { in dte_write_nco_delta()
97 ptp_dte->ts_wrap_cnt--; in dte_write_nco_delta()
104 ptp_dte->ts_wrap_cnt++; in dte_write_nco_delta()
105 ns -= DTE_NCO_MAX_NS; in dte_write_nco_delta()
109 dte_write_nco(ptp_dte->regs, ns); in dte_write_nco_delta()
111 ptp_dte->ts_ovf_last = (ns >> DTE_NCO_TS_WRAP_LSHIFT) & in dte_write_nco_delta()
120 ns = dte_read_nco(ptp_dte->regs); in dte_read_nco_with_ovf()
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/linux/arch/powerpc/boot/dts/fsl/
H A Dqoriq-fman3-1.dtsi4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
36 #address-cells = <1>;
37 #size-cells = <1>;
38 cell-index = <1>;
44 clock-names = "fmanclk";
45 fsl,qman-channel-range = <0x820 0x10>;
46 ptimer-handle = <&ptp_timer1>;
49 compatible = "fsl,fman-muram";
54 cell-index = <0x2>;
55 compatible = "fsl,fman-v3-port-oh";
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H A Dqoriq-fman-1.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
36 #address-cells = <1>;
37 #size-cells = <1>;
38 cell-index = <1>;
44 clock-names = "fmanclk";
45 fsl,qman-channel-range = <0x60 0xc>;
46 ptimer-handle = <&ptp_timer1>;
49 compatible = "fsl,fman-muram";
54 cell-index = <0x1>;
55 compatible = "fsl,fman-v2-port-oh";
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H A Dqoriq-fman3l-0.dtsi4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
36 #address-cells = <1>;
37 #size-cells = <1>;
38 cell-index = <0>;
44 clock-names = "fmanclk";
45 fsl,qman-channel-range = <0x800 0x10>;
46 ptimer-handle = <&ptp_timer0>;
49 compatible = "fsl,fman-muram";
54 cell-index = <0x2>;
55 compatible = "fsl,fman-v3-port-oh";
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