Home
last modified time | relevance | path

Searched +full:ptp +full:- +full:timer (Results 1 – 25 of 147) sorted by relevance

123456

/linux/Documentation/devicetree/bindings/net/
H A Dintel,ixp46x-ptp-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/intel,ixp46x-ptp-timer.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Intel IXP46x PTP Timer (TSYNC)
11 - Linus Walleij <linus.walleij@linaro.org>
14 The Intel IXP46x PTP timer is known in the manual as IEEE1588 Hardware
15 Assist and Time Synchronization Hardware Assist TSYNC provides a PTP
16 timer. It exists in the Intel IXP45x and IXP46x XScale SoCs.
20 const: intel,ixp46x-ptp-timer
[all …]
H A Dfsl,fman.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
13 Due to the fact that the FMan is an aggregation of sub-engines (ports, MACs,
19 - fsl,fman
26 cell-index:
31 The cell-index value may be used by the SoC, to identify the
33 there's a description of the cell-index use in each SoC:
35 - P1023:
[all …]
/linux/include/linux/fsl/
H A Dptp_qoriq.h1 // SPDX-License-Identifier: GPL-2.0
14 * qoriq ptp registers
17 u32 tmr_ctrl; /* Timer control register */
19 u32 tmr_temask; /* Timer event mask register */
21 u32 tmr_pemask; /* Timer event mask register */
23 u32 tmr_cnt_h; /* Timer counter high register */
24 u32 tmr_cnt_l; /* Timer counter low register */
25 u32 tmr_add; /* Timer drift compensation addend register */
26 u32 tmr_acc; /* Timer accumulator register */
27 u32 tmr_prsc; /* Timer prescale */
[all …]
/linux/Documentation/devicetree/bindings/ptp/
H A Dfsl,ptp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ptp/fsl,ptp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale QorIQ 1588 timer based PTP clock
10 - Frank Li <Frank.Li@nxp.com>
15 - enum:
16 - fsl,etsec-ptp
17 - fsl,fman-ptp-timer
18 - fsl,dpaa2-ptp
[all …]
/linux/drivers/net/ethernet/freescale/
H A Dfec_ptp.c1 // SPDX-License-Identifier: GPL-2.0
3 * Fast Ethernet Controller (ENET) PTP driver for MX6x.
92 * fec_ptp_read - read raw cycle counter (to be used by time counter)
105 tempval = readl(fep->hwp + FEC_ATIME_CTRL); in fec_ptp_read()
107 writel(tempval, fep->hwp + FEC_ATIME_CTRL); in fec_ptp_read()
109 if (fep->quirks & FEC_QUIRK_BUG_CAPTURE) in fec_ptp_read()
112 return readl(fep->hwp + FEC_ATIME); in fec_ptp_read()
120 * This function enble the PPS ouput on the timer channel.
129 spin_lock_irqsave(&fep->tmreg_lock, flags); in fec_ptp_enable_pps()
131 if (fep->pps_enable == enable) { in fec_ptp_enable_pps()
[all …]
/linux/drivers/net/ethernet/cadence/
H A Dmacb_ptp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * 1588 PTP support for Cadence GEM device.
5 * Copyright (C) 2017 Cadence Design Systems - https://www.cadence.com
26 #define GEM_PTP_TIMER_NAME "gem-ptp-timer"
31 if (bp->hw_dma_cap == HW_DMA_CAP_PTP) in macb_ptp_desc()
34 if (bp->hw_dma_cap == HW_DMA_CAP_64B_PTP) in macb_ptp_desc()
41 static int gem_tsu_get_time(struct ptp_clock_info *ptp, struct timespec64 *ts, in gem_tsu_get_time() argument
44 struct macb *bp = container_of(ptp, struct macb, ptp_clock_info); in gem_tsu_get_time()
49 spin_lock_irqsave(&bp->tsu_clk_lock, flags); in gem_tsu_get_time()
59 /* if so, use later read & re-read seconds in gem_tsu_get_time()
[all …]
H A Dmacb.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2004-2006 Atmel Corporation
100 #define GEM_RXPTPUNI 0x00D4 /* PTP RX Unicast address */
101 #define GEM_TXPTPUNI 0x00D8 /* PTP TX Unicast address */
102 #define GEM_EFTSH 0x00e8 /* PTP Event Frame Transmitted Seconds Register 47:32 */
103 #define GEM_EFRSH 0x00ec /* PTP Event Frame Received Seconds Register 47:32 */
104 #define GEM_PEFTSH 0x00f0 /* PTP Peer Event Frame Transmitted Seconds Register 47:32 */
105 #define GEM_PEFRSH 0x00f4 /* PTP Peer Event Frame Received Seconds Register 47:32 */
114 #define GEM_TX65CNT 0x011c /* 65-127 byte Frames TX counter */
115 #define GEM_TX128CNT 0x0120 /* 128-255 byte Frames TX counter */
[all …]
/linux/drivers/net/ethernet/mellanox/mlx4/
H A Den_clock.c14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
39 /* mlx4_en_read_clock - read raw cycle counter (to be used by time counter)
45 struct mlx4_dev *dev = mdev->dev; in mlx4_en_read_clock()
47 return mlx4_read_clock(dev) & tc->mask; in mlx4_en_read_clock()
55 lo = (u64)be16_to_cpu(ts_cqe->timestamp_lo); in mlx4_en_get_cqe_ts()
56 hi = ((u64)be32_to_cpu(ts_cqe->timestamp_hi) + !lo) << 16; in mlx4_en_get_cqe_ts()
67 seq = read_seqbegin(&mdev->clock_lock); in mlx4_en_get_hwtstamp()
68 nsec = timecounter_cyc2time(&mdev->clock, timestamp); in mlx4_en_get_hwtstamp()
69 } while (read_seqretry(&mdev->clock_lock, seq)); in mlx4_en_get_hwtstamp()
[all …]
/linux/drivers/net/ethernet/xscale/
H A Dptp_ixp46x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * PTP 1588 clock using the IXP46X
46 lo = __raw_readl(&regs->systime_lo); in ixp_systime_read()
47 hi = __raw_readl(&regs->systime_hi); in ixp_systime_read()
64 __raw_writel(lo, &regs->systime_lo); in ixp_systime_write()
65 __raw_writel(hi, &regs->systime_hi); in ixp_systime_write()
75 struct ixp46x_ts_regs *regs = ixp_clock->regs; in isr()
79 val = __raw_readl(&regs->event); in isr()
83 if (ixp_clock->exts0_enabled) { in isr()
84 hi = __raw_readl(&regs->asms_hi); in isr()
[all …]
/linux/drivers/net/ethernet/chelsio/cxgb4/
H A Dcxgb4_ptp.c2 * cxgb4_ptp.c:Chelsio PTP support for T5/T6
4 * Copyright (c) 2003-2017 Chelsio Communications, Inc. All rights reserved.
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
54 * cxgb4_ptp_is_ptp_tx - determine whether TX packet is PTP or not
55 * @skb: skb of outgoing ptp request
63 return skb->len >= PTP_MIN_LENGTH && in cxgb4_ptp_is_ptp_tx()
64 skb->len <= PTP_IN_TRANSMIT_PACKET_MAXNUM && in cxgb4_ptp_is_ptp_tx()
65 likely(skb->protocol == htons(ETH_P_IP)) && in cxgb4_ptp_is_ptp_tx()
66 ip_hdr(skb)->protocol == IPPROTO_UDP && in cxgb4_ptp_is_ptp_tx()
[all …]
/linux/drivers/net/ethernet/intel/e1000e/
H A Dptp.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
4 /* PTP 1588 Hardware Clock (PHC)
5 * Derived from PTP Hardware Clock driver for Intel 82576 and 82580 (igb)
18 * e1000e_phc_adjfine - adjust the frequency of the hardware clock
19 * @ptp: ptp clock structure
27 static int e1000e_phc_adjfine(struct ptp_clock_info *ptp, long delta) in e1000e_phc_adjfine() argument
29 struct e1000_adapter *adapter = container_of(ptp, struct e1000_adapter, in e1000e_phc_adjfine()
31 struct e1000_hw *hw = &adapter->hw; in e1000e_phc_adjfine()
42 spin_lock_irqsave(&adapter->systim_lock, flags); in e1000e_phc_adjfine()
[all …]
/linux/drivers/net/ethernet/intel/igc/
H A Digc_ptp.c1 // SPDX-License-Identifier: GPL-2.0
27 struct igc_hw *hw = &adapter->hw; in igc_ptp_read()
34 ts->tv_sec = sec; in igc_ptp_read()
35 ts->tv_nsec = nsec; in igc_ptp_read()
41 struct igc_hw *hw = &adapter->hw; in igc_ptp_write_i225()
43 wr32(IGC_SYSTIML, ts->tv_nsec); in igc_ptp_write_i225()
44 wr32(IGC_SYSTIMH, ts->tv_sec); in igc_ptp_write_i225()
47 static int igc_ptp_adjfine_i225(struct ptp_clock_info *ptp, long scaled_ppm) in igc_ptp_adjfine_i225() argument
49 struct igc_adapter *igc = container_of(ptp, struct igc_adapter, in igc_ptp_adjfine_i225()
51 struct igc_hw *hw = &igc->hw; in igc_ptp_adjfine_i225()
[all …]
/linux/drivers/net/ethernet/mellanox/mlx5/core/lib/
H A Dclock.h14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
58 struct ptp_clock *ptp; member
61 struct mlx5_timer timer; member
93 return mdev->clock->ptp ? ptp_clock_index(mdev->clock->ptp) : -1; in mlx5_clock_get_ptp_index()
99 struct mlx5_timer *timer = &clock->timer; in mlx5_timecounter_cyc2time() local
104 seq = read_seqbegin(&clock->lock); in mlx5_timecounter_cyc2time()
105 nsec = timecounter_cyc2time(&timer->tc, timestamp); in mlx5_timecounter_cyc2time()
106 } while (read_seqretry(&clock->lock, seq)); in mlx5_timecounter_cyc2time()
127 return -1; in mlx5_clock_get_ptp_index()
/linux/drivers/net/ethernet/intel/ice/
H A Dice_ptp.c1 // SPDX-License-Identifier: GPL-2.0
20 { TIME_SYNC, { 4, -1 }, { 0, 0 }},
21 { ONE_PPS, { -1, 5 }, { 0, 11 }},
30 { TIME_SYNC, { 4, -1 }, { 11, 0 }},
31 { ONE_PPS, { -1, 5 }, { 0, 9 }},
40 { ONE_PPS, { -1, 5 }, { 0, 1 }},
53 { GNSS, { 1, -1 }, { 0, 0 }},
55 { UFL1, { -1, 0 }, { 0, 1 }},
57 { UFL2, { 3, -1 }, { 0, 0 }},
62 return !pf->adapter ? NULL : pf->adapter->ctrl_pf; in ice_get_ctrl_pf()
[all …]
/linux/drivers/net/ethernet/renesas/
H A Drcar_gen4_ptp.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Renesas R-Car Gen4 gPTP device driver
15 #define ptp_to_priv(ptp) container_of(ptp, struct rcar_gen4_ptp_private, info) argument
29 static int rcar_gen4_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm) in rcar_gen4_ptp_adjfine() argument
31 struct rcar_gen4_ptp_private *ptp_priv = ptp_to_priv(ptp); in rcar_gen4_ptp_adjfine()
32 s64 addend = ptp_priv->default_addend; in rcar_gen4_ptp_adjfine()
37 scaled_ppm = -scaled_ppm; in rcar_gen4_ptp_adjfine()
39 addend = neg_adj ? addend - diff : addend + diff; in rcar_gen4_ptp_adjfine()
41 iowrite32(addend, ptp_priv->addr + ptp_priv->offs->increment); in rcar_gen4_ptp_adjfine()
47 static void _rcar_gen4_ptp_gettime(struct ptp_clock_info *ptp, in _rcar_gen4_ptp_gettime() argument
[all …]
/linux/drivers/ptp/
H A Dptp_qoriq.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * PTP 1588 clock for Freescale QorIQ 1588 timer
26 /* Caller must hold ptp_qoriq->lock. */
29 struct ptp_qoriq_registers *regs = &ptp_qoriq->regs; in tmr_cnt_read()
33 lo = ptp_qoriq->read(&regs->ctrl_regs->tmr_cnt_l); in tmr_cnt_read()
34 hi = ptp_qoriq->read(&regs->ctrl_regs->tmr_cnt_h); in tmr_cnt_read()
40 /* Caller must hold ptp_qoriq->lock. */
43 struct ptp_qoriq_registers *regs = &ptp_qoriq->regs; in tmr_cnt_write()
47 ptp_qoriq->write(&regs->ctrl_regs->tmr_cnt_l, lo); in tmr_cnt_write()
48 ptp_qoriq->write(&regs->ctrl_regs->tmr_cnt_h, hi); in tmr_cnt_write()
[all …]
H A Dptp_dte.c1 // SPDX-License-Identifier: GPL-2.0-only
40 /* ptp dte priv structure */
91 ns = dte_read_nco(ptp_dte->regs); in dte_write_nco_delta()
95 if (ptp_dte->ts_wrap_cnt) { in dte_write_nco_delta()
97 ptp_dte->ts_wrap_cnt--; in dte_write_nco_delta()
104 ptp_dte->ts_wrap_cnt++; in dte_write_nco_delta()
105 ns -= DTE_NCO_MAX_NS; in dte_write_nco_delta()
109 dte_write_nco(ptp_dte->regs, ns); in dte_write_nco_delta()
111 ptp_dte->ts_ovf_last = (ns >> DTE_NCO_TS_WRAP_LSHIFT) & in dte_write_nco_delta()
120 ns = dte_read_nco(ptp_dte->regs); in dte_read_nco_with_ovf()
[all …]
/linux/drivers/virtio/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
78 If disabled, you get a slightly smaller, non-transitional driver,
106 This driver provides access to virtio-pmem devices, storage devices
107 that are mapped into the physical address space - similar to NVDIMMs
108 - with a virtio-based flushing interface.
132 This driver provides access to virtio-mem paravirtualized memory
135 This driver currently supports x86-64, arm64, riscv and s390.
137 memory hot(un)plug, architecture-specific and/or common
138 code changes may be required for virtio-mem, kdump and kexec to
167 Allow virtio-mmio devices instantiation via the kernel command line
[all …]
/linux/drivers/net/ethernet/freescale/enetc/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
9 If compiled as module (M), the module name is fsl-enetc-core.
17 If compiled as module (M), the module name is nxp-enetc-pf-common.
44 If compiled as module (M), the module name is fsl-enetc.
58 based on PCIe Single Root IO Virtualization (SR-IOV) and a full range
61 If compiled as module (M), the module name is nxp-enetc4.
74 If compiled as module (M), the module name is fsl-enetc-vf.
82 If compiled as module (M), the module name is fsl-enetc-ierb.
91 If compiled as module (M), the module name is fsl-enetc-mdio.
94 tristate "ENETC PTP clock driver"
[all …]
/linux/arch/arm/boot/dts/intel/ixp/
H A Dintel-ixp45x-ixp46x.dtsi1 // SPDX-License-Identifier: ISC
8 #include "intel-ixp4xx.dtsi"
13 compatible = "intel,ixp46x-expansion-bus-controller", "syscon";
19 compatible = "intel,ixp46x-rng";
23 interrupt-controller@c8003000 {
24 compatible = "intel,ixp43x-interrupt";
32 compatible = "intel,ixp4xx-udc";
39 compatible = "intel,ixp4xx-i2c";
47 compatible = "intel,ixp4xx-ethernet";
52 queue-rx = <&qmgr 0>;
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dqoriq-fman3-0.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
5 * Copyright 2012-2015 Freescale Semiconductor Inc.
9 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
14 cell-index = <0>;
21 clock-names = "fmanclk";
22 fsl,qman-channel-range = <0x800 0x10>;
23 ptimer-handle = <&ptp_timer0>;
24 dma-coherent;
[all …]
/linux/drivers/net/ethernet/freescale/dpaa2/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
21 Enable Priority-Based Flow Control (PFC) support for DPAA2 Ethernet
26 tristate "Freescale DPAA2 PTP Clock"
30 This driver adds support for using the DPAA2 1588 timer module
31 as a PTP clock.
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmarvell,armada-xp-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,mv78230-pinctrl", "marvell,mv78260-pinctrl",
8 "marvell,mv78460-pinctrl"
9 - reg: register specifier of MPP registers
39 mpp18 18 gpio, ge0(rxerr), ge1(rxd0), lcd(d18), ptp(trig)
40 mpp19 19 gpio, ge0(crs), ge1(rxd1), lcd(d19), ptp(evreq)
41 mpp20 20 gpio, ge0(rxd4), ge1(rxd2), lcd(d20), ptp(clk)
48 mpp27 27 gpio, lcd(e), tdm(dtx), ptp(trig)
49 mpp28 28 gpio, lcd(pwm), tdm(drx), ptp(evreq)
50 mpp29 29 gpio, lcd(ref-clk), tdm(int0), ptp(clk)
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Dqoriq-fman3-1.dtsi4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
36 #address-cells = <1>;
37 #size-cells = <1>;
38 cell-index = <1>;
44 clock-names = "fmanclk";
45 fsl,qman-channel-range = <0x820 0x10>;
46 ptimer-handle = <&ptp_timer1>;
49 compatible = "fsl,fman-muram";
54 cell-index = <0x2>;
55 compatible = "fsl,fman-v3-port-oh";
[all …]
H A Dqoriq-fman-1.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
36 #address-cells = <1>;
37 #size-cells = <1>;
38 cell-index = <1>;
44 clock-names = "fmanclk";
45 fsl,qman-channel-range = <0x60 0xc>;
46 ptimer-handle = <&ptp_timer1>;
49 compatible = "fsl,fman-muram";
54 cell-index = <0x1>;
55 compatible = "fsl,fman-v2-port-oh";
[all …]

123456