| /linux/Documentation/arch/arm/ |
| H A D | marvell.rst | 44 …s://web.archive.org/web/20111027032509/http://www.marvell.com/embedded-processors/armada-300/asset…
47 …s://web.archive.org/web/20111027032509/http://www.marvell.com/embedded-processors/armada-300/asset…
50 …s://web.archive.org/web/20130730072715/http://www.marvell.com/embedded-processors/kirkwood/assets/…
51 …s://web.archive.org/web/20121021182835/http://www.marvell.com/embedded-processors/kirkwood/assets/…
52 …s://web.archive.org/web/20130730091033/http://www.marvell.com/embedded-processors/kirkwood/assets/…
55 …s://web.archive.org/web/20131113121446/http://www.marvell.com/embedded-processors/kirkwood/assets/…
56 …s://web.archive.org/web/20121021182835/http://www.marvell.com/embedded-processors/kirkwood/assets/…
57 …s://web.archive.org/web/20130730091033/http://www.marvell.com/embedded-processors/kirkwood/assets/…
61 …s://web.archive.org/web/20120616201621/http://www.marvell.com/embedded-processors/kirkwood/assets/…
62 …s://web.archive.org/web/20130730091654/http://www.marvell.com/embedded-processors/kirkwood/assets/…
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| /linux/Documentation/hwmon/ |
| H A D | k10temp.rst | 6 * AMD Family 10h processors:
16 * AMD Family 11h processors:
20 * AMD Family 12h processors: "Llano" (E2/A4/A6/A8-Series)
22 * AMD Family 14h processors: "Brazos" (C/E/G/Z-Series)
24 * AMD Family 15h processors: "Bulldozer" (FX-Series), "Trinity", "Kaveri",
27 * AMD Family 16h processors: "Kabini", "Mullins"
29 * AMD Family 17h processors: "Zen", "Zen 2"
31 * AMD Family 18h processors: "Hygon Dhyana"
33 * AMD Family 19h processors: "Zen 3"
41 BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h Processors:
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| H A D | coretemp.rst | 70 22nm Core i5/i7 Processors
81 32nm Core i3/i5/i7 Processors
88 32nm Core i7 Extreme Processors
91 32nm Celeron Processors
95 32nm Atom Processors
103 45nm Xeon Processors 5400 Quad-Core
109 45nm Xeon Processors 5200 Dual-Core
116 45nm Atom Processors
134 45nm Core2 Processors
145 45nm Core2 Quad Processors
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| H A D | fam15h_power.rst | 6 * AMD Family 15h Processors
8 * AMD Family 16h Processors
16 - BIOS and Kernel Developer's Guide (BKDG) For AMD Family 15h Processors
17 - BIOS and Kernel Developer's Guide (BKDG) For AMD Family 16h Processors
33 of AMD Family 15h and 16h processors via TDP algorithm.
35 For AMD Family 15h and 16h processors the following power values can
55 On multi-node processors the calculated value is for the entire
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| /linux/drivers/cpuidle/ |
| H A D | Kconfig.arm | 47 bool "Support for ARM big.LITTLE processors"
60 bool "CPU Idle Driver for CLPS711X processors"
66 bool "CPU Idle Driver for Calxeda processors"
70 Select this to enable cpuidle on Calxeda processors.
79 bool "CPU Idle Driver for Xilinx Zynq processors"
82 Select this to enable cpuidle on Xilinx Zynq processors.
85 bool "Cpu Idle Driver for the ST-E u8500 processors"
88 Select this to enable cpuidle for ST-E u8500 processors.
91 bool "Cpu Idle Driver for the AT91 processors"
95 Select this to enable cpuidle for AT91 processors.
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| /linux/sound/soc/sof/intel/ |
| H A D | Kconfig | 50 using the Baytrail, Braswell or Cherrytrail processors.
70 using the Broadwell processors.
94 using the Tangier/Merrifield processors.
108 This adds support for the Intel(R) platforms using the SkyLake processors.
118 This adds support for the Intel(R) platforms using the KabyLake processors.
135 using the Apollolake processors.
145 using the Geminilake processors.
162 using the Cannonlake processors.
172 using the Coffeelake processors.
182 using the Cometlake processors.
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| /linux/Documentation/arch/arc/ |
| H A D | arc.rst | 3 Linux kernel for ARC processors
10 ARC processors and relevant open source projects.
16 - `<https://github.com/foss-for-synopsys-dwc-arc-processors>`_ -
18 ARC processors. Some of the projects are forks of various upstream projects,
21 as open source for use on ARC Processors.
23 - `Official Synopsys ARC Processors website
26 Manual, AKA PRM for ARC HS processors
34 Important note on ARC processors configurability
37 ARC processors are highly configurable and several configurable options
52 Building the Linux kernel for ARC processors
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| /linux/arch/x86/ |
| H A D | Kconfig.cpu | 40 - "Geode GX/LX" For AMD Geode GX and LX processors.
197 Do not use this option for K6/Athlon/Opteron processors!
209 Select this for AMD Geode GX and LX processors.
367 bool "Support Intel processors" if PROCESSOR_SELECT
369 This enables detection, tunings and quirks for Intel processors
380 bool "Support Cyrix processors" if PROCESSOR_SELECT
383 This enables detection, tunings and quirks for Cyrix processors
394 bool "Support AMD processors" if PROCESSOR_SELECT
396 This enables detection, tunings and quirks for AMD processors
407 bool "Support Hygon processors" if PROCESSOR_SELECT
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| /linux/Documentation/admin-guide/hw-vuln/ |
| H A D | processor_mmio_stale_data.rst | 49 processors, MMIO primary reads will return 64 bytes of data to the core fill
61 processors affected by FBSDP, this may expose stale data from the fill buffers
67 into client core fill buffers, processors affected by MFBDS can leak data from
77 Affected Processors
80 processors for the server market (excluding Intel Xeon E3 processors) are
83 Below is the list of affected Intel processors [#f1]_:
115 Newer processors and microcode update on existing affected processors added new
130 values as part of MD_CLEAR operations. Processors that do not
135 IA32_MCU_OPT_CTRL[FB_CLEAR_DIS]. On such processors, the FB_CLEAR_DIS
137 FB_CLEAR action. Not all processors that support FB_CLEAR will support
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| H A D | cross-thread-rsb.rst | 7 Certain AMD and Hygon processors are subject to a cross-thread return address
18 Affected processors
23 - AMD Family 17h processors
24 - Hygon Family 18h processors
38 Affected SMT-capable processors support 1T and 2T modes of execution when SMT
46 In affected processors, the return address predictor (RAP) is partitioned
61 An attack can be mounted on affected processors by performing a series of CALL
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| H A D | special-register-buffer-data-sampling.rst | 17 Affected processors
23 in the following list, with the exception of the listed processors
25 latter class of processors are only affected when Intel TSX is enabled
70 accesses from other logical processors will be delayed until the special
78 #. Executing RDRAND at the same time on multiple logical processors will be
83 logical processors that miss their core caches, with an impact similar to
88 Software Guard Extensions (Intel SGX) enclaves. On logical processors that
91 processors memory accesses. The opt-out mechanism does not affect Intel SGX
106 for other logical processors.
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| H A D | multihit.rst | 4 iTLB multihit is an erratum where some processors may incur a machine check
12 Affected processors
18 - non-Intel processors
22 - Intel processors that have the PSCHANGE_MC_NO bit set in the
41 of the page tables. Modern processors use virtual memory, a technique that creates
42 the illusion of a very large memory for processors. This virtual space is split
47 processors include a structure, called TLB, that caches recent translations.
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| H A D | mds.rst | 8 Affected processors
11 This vulnerability affects a wide range of Intel processors. The
14 - Processors from AMD, Centaur and other non Intel vendors
20 - Intel processors which have the ARCH_CAP_MDS_NO bit set in the
26 Not all processors are affected by all variants of MDS, but the mitigation
45 When performing store, load, L1 refill operations, processors write data
260 Not specifying this option is equivalent to "mds=full". For processors
296 The kernel default mitigations for vulnerable processors are:
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| /linux/arch/x86/events/ |
| H A D | Kconfig | 10 available on NehalemEX and more modern processors.
18 monitoring on modern processors.
26 monitoring on modern processors.
32 Provide power reporting mechanism support for AMD processors.
35 average power consumption on Family 15h processors.
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| /linux/tools/perf/pmu-events/arch/x86/goldmont/ |
| H A D | frontend.json | 39 … "References per ICache line. This event counts differently than Intel processors based on Silverm…
43 …h target is to a new line.\r\nThis event counts differently than Intel processors based on Silverm…
48 …vailable in the ICache (hit). This event counts differently than Intel processors based on Silverm…
52 … cache line is in the ICache. This event counts differently than Intel processors based on Silverm…
57 …ailable in the ICache (miss). This event counts differently than Intel processors based on Silverm…
61 …he line is not in the ICache. This event counts differently than Intel processors based on Silverm…
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| /linux/tools/perf/pmu-events/arch/x86/goldmontplus/ |
| H A D | frontend.json | 39 … "References per ICache line. This event counts differently than Intel processors based on Silverm…
43 …h target is to a new line.\r\nThis event counts differently than Intel processors based on Silverm…
48 …vailable in the ICache (hit). This event counts differently than Intel processors based on Silverm…
52 … cache line is in the ICache. This event counts differently than Intel processors based on Silverm…
57 …ailable in the ICache (miss). This event counts differently than Intel processors based on Silverm…
61 …he line is not in the ICache. This event counts differently than Intel processors based on Silverm…
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| /linux/drivers/spmi/ |
| H A D | Kconfig | 9 serial interface between baseband and application processors
30 processors.
41 processors.
52 processors.
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| /linux/Documentation/arch/powerpc/ |
| H A D | ptrace.rst | 6 processors:
14 that's extendable and that covers both BookE and server processors, so
23 BookE processors don't have restrictions here, but server processors have
87 that the BookE supports. COMEFROM breakpoints available in server processors
137 - set a watchpoint in server processors (BookS)::
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| /linux/drivers/crypto/ |
| H A D | Kconfig | 8 processors. This option alone does not add any kernel code.
20 Some VIA processors come with an integrated crypto engine
50 Available in VIA C7 and newer processors.
257 The Freescale SEC is present on PowerQUICC 'E' processors, such
307 OMAP processors have various crypto HW accelerators. Select this if
322 OMAP processors have MD5/SHA1/SHA2 hw accelerator. Select this if you
336 OMAP processors have AES module accelerator. Select this if you
346 OMAP processors have DES/3DES module accelerator. Select this if you
409 coprocessor that is in IBM PowerPC P7+ or later processors. This
422 Some Atmel processors can combine the AES and SHA hw accelerators
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| /linux/arch/sh/ |
| H A D | Kconfig.cpu | 24 Selecting this option will enable support for SH processors that
43 Selecting this option will enable support for SH processors that
63 the store queues integrated in the SH-4 processors.
84 This will enable the use of SR.RB register bank usage. Processors
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| /linux/arch/x86/kvm/ |
| H A D | Kconfig | 96 tristate "KVM for Intel (and compatible) processors support"
101 Provides support for KVM on processors equipped with Intel's VT
140 confidential VMs on Intel processors.
145 tristate "KVM for AMD processors support"
148 Provides support for KVM on AMD processors equipped with the AMD-V
167 Secure Nested Paging (SEV-SNP) technologies on AMD processors.
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| /linux/Documentation/admin-guide/pm/ |
| H A D | intel_pstate.rst | 19 generations of Intel processors. Note, however, that some of those processors
24 For the processors supported by ``intel_pstate``, the P-state concept is broader
68 This is the default operation mode of ``intel_pstate`` for processors with
147 This operation mode is optional for processors that do not support the HWP
151 In this mode ``intel_pstate`` may refuse to work with processors that are not
198 This is the default operation mode of ``intel_pstate`` for processors without
205 processors that are not recognized by it if HWP is prevented from being enabled
252 processors will never use any P-states above the last one set by software for
256 processors setting any P-state from the turbo range will enable the processor
272 Some processors allow multiple cores to be in turbo P-states at the same time,
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| /linux/drivers/video/fbdev/geode/ |
| H A D | Kconfig | 11 the AMD Geode family of processors.
19 AMD Geode LX processors.
32 AMD Geode GX processors.
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| /linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | intel,ixp4xx-interrupt.yaml | 8 title: Intel IXP4xx XScale Networking Processors Interrupt Controller
14 This interrupt controller is found in the Intel IXP4xx processors.
15 Some processors have 32 interrupts, some have up to 64 interrupts.
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| /linux/Documentation/devicetree/bindings/arm/ |
| H A D | arm,corstone1000.yaml | 16 processors.
18 Support for Cortex‑A32, Cortex‑A35 and Cortex‑A53 processors. Two expansion
19 systems for M-Class (or other) processors for adding sensors, connectivity,
|