| /linux/tools/power/cpupower/man/ |
| H A D | cpupower-idle-set.1 | 1 .TH "CPUPOWER-IDLE-SET" "1" "0.1" "" "cpupower Manual"
4 cpupower\-idle\-set \- Utility to set cpu idle state specific kernel options
7 cpupower [ \-c cpulist ] idle\-set [\fIoptions\fP]
10 The cpupower idle\-set subcommand allows to set cpu idle, also called cpu
11 sleep state, specific options offered by the kernel. One example is disabling
16 \fB\-d\fR \fB\-\-disable\fR <STATE_NO>
17 Disable a specific processor sleep state.
19 \fB\-e\fR \fB\-\-enable\fR <STATE_NO>
20 Enable a specific processor sleep state.
22 \fB\-D\fR \fB\-\-disable-by-latency\fR <LATENCY>
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| H A D | cpupower-monitor.1 | 1 .TH CPUPOWER\-MONITOR "1" "22/02/2011" "" "cpupower Manual"
3 cpupower\-monitor \- Report processor frequency and idle statistics
7 .RB "\-l"
10 .RB [ -c ] [ "\-m <mon1>," [ "<mon2>,..." ] ]
11 .RB [ "\-i seconds" ]
14 .RB [ -c ][ "\-m <mon1>," [ "<mon2>,..." ] ]
18 \fBcpupower-monitor \fP reports processor topology, frequency and idle power
22 \fBcpupower-monitor \fP implements independent processor sleep state and
24 directly reading out hardware registers. Use \-l to get an overview which are
29 \-l
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| H A D | cpupower-idle-info.1 | 1 .TH "CPUPOWER-IDLE-INFO" "1" "0.1" "" "cpupower Manual"
4 cpupower\-idle\-info \- Utility to retrieve cpu idle kernel information
7 cpupower [ \-c cpulist ] idle\-info [\fIoptions\fP]
14 \fB\-s\fR \fB\-\-silen
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| H A D | cpupower-info.1 | 1 .TH CPUPOWER\-INFO "1" "22/02/2011" "" "cpupower Manual"
3 cpupower\-info \- Shows processor power related kernel or hardware configurations
9 \fBcpupower info \fP shows kernel configurations or processor hardware
10 registers affecting processor power saving policies.
13 of core zero are displayed only. cpupower --cpu all cpuinfo will show the
14 settings of all cores, see cpupower(1) how to choose specific cores.
19 \fB\-
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| H A D | cpupower-set.1 | 1 .TH CPUPOWER\-SET "1" "22/02/2011" "" "cpupower Manual"
3 cpupower\-set \- Set processor power related kernel or hardware configurations
6 .B cpupower set [ \-b VAL | \-e POLICY | \-m MODE | \-t BOOL ]
11 registers affecting processor power saving policies.
15 described in the cpupower(1) manpage in the \-\-cpu option section. Whether an
24 \-\-perf-bias, \-b
28 the processor.
30 The range of valid numbers is 0-15, where 0 is maximum
33 The processor uses this information in model-specific ways
34 when it must select trade-offs between performance and
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| /linux/include/linux/ |
| H A D | remoteproc.h | 2 * Remote Processor Framework
20 * from this software without specific prior written permission.
50 * struct rproc_mem_entry - memory entry descriptor
63 * @alloc: specific memory allocator function
84 * enum rsc_handling_status - return status of rproc_ops handle_rsc hook
94 * struct rproc_ops - platform-specific device handlers
110 * @load: load firmware to memory, where the remote processor
142 * enum rproc_state - remot
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| /linux/Documentation/admin-guide/pm/ |
| H A D | intel_idle.rst | 1 .. SPDX-License-Identifier: GPL-2.0
20 a particular processor model in it depends on whether or not it recognizes that
21 processor model and may also depend on information coming from the platform
24 Documentation/admin-guide/pm/cpuidle.rst if you have not done that yet.]
26 ``intel_idle`` uses the ``MWAIT`` instruction to inform the processor that the
28 processor's functional blocks into low-power states. That instruction takes two
30 first of which, referred to as a *hint*, can be used by the processor to
38 only way to pass early-configuration-time parameters to it is via the kernel
55 C-state requests from the OS (e.g., C6 requests) to C1. The idea is that
56 firmware monitors CPU wake-up rate, and if it is higher than a
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| H A D | intel_pstate.rst | 1 .. SPDX-License-Identifier: GPL-2.0
22 Documentation/admin-guide/pm/cpufreq.rst if you have not done that yet.]
24 For the processors supported by ``intel_pstate``, the P-state concept is broader
27 information about that). For this reason, the representation of P-states used
32 ``intel_pstate`` maps its internal representation of P-states to frequencies too
38 Since the hardware P-state selection interface used by ``intel_pstate`` is
43 time the corresponding CPU is taken offline and need to be re-initialized when
47 only way to pass early-configuration-time parameters to it is via the kernel
64 the processor.
69 -----------
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| /linux/arch/alpha/include/asm/ |
| H A D | mce.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
14 unsigned int proc_offset; /* processor-specific offset */
15 unsigned int sys_offset; /* system-specific offset */
21 * --- This is used to log uncorrectable errors such as
23 * --- These errors are detected by both processor and systems.
26 unsigned long shadow[8]; /* Shadow reg. 8-14, 25 */
34 unsigned long ic_perr_stat; /* I-CACHE Reg. <11> set Data parity
36 unsigned long dc_perr_stat; /* D-CACHE error Reg. Bits set to 1:
42 unsigned long mm_stat; /* Holds the reason for D-stream
43 fault or D-cache parity errors */
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| /linux/tools/power/x86/x86_energy_perf_policy/ |
| H A D | x86_energy_perf_policy.8 | 1 .\" This page Copyright (C) 2010 - 2015 Len Brown <len.brown@intel.com>
5 x86_energy_perf_policy \- Manage Energy vs. Performance Policy
10 .RB "scope: \-\-cpu\ cpu-list | \-\-pkg\ pkg-list"
12 .RB "cpu-list, pkg-list: # | #,# | #-# | all"
14 .RB "field: \-\-all | \-\-epb | \-\-hwp-epp | \-\-hwp-min | \-\-hwp-max | \-\-hwp-desired"
16 .RB "other: (\-\-force | \-\-hwp-enable | \-\-turbo-enable) value)"
18 .RB "soc-slider: --soc-slider-balance # | --soc-slider-offset # | --platform-profile <name>"
20 .RB "value: # | default | performance | balance-performance | balance-power | power"
23 displays and updates energy-performance policy settings specific to
26 and also decodes underlying Model Specific Register (MSRs).
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| /linux/Documentation/arch/arm64/ |
| H A D | acpi_object_usage.rst | 16 - Required: DSDT, FADT, GTDT, MADT, MCFG, RSDP, SPCR, XSDT
18 - Recommended: BERT, EINJ, ERST, HEST, PCCT, SSDT
20 - Optional: AGDI, BGRT, CEDT, CPEP, CSRT, DBG2, DRTM, ECDT, FACS, FPDT,
24 - Not supported: AEST, APMT, BOOT, DBGP, DMAR, ETDT, HPET, IVRS, LPIT,
41 This table describes a non-maskable event, that is used by the platform
68 Optional, not currently supported, with no real use-case for an
83 time as ARM-compatible hardware is available, and the specification
151 UEFI-based; if it is UEFI-based, this table may be supplied. When this
167 the hardware reduced profile, and only 64-bit address fields will
184 filled in properly - that the PSCI_COMPLIANT flag is set and that
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| /linux/Documentation/arch/powerpc/ |
| H A D | vas-api.rst | 1 .. SPDX-License-Identifier: GPL-2.0
2 .. _VAS-API:
11 Power9 processor introduced Virtual Accelerator Switchboard (VAS) which
12 allows both userspace and kernel communicate to co-processor
14 unit comprises of one or more hardware engines or co-processor types
21 Requests to the GZIP engine must be formatted as a co-processo
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| /linux/tools/perf/Documentation/ |
| H A D | perf-list.txt | 1 perf-list(1)
5 ----
6 perf-list - List all symbolic event types
9 --------
15 -----------
17 various perf commands with the -e option.
20 -------
21 -d::
22 --desc::
25 --no-desc::
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| /linux/arch/arm/mach-mmp/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
10 Support for Marvell's PXA168/PXA910(MMP), MMP2, and MMP3 processor lines.
56 with Marvell MMP3 processor, also known as PXA2128 or
65 Select code specific to PXA168
71 Select code specific to PXA910
77 Select code specific to MMP2. MMP2 is ARMv7 compatible.
|
| /linux/drivers/remoteproc/ |
| H A D | remoteproc_core.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Remote Processor Framework
8 * Ohad Ben-Cohen <ohad@wizery.com>
12 * Suman Anna <s-anna@ti.com>
22 #include <linux/dma-mapping.h>
78 * IOMMU core will invoke this handler whenever the remote processor
94 return -ENOSY in rproc_iommu_fault()
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| /linux/arch/powerpc/include/asm/ |
| H A D | paca.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * This control block defines the PACA which defines the processor
4 * specific data for each logical processor on the system.
21 #include <asm/exception-64e.h>
23 #include <asm/exception-64s.h>
34 #include <asm-generic/mmiowb_types.h>
49 #define get_slb_shadow() (get_paca()->slb_shadow_ptr)
59 * processor.
66 * read-only (after boot) fields in the first cacheline to
81 u16 paca_index; /* Logical processor number */
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| /linux/Documentation/arch/x86/ |
| H A D | intel-hfi.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Hardware-Feedback Interface for scheduling on Intel Hardware
8 --------
11 IA-32 Architectures Software Developer's Manual (Intel SDM) Volume 3 Section
19 -------------------------------
23 capability is given as a unit-less quantity in the range [0-255]. Higher values
30 at which these capabilities are updated is specific to each processor model. On
35 excessive heat, the HFI may reflect reduced performance on specific CPUs.
39 capabilities of a given logical processor becomes zero, it is an indication that
41 that processor for performance or energy efficiency reasons, respectively.
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| /linux/Documentation/firmware-guide/acpi/ |
| H A D | chromeos-acpi-device.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 Hardware functionality specific to Chrome OS is exposed through a Chrome OS ACPI device.
11 .. flat-table:: Supported ACPI Objects
13 :header-rows: 1
15 * - Object
16 - Description
18 * - CHSW
19 - Chrome OS switch positions
21 * - HWID
22 - Chrome OS hardware ID
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| /linux/Documentation/devicetree/bindings/remoteproc/ |
| H A D | ti,davinci-rproc.txt | 4 The TI Davinci family of SoCs usually contains a TI DSP Core sub-system that
5 is used to offload some of the processor-intensive tasks or algorithms, for
8 The processor cores in the sub-system usually contain additional sub-modules
10 controller, a dedicated local power/sleep controller etc. The DSP processor
15 Each DSP Core sub-system is represented as a single DT node.
18 --------------------
21 - compatible: Should be one of the following,
22 "ti,da850-dsp" for DSPs on OMAP-L138 SoCs
24 - reg: Should contain an entry for each value in 'reg-names'.
27 the parent node's '#address-cells' and '#size-cells' values.
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| H A D | ti,k3-m4f-rproc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-m4f-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI K3 M4F processor subsystems
10 - Hari Nagalla <hnagalla@ti.com>
11 - Mathieu Poirier <mathieu.poirier@linaro.org>
17 home automation applications, may use the M4F core as a remote processor
20 $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
25 - ti,am64-m4fss
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| /linux/Documentation/devicetree/bindings/arm/keystone/ |
| H A D | ti,k3-sci-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/keystone/ti,k3-sci-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Common K3 TI-SCI
10 - Nishanth Menon <nm@ti.com>
13 The TI K3 family of SoCs usually have a central System Controller Processor
14 that is responsible for managing various SoC-level resources like clocks,
15 resets, interrupts etc. The communication with that processor is performed
16 through the TI-SCI protocol.
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| /linux/arch/sparc/include/asm/ |
| H A D | bbc.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * bbc.h: Defines for BootBus Controller found on UltraSPARC-III
12 /* Register sizes are indicated by "B" (Byte, 1-byte),
13 * "H" (Half-word, 2 bytes), "W" (Word, 4 bytes) or
29 #define BBC_ES_DACT 0x14 /* [B] E* De-Assert Change Time */
30 #define BBC_ES_DABT 0x15 /* [B] E* De-Assert Bypass Time */
38 #define BBC_I2C_0_S1 0x2e /* [B] I2C ctrlr-0 reg S1 */
39 #define BBC_I2C_0_S0 0x2f /* [B] I2C ctrlr-0 regs S0,S0',S2,S3*/
40 #define BBC_I2C_1_S1 0x30 /* [B] I2C ctrlr-1 reg S1 */
41 #define BBC_I2C_1_S0 0x31 /* [B] I2C ctrlr-1 regs S0,S0',S2,S3*/
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| /linux/Documentation/hwmon/ |
| H A D | fam15h_power.rst | 16 - BIOS and Kernel Developer's Guide (BKDG) For AMD Family 15h Processors
17 - BIOS and Kernel Developer's Guide (BKDG) For AMD Family 16h Processors
18 - AMD64 Architecture Programmer's Manual Volume 2: System Programming
23 -----------
25 1) Processor TDP (Thermal design power)
28 processor varies based on the workload being executed. Derated power
29 is the power consumed when running a specific application. Thermal
36 be calculated using different processor northbridge function
41 consumed by the processor for NB and logic external to the core.
45 the processor can support.
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| /linux/Documentation/virt/hyperv/ |
| H A D | coco.rst | 1 .. SPDX-License-Identifier: GPL-2.0
5 Hyper-V can create and run Linux guests that are Confidential Computing
6 (CoCo) VMs. Such VMs cooperate with the physical processor to better protect
9 CoCo VMs on Hyper-V share the generic CoCo VM threat model and security
10 objectives described in Documentation/security/snp-tdx-threat-model.rst. Note
11 that Hyper-V specific code in Linux refers to CoCo VMs as "isolated VMs" or
14 A Linux CoCo VM on Hyper-V requires the cooperation and interaction of the
17 * Physical hardware with a processor that supports CoCo VMs
19 * The hardware runs a version of Windows/Hyper-V with support for CoCo VMs
25 * AMD processor with SEV-SNP. Hyper-V does not run guest VMs with AMD SME,
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| /linux/arch/xtensa/include/asm/ |
| H A D | dma.h | 2 * include/asm-xtensa/dma.h
8 * Copyright (C) 2003 - 2005 Tensilica Inc.
17 * This is only to be defined if we have PC-like DMA.
18 * By default this is not true on an Xtensa processor,
31 * NOTE: This is board (platform) specific, not processor-specific!
48 #define MAX_DMA_ADDRESS (PAGE_OFFSET + XCHAL_KIO_SIZE - 1)
|