xref: /linux/Documentation/devicetree/bindings/remoteproc/ti,davinci-rproc.txt (revision 9b61b2069681b60d0d0bedbd0fe3c70123dddb19) 
1TI Davinci DSP devices
2=======================
3
4The TI Davinci family of SoCs usually contains a TI DSP Core sub-system that
5is used to offload some of the processor-intensive tasks or algorithms, for
6achieving various system level goals.
7
8The processor cores in the sub-system usually contain additional sub-modules
9like L1 and/or L2 caches/SRAMs, an Interrupt Controller, an external memory
10controller, a dedicated local power/sleep controller etc. The DSP processor
11core used in Davinci SoCs is usually a C674x DSP CPU.
12
13DSP Device Node:
14================
15Each DSP Core sub-system is represented as a single DT node.
16
17Required properties:
18--------------------
19The following are the mandatory properties:
20
21- compatible:		Should be one of the following,
22			    "ti,da850-dsp" for DSPs on OMAP-L138 SoCs
23
24- reg:			Should contain an entry for each value in 'reg-names'.
25			Each entry should have the memory region's start address
26			and the size of the region, the representation matching
27			the parent node's '#address-cells' and '#size-cells' values.
28
29- reg-names:		Should contain strings with the following names, each
30			representing a specific internal memory region or a
31			specific register space,
32			     "l2sram", "l1pram", "l1dram", "host1cfg", "chipsig_base"
33
34- interrupts: 		Should contain the interrupt number used to receive the
35			interrupts from the DSP. The value should follow the
36			interrupt-specifier format as dictated by the
37			'interrupt-parent' node.
38
39- memory-region:	phandle to the reserved memory node to be associated
40			with the remoteproc device. The reserved memory node
41			can be a CMA memory node, and should be defined as
42			per the bindings in
43			Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
44
45
46Example:
47--------
48
49	/* DSP Reserved Memory node */
50	reserved-memory {
51		#address-cells = <1>;
52		#size-cells = <1>;
53		ranges;
54
55		dsp_memory_region: dsp-memory@c3000000 {
56			compatible = "shared-dma-pool";
57			reg = <0xc3000000 0x1000000>;
58			reusable;
59		};
60	};
61
62	/* DSP node */
63	{
64		dsp: dsp@11800000 {
65			compatible = "ti,da850-dsp";
66			reg = <0x11800000 0x40000>,
67			      <0x11e00000 0x8000>,
68			      <0x11f00000 0x8000>,
69			      <0x01c14044 0x4>,
70			      <0x01c14174 0x8>;
71			reg-names = "l2sram", "l1pram", "l1dram", "host1cfg",
72				    "chipsig";
73			interrupt-parent = <&intc>;
74			interrupts = <28>;
75			memory-region = <&dsp_memory_region>;
76		};
77	};
78