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/linux/Documentation/ABI/testing/
H A Dsysfs-ptp41 Write integer to re-configure it.
93 and the channel number. The function and channel
103 "1" means that the PPS is supported, while "0" means
110 This write-only file enables or disables external
112 channel index followed by a "1" into the file.
113 To disable external timestamps, write the channel
121 the form of three integers: channel index, seconds,
128 This write-only file enables or disables periodic
130 integers into the file: channel index, start time
139 This write-only file enables or disables delivery of
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/linux/drivers/net/ethernet/freescale/
H A Dfec_ptp.c1 // SPDX-License-Identifier: GPL-2.0
92 * fec_ptp_read - read raw cycle counter (to be used by time counter)
105 tempval = readl(fep->hwp + FEC_ATIME_CTRL); in fec_ptp_read()
107 writel(tempval, fep->hwp + FEC_ATIME_CTRL); in fec_ptp_read()
109 if (fep->quirks & FEC_QUIRK_BUG_CAPTURE) in fec_ptp_read()
112 return readl(fep->hwp + FEC_ATIME); in fec_ptp_read()
118 * @enable: enable the channel pps output
120 * This function enables the PPS output on the timer channel.
129 spin_lock_irqsave(&fep->tmreg_lock, flags); in fec_ptp_enable_pps()
131 if (fep->pps_enable == enable) { in fec_ptp_enable_pps()
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/linux/tools/testing/selftests/ptp/
H A Dtestptp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * PTP 1588 clock support - User space test program
35 #define CLOCK_INVALID -1
113 return t->sec * NSEC_PER_SEC + t->nsec; in pctns()
120 " -c query the ptp clock's capabilities\n" in usage()
121 " -d name device to open\n" in usage()
122 " -e val read 'val' external time stamp events\n" in usage()
123 " -E val enable rising (1), falling (2), or both (3) edges\n" in usage()
124 " -f val adjust the ptp clock frequency by 'val' ppb\n" in usage()
125 " -F chan Enable single channel mask and keep device open for debugfs verification.\n" in usage()
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/linux/Documentation/devicetree/bindings/dpll/
H A Ddpll-device.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dpll/dpll-device.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Digital Phase-Locked Loop (DPLL) Device
10 - Ivan Vecera <ivecera@redhat.com>
13 Digital Phase-Locked Loop (DPLL) device is used for precise clock
16 output pins. Each DPLL channel can either produce pulse-per-clock signal
17 or drive ethernet equipment clock. The type of each channel can be
18 indicated by dpll-types property.
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/linux/include/uapi/linux/
H A Dptp_clock.h1 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
3 * PTP 1588 clock support - user space interface
83 * struct ptp_clock_time - represents a time value
87 * included for sub-nanosecond resolution, should the demand for
102 int pps; /* Whether the clock supports a PPS callbac member
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/linux/drivers/net/ethernet/sfc/
H A Dptp.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright 2011-2013 Solarflare Communications Inc.
116 /* 01-1B-19-00-00-00 */
142 #define MC_NANOSECOND_MASK ((1 << MC_NANOSECOND_BITS) - 1)
143 #define MC_SECOND_MASK ((1 << (32 - MC_NANOSECOND_BITS)) - 1)
145 /* Maximum parts-per-billion adjustment that is acceptable */
160 * struct efx_ptp_match - Matching structure, stored in sk_buff's cb area.
163 * @state: The state of the packet - whether it is ready for processing or
172 * struct efx_ptp_event_rx - A PTP receive event (from MC)
188 * struct efx_ptp_timeset - Synchronisation between host and MC
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/linux/drivers/net/ethernet/sfc/siena/
H A Dptp.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright 2011-2013 Solarflare Communications Inc.
143 #define MC_NANOSECOND_MASK ((1 << MC_NANOSECOND_BITS) - 1)
144 #define MC_SECOND_MASK ((1 << (32 - MC_NANOSECOND_BITS)) - 1)
146 /* Maximum parts-per-billion adjustment that is acceptable */
161 * struct efx_ptp_match - Matching structure, stored in sk_buff's cb area.
165 * @state: The state of the packet - whether it is ready for processing or
175 * struct efx_ptp_event_rx - A PTP receive event (from MC)
191 * struct efx_ptp_timeset - Synchronisation between host and MC
207 u32 window; /* Derived: end - start, allowing for wrap */
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/linux/drivers/net/ethernet/synopsys/
H A Ddwc-xlgmac-common.c5 * This program is dual-licensed; you may select either version 2 of
21 #include "dwc-xlgmac.h"
22 #include "dwc-xlgmac-reg.h"
24 static int debug = -1;
34 struct net_device *netdev = pdata->netdev; in xlgmac_read_mac_addr()
37 memcpy(pdata->mac_addr, dev_addr, netdev->addr_len); in xlgmac_read_mac_addr()
42 pdata->tx_osp_mode = DMA_OSP_ENABLE; in xlgmac_default_config()
43 pdata->tx_sf_mode = MTL_TSF_ENABLE; in xlgmac_default_config()
44 pdata->rx_sf_mode = MTL_RSF_DISABLE; in xlgmac_default_config()
45 pdata->pblx8 = DMA_PBL_X8_ENABLE; in xlgmac_default_config()
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H A Ddwc-xlgmac.h5 * This program is dual-licensed; you may select either version 2 of
21 #include <linux/dma-mapping.h>
29 #define XLGMAC_DRV_NAME "dwc-xlgmac"
47 #define XLGMAC_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1))
97 ((_ring)->desc_data_head + \
98 ((idx) & ((_ring)->dma_desc_count - 1))); \
104 ((var) & GENMASK(_pos + _len - 1, _pos)) >> (_pos); \
111 ((_var) & GENMASK(_pos + _len - 1, _pos)) >> (_pos); \
119 _val = (_val << _pos) & GENMASK(_pos + _len - 1, _pos); \
120 _var = (_var & ~GENMASK(_pos + _len - 1, _pos)) | _val; \
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/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mn-venice-gw7902.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/net/ti-dp83867.h>
17 compatible = "gw,imx8mn-gw7902", "fsl,imx8mn";
26 stdout-path = &uart2;
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
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H A Dimx8mm-venice-gw7902.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/net/ti-dp83867.h>
12 #include <dt-bindings/phy/phy-imx8-pcie.h>
18 compatible = "gw,imx8mm-gw7902", "fsl,imx8mm";
29 stdout-path = &uart2;
38 compatible = "fixed-clock";
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H A Dimx8mp-venice-gw74xx.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy-imx8-pcie.h>
12 #include <dt-bindings/net/ti-dp83867.h>
18 compatible = "gateworks,imx8mp-gw74xx", "fsl,imx8mp";
33 stdout-path = &uart2;
42 pinctrl-names = "default";
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/linux/sound/usb/
H A Dcard.h1 /* SPDX-License-Identifier: GPL-2.0 */
16 unsigned int fmt_type; /* USB audio format type (1-3) */
19 unsigned int frame_size; /* samples per frame for non-audio */
40 struct snd_pcm_chmap_elem *chmap; /* (optional) channel map */
69 int opened; /* open refcount; protect with chip->mutex */
109 unsigned int sample_rem; /* remainder from division fs/pps */
111 unsigned int pps; /* packets per second */ member
132 bool lowlatency_playback; /* low-latency playback mode */
133 bool need_setup; /* (re-)need for hw_params? */
134 bool need_prepare; /* (re-)need for prepare? */
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/linux/sound/core/oss/
H A Dmulaw.c2 * Mu-Law conversion Plug-In Interface
4 * Uros Bizjak <uros@kss-loka.si>
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29 #define SIGN_BIT (0x80) /* Sign bit for a u-law byte. */
31 #define NSEGS (8) /* Number of u-law segments. */
55 * linear2ulaw() - Convert a linear PCM value to u-law
58 * is biased by adding 33 which shifts the encoding range from (0 - 8158) to
59 * (33 - 8191). The result can be seen in the following encoding table:
62 * ------------------------ ---------------
75 * four bits wxyz. * The trailing bits (a - h) are ignored.
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/linux/drivers/dpll/zl3073x/
H A Dprop.c1 // SPDX-License-Identifier: GPL-2.0-only
16 * zl3073x_pin_check_freq - verify frequency for given pin
62 dev_warn(zldev->dev, in zl3073x_pin_check_freq()
69 * zl3073x_prop_pin_package_label_set - get package label for the pin
78 * REF<n> - differential input reference
79 * REF<n>P & REF<n>N - single-ended input reference (P or N pin)
80 * OUT<n> - differential output
81 * OUT<n>P & OUT<n>N - single-ended output (P or N pin)
110 snprintf(props->package_label, sizeof(props->package_label), "%s%u%s", in zl3073x_prop_pin_package_label_set()
116 props->dpll_props.package_label = props->package_label; in zl3073x_prop_pin_package_label_set()
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/linux/drivers/iio/imu/
H A Dadis16480.c1 // SPDX-License-Identifier: GPL-2.0-only
102 * External clock scaling in PPS mode.
116 ADIS16480_REG((page) + 1, (x) - 60 + 8))
194 … "Allow IMU rates below the minimum advisable when external clk is used in PPS mode (default: N)");
199 struct adis16480 *adis16480 = file->private_data; in adis16480_show_firmware_revision()
205 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_REV, &rev); in adis16480_show_firmware_revision()
224 struct adis16480 *adis16480 = file->private_data; in adis16480_show_firmware_date()
230 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_Y, &year); in adis16480_show_firmware_date()
234 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_DM, &md); in adis16480_show_firmware_date()
238 len = snprintf(buf, sizeof(buf), "%.2x-%.2x-%.4x\n", in adis16480_show_firmware_date()
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/linux/drivers/net/wireless/marvell/mwifiex/
H A Duap_event.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2011-2020 NXP
24 priv->wmm_enabled = false; in mwifiex_check_uap_capabilities()
26 evt_len = event->len; in mwifiex_check_uap_capabilities()
27 curr = event->data; in mwifiex_check_uap_capabilities()
29 mwifiex_dbg_dump(priv->adapter, EVT_D, "uap capabilities:", in mwifiex_check_uap_capabilities()
30 event->data, event->len); in mwifiex_check_uap_capabilities()
34 while ((evt_len >= sizeof(tlv_hdr->header))) { in mwifiex_check_uap_capabilities()
36 tlv_len = le16_to_cpu(tlv_hdr->header.len); in mwifiex_check_uap_capabilities()
38 if (evt_len < tlv_len + sizeof(tlv_hdr->header)) in mwifiex_check_uap_capabilities()
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/linux/include/linux/mfd/
H A Didt8a340_reg.h1 /* SPDX-License-Identifier: GPL-2.0+ */
230 /* Signed 42-bit FFO in units of 2^(-53) */
241 /* Signed 42-bit FFO in units of 2^(-53) */
380 /* Enable TOD counter, output channel sync and even-PPS mode */
392 /* 8-bit subns, 32-bit ns, 48-bit seconds */
409 /* 8-bit subns, 32-bit ns, 48-bit seconds */
427 /* 8-bit subns, 32-bit ns, 48-bit seconds */
719 /* CANCEL CURRENT TOD READ; MODULE BECOMES IDLE - NO TRIGGER OCCURS */
723 /* TRIGGER ON RISING EDGE OF INTERNAL TOD PPS SIGNAL */
727 /* TRIGGER ON RISING EDGE OF SELECTED PWM DECODER 1PPS OUTPUT */
/linux/drivers/net/ethernet/marvell/octeontx2/nic/
H A Dotx2_tc.c1 // SPDX-License-Identifier: GPL-2.0
32 #define MCAST_INVALID_GRP (-1U)
64 if (is_dev_otx2(nic->pdev)) { in otx2_get_egress_burst_cfg()
78 *burst_exp = ilog2(burst) ? ilog2(burst) - 1 : 0; in otx2_get_egress_burst_cfg()
79 tmp = burst - rounddown_pow_of_two(burst); in otx2_get_egress_burst_cfg()
83 *burst_mantissa = tmp / (1ULL << (*burst_exp - 7)); in otx2_get_egress_burst_cfg()
109 *exp = ilog2(maxrate) ? ilog2(maxrate) - 1 : 0; in otx2_get_egress_rate_cfg()
110 tmp = maxrate - rounddown_pow_of_two(maxrate); in otx2_get_egress_rate_cfg()
114 *mantissa = tmp / (1ULL << (*exp - 7)); in otx2_get_egress_rate_cfg()
133 if (is_dev_otx2(nic->pdev)) { in otx2_get_txschq_rate_regval()
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/linux/drivers/net/ethernet/intel/i40e/
H A Di40e_ptp.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
5 #include <linux/posix-clock.h>
39 CANT_DO_PINS = -1,
52 end = -2,
66 led_end = -2,
145 * i40e_ptp_extts0_work - workqueue task function
154 struct i40e_hw *hw = &pf->hw; in i40e_ptp_extts0_work()
169 event.index = hw->pf_id; in i40e_ptp_extts0_work()
172 ptp_clock_event(pf->ptp_clock, &event); in i40e_ptp_extts0_work()
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/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A Ddsi.c1 // SPDX-License-Identifier: GPL-2.0-only
140 /* Virtual channel interrupts */
211 static int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel);
408 return to_platform_device(dssdev->dev); in dsi_get_dsidev_from_dssdev()
429 return out ? to_platform_device(out->dev) : NULL; in dsi_get_dsidev_from_id()
439 case DSI_PROTO: base = dsi->proto_base; break; in dsi_write_reg()
440 case DSI_PHY: base = dsi->phy_base; break; in dsi_write_reg()
441 case DSI_PLL: base = dsi->pll_base; break; in dsi_write_reg()
455 case DSI_PROTO: base = dsi->proto_base; break; in dsi_read_reg()
456 case DSI_PHY: base = dsi->phy_base; break; in dsi_read_reg()
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/linux/drivers/ptp/
H A Dptp_ocp.c1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <linux/clk-provider.h>
15 #include <linux/platform_data/i2c-xiic.h>
16 #include <linux/platform_data/i2c-ocores.h>
24 #include <linux/nvmem-consumer.h>
349 struct ptp_ocp_ext_src *pps; member
441 (void *)((uintptr_t)(bp) + (map)->bp_offset); \
457 uintptr_t addr = (uintptr_t)(bp) + (res)->bp_offset; \
480 * 0: PPS (TS5)
497 --
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/linux/drivers/media/platform/samsung/s5p-mfc/
H A Dregs-mfc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
15 #define S5P_FIMV_REG_SIZE (S5P_FIMV_END_ADDR - S5P_FIMV_START_ADDR)
16 #define S5P_FIMV_REG_COUNT ((S5P_FIMV_END_ADDR - S5P_FIMV_START_ADDR) / 4)
84 /* VC-1 decoding */
157 /* Channel & stream interface register */
309 #define S5P_FIMV_ENC_H264_TRANS_FLAG 0xd034 /* 8x8 transform flag in PPS &
333 #define S5P_FIMV_CODEC_NONE -1
346 /* Channel Control Register */
383 #define S5P_FIMV_CODEC_H264_MVC_DEC -1
384 #define S5P_FIMV_R2H_CMD_FIELD_DONE_RET -1
[all …]
/linux/drivers/net/ethernet/amd/xgbe/
H A Dxgbe-drv.c1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
3 * Copyright (c) 2014-2025, Advanced Micro Devices, Inc.
20 #include "xgbe-common.h"
67 for (i = 0; i < ARRAY_SIZE(pdata->channel); i++) { in xgbe_free_channels()
68 if (!pdata->channel[i]) in xgbe_free_channels()
71 kfree(pdata->channel[i]->rx_ring); in xgbe_free_channels()
72 kfree(pdata->channel[i]->tx_ring); in xgbe_free_channels()
73 kfree(pdata->channel[i]); in xgbe_free_channels()
75 pdata->channel[i] = NULL; in xgbe_free_channels()
78 pdata->channel_count = 0; in xgbe_free_channels()
[all …]
/linux/drivers/net/ethernet/samsung/sxgbe/
H A Dsxgbe_reg.h1 /* SPDX-License-Identifier: GPL-2.0-only */
26 /* EEE-LPI Registers */
77 /* port specific, addr = 0-3 */
92 /* addr = 0-31 */
227 /* PPS registers */
231 /* addr = 0 - 3 */
259 /* TC/Queue registers, qnum=0-15 */
309 /* Channel Registers, cha_num = 0-15 */
470 /* DMA channel interrupt status specific */

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