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/linux/arch/arm/boot/dts/microchip/
H A Dat91sam9260.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91sam9260.dtsi - Device Tree Include file for AT91SAM9260 family SoC
7 * 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
10 #include <dt-bindings/pinctrl/at91.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/clock/at91.h>
14 #include <dt-bindings/mfd/at91-usart.h>
17 #address-cells = <1>;
18 #size-cells = <1>;
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H A Dat91sam9x5.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC
11 #include <dt-bindings/dma/at91.h>
12 #include <dt-bindings/pinctrl/at91.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/clock/at91.h>
16 #include <dt-bindings/mfd/at91-usart.h>
19 #address-cells = <1>;
20 #size-cells = <1>;
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H A Dat91sam9rl.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91sam9rl.dtsi - Device Tree Include file for AT91SAM9RL family SoC
6 * Alexandre Belloni <alexandre.belloni@free-electrons.com>
9 #include <dt-bindings/pinctrl/at91.h>
10 #include <dt-bindings/clock/at91.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/pwm/pwm.h>
14 #include <dt-bindings/mfd/at91-usart.h>
17 #address-cells = <1>;
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H A Dat91sam9g20.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * at91sam9g20.dtsi - Device Tree Include file for AT91SAM9G20 family SoC
5 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
23 compatible = "mmio-sram";
25 #address-cells = <1>;
26 #size-cells = <1>;
33 compatible = "atmel,at91sam9g20-i2c";
37 compatible = "atmel,at91sam9rl-ssc";
40 adc0: adc@fffe0000 {
41 atmel,adc-startup-time = <40>;
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H A Dsama7g5.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * sama7g5.dtsi - Device Tree Include file for SAMA7G5 family SoC
12 #include <dt-bindings/iio/adc/at91-sama5d2_adc.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/clock/at91.h>
16 #include <dt-bindings/dma/at91.h>
17 #include <dt-bindings/gpio/gpio.h>
18 #include <dt-bindings/mfd/at91-usart.h>
19 #include <dt-bindings/nvmem/microchip,sama7g5-otpc.h>
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H A Dsama5d3.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC
10 #include <dt-bindings/dma/at91.h>
11 #include <dt-bindings/pinctrl/at91.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/clock/at91.h>
15 #include <dt-bindings/mfd/at91-usart.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
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H A Dsama5d4.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * sama5d4.dtsi - Device Tree Include file for SAMA5D4 family SoC
9 #include <dt-bindings/clock/at91.h>
10 #include <dt-bindings/dma/at91.h>
11 #include <dt-bindings/mfd/at91-usart.h>
12 #include <dt-bindings/pinctrl/at91.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/gpio/gpio.h>
17 #address-cells = <1>;
18 #size-cells = <1>;
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H A Dat91sam9g45.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC
11 #include <dt-bindings/dma/at91.h>
12 #include <dt-bindings/pinctrl/at91.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/clock/at91.h>
16 #include <dt-bindings/mfd/at91-usart.h>
19 #address-cells = <1>;
20 #size-cells = <1>;
[all …]
H A Dsama5d3xmb.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * sama5d3xmb.dts - Device Tree file for SAMA5D3x mother board
16 pinctrl-names = "default";
17 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>;
21 bus-width = <4>;
22 cd-gpios = <&pioD 17 GPIO_ACTIVE_HIGH>;
31 spi-max-frequency = <50000000>;
37 atmel,clk-from-rk-pin;
49 clocks = <&pmc PMC_TYPE_SYSTEM 8>;
50 clock-names = "mclk";
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H A Dsama5d3xmb_cmp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * sama5d3xmb_cmp.dts - Device Tree file for SAMA5D3x CMP mother board
10 compatible = "atmel,sama5d3xmb-cmp", "atmel,sama5d3xcm-cmp", "atmel,sama5d3", "atmel,sama5";
15 pinctrl-names = "default";
16 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>;
20 bus-width = <4>;
21 cd-gpios = <&pioD 17 GPIO_ACTIVE_HIGH>;
30 spi-max-frequency = <50000000>;
36 atmel,clk-from-rk-pin;
48 clocks = <&pmc PMC_TYPE_SYSTEM 8>;
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H A Dat91-sama5d4ek.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * at91-sama5d4ek.dts - Device Tree file for SAMA5D4 Evaluation Kit
8 /dts-v1/;
12 model = "Atmel SAMA5D4-EK";
16 stdout-path = "serial0:115200n8";
25 clock-frequency = <32768>;
29 clock-frequency = <12000000>;
35 adc0: adc@fc034000 {
36 pinctrl-names = "default";
37 pinctrl-0 = <
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H A Dat91sam9m10g45ek.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91sam9m10g45ek.dts - Device Tree file for AT91SAM9M10G45-EK board
8 /dts-v1/;
10 #include <dt-bindings/pwm/pwm.h>
13 model = "Atmel AT91SAM9M10G45-EK";
18 stdout-path = "serial0:115200n8";
27 clock-frequency = <32768>;
31 clock-frequency = <12000000>;
43 compatible = "atmel,tcb-timer";
48 compatible = "atmel,tcb-timer";
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/linux/drivers/iio/adc/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # ADC drivers
10 bool "ST-Ericsson AB8500 GPADC driver"
25 tristate "Analog Devices AD4000 ADC Driver"
31 SPI analog to digital converters (ADC).
37 tristate "Analog Device AD4130 ADC Driver"
45 Say yes here to build support for Analog Devices AD4130-8 SPI analog
46 to digital converters (ADC).
52 tristate "Analog Device AD4695 ADC Driver"
59 analog to digital converters (ADC).
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/linux/arch/arm/boot/dts/nvidia/
H A Dtegra30-colibri.dtsi1 // SPDX-License-Identifier: GPL-2.0
15 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
16 nvidia,hpd-gpio =
18 pll-supply = <&reg_1v8_avdd_hdmi_pll>;
19 vdd-supply = <&reg_3v3_avdd_hdmi>;
24 lan-reset-n-hog {
25 gpio-hog;
27 output-high;
28 line-name = "LAN_RESET#";
33 pinctrl-names = "default";
[all …]
H A Dtegra30-apalis-v1.1.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
16 avdd-pexa-supply = <&vdd2_reg>;
17 avdd-pexb-supply = <&vdd2_reg>;
18 avdd-pex-pll-supply = <&vdd2_reg>;
19 avdd-plle-supply = <&ldo6_reg>;
20 hvdd-pex-supply = <&reg_module_3v3>;
21 vddio-pex-ctl-supply = <&reg_module_3v3>;
22 vdd-pexa-supply = <&vdd2_reg>;
23 vdd-pexb-supply = <&vdd2_reg>;
27 nvidia,num-lanes = <4>;
[all …]
H A Dtegra30-apalis.dtsi1 // SPDX-License-Identifier: GPL-2.0
15 avdd-pexa-supply = <&vdd2_reg>;
16 avdd-pexb-supply = <&vdd2_reg>;
17 avdd-pex-pll-supply = <&vdd2_reg>;
18 avdd-plle-supply = <&ldo6_reg>;
19 hvdd-pex-supply = <&reg_module_3v3>;
20 vddio-pex-ctl-supply = <&reg_module_3v3>;
21 vdd-pexa-supply = <&vdd2_reg>;
22 vdd-pexb-supply = <&vdd2_reg>;
26 nvidia,num-lanes = <4>;
[all …]
H A Dtegra114-asus-tf701t.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include <dt-bindings/input/gpio-keys.h>
6 #include <dt-bindings/input/input.h>
13 chassis-type = "convertible";
29 trusted-foundations {
30 compatible = "tlm,trusted-foundations";
31 tlm,version-major = <2>;
32 tlm,version-minor = <8>;
40 reserved-memory {
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/linux/
H A DMAINTAINERS5 ----------
[all...]
H A DCREDITS1 This is at least a partial credits-file of people that have
4 scripts. The fields are: name (N), email (E), web-address
6 snail-mail address (S).
10 -------
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/linux/Documentation/admin-guide/media/
H A Dbttv.rst1 .. SPDX-License-Identifier: GPL-2.0
8 ----------------------
12 ./scripts/config -e PCI
13 ./scripts/config -m I2C
14 ./scripts/config -m INPUT
15 ./scripts/config -m MEDIA_SUPPORT
16 ./scripts/config -e MEDIA_PCI_SUPPORT
17 ./scripts/config -e MEDIA_ANALOG_TV_SUPPORT
18 ./scripts/config -e MEDIA_DIGITAL_TV_SUPPORT
19 ./scripts/config -e MEDIA_RADIO_SUPPORT
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/linux/drivers/net/ethernet/intel/e1000e/
H A Dphy.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
37 * e1000e_check_reset_block_generic - Check if PHY reset is blocked
54 * e1000e_get_phy_id - Retrieve the PHY ID and revision
62 struct e1000_phy_info *phy = &hw->phy; in e1000e_get_phy_id()
67 if (!phy->ops.read_reg) in e1000e_get_phy_id()
75 phy->id = (u32)(phy_id << 16); in e1000e_get_phy_id()
81 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); in e1000e_get_phy_id()
82 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); in e1000e_get_phy_id()
84 if (phy->id != 0 && phy->id != PHY_REVISION_MASK) in e1000e_get_phy_id()
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