1724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0 2724ba675SRob Herring 3724ba675SRob Herring/dts-v1/; 4724ba675SRob Herring 5724ba675SRob Herring#include <dt-bindings/input/gpio-keys.h> 6724ba675SRob Herring#include <dt-bindings/input/input.h> 7724ba675SRob Herring 8724ba675SRob Herring#include "tegra114.dtsi" 9724ba675SRob Herring 10724ba675SRob Herring/ { 11724ba675SRob Herring model = "Asus Transformer Pad TF701T"; 12724ba675SRob Herring compatible = "asus,tf701t", "nvidia,tegra114"; 13724ba675SRob Herring chassis-type = "convertible"; 14724ba675SRob Herring 15724ba675SRob Herring aliases { 16724ba675SRob Herring mmc0 = "/mmc@78000600"; /* eMMC */ 17724ba675SRob Herring mmc1 = "/mmc@78000400"; /* uSD slot */ 18724ba675SRob Herring mmc2 = "/mmc@78000000"; /* WiFi */ 19724ba675SRob Herring 20724ba675SRob Herring rtc0 = &palmas; 21724ba675SRob Herring rtc1 = "/rtc@7000e000"; 22724ba675SRob Herring 23724ba675SRob Herring serial0 = &uartd; /* Console */ 24724ba675SRob Herring serial1 = &uartc; /* Bluetooth */ 25724ba675SRob Herring serial2 = &uartb; /* GPS */ 26724ba675SRob Herring }; 27724ba675SRob Herring 28724ba675SRob Herring firmware { 29724ba675SRob Herring trusted-foundations { 30724ba675SRob Herring compatible = "tlm,trusted-foundations"; 31724ba675SRob Herring tlm,version-major = <2>; 32724ba675SRob Herring tlm,version-minor = <8>; 33724ba675SRob Herring }; 34724ba675SRob Herring }; 35724ba675SRob Herring 36724ba675SRob Herring memory@80000000 { 37724ba675SRob Herring reg = <0x80000000 0x80000000>; 38724ba675SRob Herring }; 39724ba675SRob Herring 40724ba675SRob Herring reserved-memory { 41724ba675SRob Herring #address-cells = <1>; 42724ba675SRob Herring #size-cells = <1>; 43724ba675SRob Herring ranges; 44724ba675SRob Herring 45724ba675SRob Herring linux,cma@80000000 { 46724ba675SRob Herring compatible = "shared-dma-pool"; 47724ba675SRob Herring alloc-ranges = <0x80000000 0x30000000>; 48724ba675SRob Herring size = <0x10000000>; 49724ba675SRob Herring linux,cma-default; 50724ba675SRob Herring reusable; 51724ba675SRob Herring }; 52724ba675SRob Herring 53724ba675SRob Herring trustzone@bfe00000 { 54724ba675SRob Herring reg = <0xbfe00000 0x200000>; 55724ba675SRob Herring no-map; 56724ba675SRob Herring }; 57724ba675SRob Herring }; 58724ba675SRob Herring 59724ba675SRob Herring host1x@50000000 { 60fceb6acdSSvyatoslav Ryhel hdmi@54280000 { 61fceb6acdSSvyatoslav Ryhel status = "okay"; 62fceb6acdSSvyatoslav Ryhel 63fceb6acdSSvyatoslav Ryhel hdmi-supply = <&hdmi_5v0_sys>; 64fceb6acdSSvyatoslav Ryhel pll-supply = <&avdd_hdmi_pll>; 65fceb6acdSSvyatoslav Ryhel vdd-supply = <&avdd_hdmi>; 66fceb6acdSSvyatoslav Ryhel 67fceb6acdSSvyatoslav Ryhel port { 68fceb6acdSSvyatoslav Ryhel hdmi_out: endpoint { 69fceb6acdSSvyatoslav Ryhel remote-endpoint = <&connector_in>; 70fceb6acdSSvyatoslav Ryhel }; 71fceb6acdSSvyatoslav Ryhel }; 72fceb6acdSSvyatoslav Ryhel }; 73fceb6acdSSvyatoslav Ryhel 74724ba675SRob Herring dsi@54300000 { 75724ba675SRob Herring status = "okay"; 76724ba675SRob Herring 771f02c9fbSSvyatoslav Ryhel avdd-dsi-csi-supply = <&avdd_dsi_csi>; 78724ba675SRob Herring 79724ba675SRob Herring nvidia,ganged-mode = <&dsib>; 80724ba675SRob Herring 81724ba675SRob Herring panel_primary: panel@0 { 82724ba675SRob Herring compatible = "sharp,lq101r1sx01"; 83724ba675SRob Herring reg = <0>; 84724ba675SRob Herring 85724ba675SRob Herring link2 = <&panel_secondary>; 86724ba675SRob Herring 871f02c9fbSSvyatoslav Ryhel power-supply = <&dvdd_1v8_lcd>; 88724ba675SRob Herring backlight = <&backlight>; 89724ba675SRob Herring }; 90724ba675SRob Herring }; 91724ba675SRob Herring 92724ba675SRob Herring dsi@54400000 { 93724ba675SRob Herring status = "okay"; 94724ba675SRob Herring 951f02c9fbSSvyatoslav Ryhel avdd-dsi-csi-supply = <&avdd_dsi_csi>; 96724ba675SRob Herring 97724ba675SRob Herring panel_secondary: panel@0 { 98724ba675SRob Herring compatible = "sharp,lq101r1sx01"; 99724ba675SRob Herring reg = <0>; 100724ba675SRob Herring }; 101724ba675SRob Herring }; 102724ba675SRob Herring }; 103724ba675SRob Herring 104984d444aSSvyatoslav Ryhel vde@6001a000 { 105984d444aSSvyatoslav Ryhel assigned-clocks = <&tegra_car TEGRA114_CLK_VDE>; 106984d444aSSvyatoslav Ryhel assigned-clock-parents = <&tegra_car TEGRA114_CLK_PLL_P>; 107984d444aSSvyatoslav Ryhel assigned-clock-rates = <408000000>; 108984d444aSSvyatoslav Ryhel }; 109984d444aSSvyatoslav Ryhel 110724ba675SRob Herring pinmux@70000868 { 111b457e191SSvyatoslav Ryhel pinctrl-names = "default"; 112b457e191SSvyatoslav Ryhel pinctrl-0 = <&state_default>; 113b457e191SSvyatoslav Ryhel 114b457e191SSvyatoslav Ryhel state_default: pinmux { 115b457e191SSvyatoslav Ryhel /* WLAN SDIO pinmux */ 116b457e191SSvyatoslav Ryhel sdmmc1-clk { 117b457e191SSvyatoslav Ryhel nvidia,pins = "sdmmc1_clk_pz0"; 118b457e191SSvyatoslav Ryhel nvidia,function = "sdmmc1"; 119b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 120b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 121b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 122b457e191SSvyatoslav Ryhel }; 123b457e191SSvyatoslav Ryhel 124b457e191SSvyatoslav Ryhel sdmmc1-cmd { 125b457e191SSvyatoslav Ryhel nvidia,pins = "sdmmc1_cmd_pz1", 126b457e191SSvyatoslav Ryhel "sdmmc1_dat0_py7", 127b457e191SSvyatoslav Ryhel "sdmmc1_dat1_py6", 128b457e191SSvyatoslav Ryhel "sdmmc1_dat2_py5", 129b457e191SSvyatoslav Ryhel "sdmmc1_dat3_py4"; 130b457e191SSvyatoslav Ryhel nvidia,function = "sdmmc1"; 131724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 132724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 133724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 134724ba675SRob Herring }; 135724ba675SRob Herring 136b457e191SSvyatoslav Ryhel wlan-power { 137b457e191SSvyatoslav Ryhel nvidia,pins = "clk2_req_pcc5"; 138b457e191SSvyatoslav Ryhel nvidia,function = "rsvd2"; 139724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 140724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 141724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 142724ba675SRob Herring }; 143b457e191SSvyatoslav Ryhel 144b457e191SSvyatoslav Ryhel wlan-reset { 145b457e191SSvyatoslav Ryhel nvidia,pins = "gpio_x7_aud_px7"; 146b457e191SSvyatoslav Ryhel nvidia,function = "rsvd1"; 147b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 148b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 149b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 150724ba675SRob Herring }; 151724ba675SRob Herring 152b457e191SSvyatoslav Ryhel wlan-host-wake { 153b457e191SSvyatoslav Ryhel nvidia,pins = "pu5"; 154b457e191SSvyatoslav Ryhel nvidia,function = "pwm2"; 155b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 156b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 157b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 158b457e191SSvyatoslav Ryhel }; 159b457e191SSvyatoslav Ryhel 160b457e191SSvyatoslav Ryhel wlan-3v3-com { 161b457e191SSvyatoslav Ryhel nvidia,pins = "pu1"; 162b457e191SSvyatoslav Ryhel nvidia,function = "rsvd1"; 163b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 164b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 165b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 166b457e191SSvyatoslav Ryhel }; 167b457e191SSvyatoslav Ryhel 168b457e191SSvyatoslav Ryhel /* UART-A pinmux */ 169b457e191SSvyatoslav Ryhel uarta-cts { 170b457e191SSvyatoslav Ryhel nvidia,pins = "kb_row10_ps2"; 171b457e191SSvyatoslav Ryhel nvidia,function = "uarta"; 172b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 173b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 174b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 175b457e191SSvyatoslav Ryhel }; 176b457e191SSvyatoslav Ryhel 177b457e191SSvyatoslav Ryhel uarta-rts { 178b457e191SSvyatoslav Ryhel nvidia,pins = "kb_row9_ps1"; 179b457e191SSvyatoslav Ryhel nvidia,function = "uarta"; 180b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 181b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 182b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 183b457e191SSvyatoslav Ryhel }; 184b457e191SSvyatoslav Ryhel 185b457e191SSvyatoslav Ryhel /* GNSS UART-B pinmux */ 186b457e191SSvyatoslav Ryhel uartb-cts { 187b457e191SSvyatoslav Ryhel nvidia,pins = "uart2_cts_n_pj5"; 188b457e191SSvyatoslav Ryhel nvidia,function = "uartb"; 189b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 190b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 191b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 192b457e191SSvyatoslav Ryhel }; 193b457e191SSvyatoslav Ryhel 194b457e191SSvyatoslav Ryhel uartb-rts { 195b457e191SSvyatoslav Ryhel nvidia,pins = "uart2_rts_n_pj6"; 196b457e191SSvyatoslav Ryhel nvidia,function = "uartb"; 197b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 198b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 199b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 200b457e191SSvyatoslav Ryhel }; 201b457e191SSvyatoslav Ryhel 202b457e191SSvyatoslav Ryhel uartb-rxd { 203b457e191SSvyatoslav Ryhel nvidia,pins = "uart2_rxd_pc3"; 204b457e191SSvyatoslav Ryhel nvidia,function = "irda"; 205b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 206b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 207b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 208b457e191SSvyatoslav Ryhel }; 209b457e191SSvyatoslav Ryhel 210b457e191SSvyatoslav Ryhel uartb-txd { 211b457e191SSvyatoslav Ryhel nvidia,pins = "uart2_txd_pc2"; 212b457e191SSvyatoslav Ryhel nvidia,function = "irda"; 213b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 214b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 215b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 216b457e191SSvyatoslav Ryhel }; 217b457e191SSvyatoslav Ryhel 218b457e191SSvyatoslav Ryhel /* Bluetooth UART-C pinmux */ 219b457e191SSvyatoslav Ryhel uartc-cts-rxd { 220b457e191SSvyatoslav Ryhel nvidia,pins = "uart3_cts_n_pa1", 221b457e191SSvyatoslav Ryhel "uart3_rxd_pw7"; 222b457e191SSvyatoslav Ryhel nvidia,function = "uartc"; 223b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 224b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 225b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 226b457e191SSvyatoslav Ryhel }; 227b457e191SSvyatoslav Ryhel 228b457e191SSvyatoslav Ryhel uartc-rts-txd { 229b457e191SSvyatoslav Ryhel nvidia,pins = "uart3_rts_n_pc0", 230b457e191SSvyatoslav Ryhel "uart3_txd_pw6"; 231b457e191SSvyatoslav Ryhel nvidia,function = "uartc"; 232b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 233b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 234b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 235b457e191SSvyatoslav Ryhel }; 236b457e191SSvyatoslav Ryhel 237b457e191SSvyatoslav Ryhel bt-shutdown { 238b457e191SSvyatoslav Ryhel nvidia,pins = "kb_col6_pq6", 239b457e191SSvyatoslav Ryhel "kb_col7_pq7"; 240b457e191SSvyatoslav Ryhel nvidia,function = "rsvd2"; 241b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 242b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 243b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 244b457e191SSvyatoslav Ryhel }; 245b457e191SSvyatoslav Ryhel 246b457e191SSvyatoslav Ryhel bt-dev-wake { 247b457e191SSvyatoslav Ryhel nvidia,pins = "clk3_req_pee1"; 248b457e191SSvyatoslav Ryhel nvidia,function = "rsvd2"; 249b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 250b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 251b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 252b457e191SSvyatoslav Ryhel }; 253b457e191SSvyatoslav Ryhel 254b457e191SSvyatoslav Ryhel bt-host-wake { 255b457e191SSvyatoslav Ryhel nvidia,pins = "pu6"; 256b457e191SSvyatoslav Ryhel nvidia,function = "pwm3"; 257b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 258b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 259b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 260b457e191SSvyatoslav Ryhel }; 261b457e191SSvyatoslav Ryhel 262b457e191SSvyatoslav Ryhel bt-pcm-dap4-out { 263b457e191SSvyatoslav Ryhel nvidia,pins = "dap4_fs_pp4", 264b457e191SSvyatoslav Ryhel "dap4_dout_pp6", 265b457e191SSvyatoslav Ryhel "dap4_sclk_pp7"; 266b457e191SSvyatoslav Ryhel nvidia,function = "i2s3"; 267b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 268b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 269b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 270b457e191SSvyatoslav Ryhel }; 271b457e191SSvyatoslav Ryhel 272b457e191SSvyatoslav Ryhel bt-pcm-dap4-in { 273b457e191SSvyatoslav Ryhel nvidia,pins = "dap4_din_pp5"; 274b457e191SSvyatoslav Ryhel nvidia,function = "i2s3"; 275b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 276b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 277b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 278b457e191SSvyatoslav Ryhel }; 279b457e191SSvyatoslav Ryhel 280b457e191SSvyatoslav Ryhel /* UART-D pinmux */ 281b457e191SSvyatoslav Ryhel uartd-cts { 282b457e191SSvyatoslav Ryhel nvidia,pins = "gmi_a17_pb0"; 283b457e191SSvyatoslav Ryhel nvidia,function = "uartd"; 284b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 285b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 286b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 287b457e191SSvyatoslav Ryhel }; 288b457e191SSvyatoslav Ryhel 289b457e191SSvyatoslav Ryhel uartd-rts { 290b457e191SSvyatoslav Ryhel nvidia,pins = "gmi_a16_pj7", 291b457e191SSvyatoslav Ryhel "gmi_a19_pk7"; 292b457e191SSvyatoslav Ryhel nvidia,function = "uartd"; 293b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 294b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 295b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 296b457e191SSvyatoslav Ryhel }; 297b457e191SSvyatoslav Ryhel 298b457e191SSvyatoslav Ryhel /* MicroSD pinmux */ 299b457e191SSvyatoslav Ryhel sdmmc3-clk { 300b457e191SSvyatoslav Ryhel nvidia,pins = "sdmmc3_clk_pa6"; 301b457e191SSvyatoslav Ryhel nvidia,function = "sdmmc3"; 302b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 303b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 304b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 305b457e191SSvyatoslav Ryhel }; 306b457e191SSvyatoslav Ryhel 307b457e191SSvyatoslav Ryhel sdmmc3-data { 308b457e191SSvyatoslav Ryhel nvidia,pins = "sdmmc3_cmd_pa7", 309b457e191SSvyatoslav Ryhel "sdmmc3_dat0_pb7", 310b457e191SSvyatoslav Ryhel "sdmmc3_dat1_pb6", 311b457e191SSvyatoslav Ryhel "sdmmc3_dat2_pb5", 312b457e191SSvyatoslav Ryhel "sdmmc3_dat3_pb4", 313b457e191SSvyatoslav Ryhel "kb_col4_pq4", 314b457e191SSvyatoslav Ryhel "sdmmc3_cd_n_pv2", 315b457e191SSvyatoslav Ryhel "sdmmc3_clk_lb_out_pee4", 316b457e191SSvyatoslav Ryhel "sdmmc3_clk_lb_in_pee5"; 317b457e191SSvyatoslav Ryhel nvidia,function = "sdmmc3"; 318b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 319b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 320b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 321b457e191SSvyatoslav Ryhel }; 322b457e191SSvyatoslav Ryhel 323b457e191SSvyatoslav Ryhel microsd-pwr { 324b457e191SSvyatoslav Ryhel nvidia,pins = "gmi_clk_pk1"; 325724ba675SRob Herring nvidia,function = "gmi"; 326724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 327724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 328724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 329724ba675SRob Herring }; 330b457e191SSvyatoslav Ryhel 331b457e191SSvyatoslav Ryhel /* EMMC pinmux */ 332b457e191SSvyatoslav Ryhel sdmmc4-clk-cmd { 333b457e191SSvyatoslav Ryhel nvidia,pins = "sdmmc4_clk_pcc4"; 334b457e191SSvyatoslav Ryhel nvidia,function = "sdmmc4"; 335b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 336b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 337b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 338724ba675SRob Herring }; 339724ba675SRob Herring 340b457e191SSvyatoslav Ryhel sdmmc4-data { 341b457e191SSvyatoslav Ryhel nvidia,pins = "sdmmc4_cmd_pt7", 342b457e191SSvyatoslav Ryhel "sdmmc4_dat0_paa0", 343b457e191SSvyatoslav Ryhel "sdmmc4_dat1_paa1", 344b457e191SSvyatoslav Ryhel "sdmmc4_dat2_paa2", 345b457e191SSvyatoslav Ryhel "sdmmc4_dat3_paa3", 346b457e191SSvyatoslav Ryhel "sdmmc4_dat4_paa4", 347b457e191SSvyatoslav Ryhel "sdmmc4_dat5_paa5", 348b457e191SSvyatoslav Ryhel "sdmmc4_dat6_paa6", 349b457e191SSvyatoslav Ryhel "sdmmc4_dat7_paa7"; 350b457e191SSvyatoslav Ryhel nvidia,function = "sdmmc4"; 351724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 352724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 353724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 354724ba675SRob Herring }; 355724ba675SRob Herring 356b457e191SSvyatoslav Ryhel /* I2C pinmux */ 357b457e191SSvyatoslav Ryhel gen1-i2c { 358b457e191SSvyatoslav Ryhel nvidia,pins = "gen1_i2c_scl_pc4", 359b457e191SSvyatoslav Ryhel "gen1_i2c_sda_pc5"; 360b457e191SSvyatoslav Ryhel nvidia,function = "i2c1"; 361b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 362b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 363b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 364b457e191SSvyatoslav Ryhel nvidia,open-drain = <TEGRA_PIN_ENABLE>; 365b457e191SSvyatoslav Ryhel nvidia,lock = <TEGRA_PIN_DISABLE>; 366b457e191SSvyatoslav Ryhel }; 367b457e191SSvyatoslav Ryhel 368b457e191SSvyatoslav Ryhel gen2-i2c { 369b457e191SSvyatoslav Ryhel nvidia,pins = "gen2_i2c_scl_pt5", 370b457e191SSvyatoslav Ryhel "gen2_i2c_sda_pt6"; 371b457e191SSvyatoslav Ryhel nvidia,function = "i2c2"; 372b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 373b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 374b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 375b457e191SSvyatoslav Ryhel nvidia,open-drain = <TEGRA_PIN_ENABLE>; 376b457e191SSvyatoslav Ryhel nvidia,lock = <TEGRA_PIN_DISABLE>; 377b457e191SSvyatoslav Ryhel }; 378b457e191SSvyatoslav Ryhel 379b457e191SSvyatoslav Ryhel cam-i2c { 380b457e191SSvyatoslav Ryhel nvidia,pins = "cam_i2c_scl_pbb1", 381b457e191SSvyatoslav Ryhel "cam_i2c_sda_pbb2"; 382b457e191SSvyatoslav Ryhel nvidia,function = "i2c3"; 383b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 384b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 385b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 386b457e191SSvyatoslav Ryhel nvidia,open-drain = <TEGRA_PIN_ENABLE>; 387b457e191SSvyatoslav Ryhel nvidia,lock = <TEGRA_PIN_DISABLE>; 388b457e191SSvyatoslav Ryhel }; 389b457e191SSvyatoslav Ryhel 390b457e191SSvyatoslav Ryhel ddc-i2c { 391b457e191SSvyatoslav Ryhel nvidia,pins = "ddc_scl_pv4", 392b457e191SSvyatoslav Ryhel "ddc_sda_pv5"; 393b457e191SSvyatoslav Ryhel nvidia,function = "i2c4"; 394b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 395b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 396b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 397b457e191SSvyatoslav Ryhel nvidia,lock = <TEGRA_PIN_DISABLE>; 398b457e191SSvyatoslav Ryhel }; 399b457e191SSvyatoslav Ryhel 400b457e191SSvyatoslav Ryhel pwr-i2c { 401b457e191SSvyatoslav Ryhel nvidia,pins = "pwr_i2c_scl_pz6", 402b457e191SSvyatoslav Ryhel "pwr_i2c_sda_pz7"; 403b457e191SSvyatoslav Ryhel nvidia,function = "i2cpwr"; 404b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 405b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 406b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 407b457e191SSvyatoslav Ryhel nvidia,open-drain = <TEGRA_PIN_ENABLE>; 408b457e191SSvyatoslav Ryhel nvidia,lock = <TEGRA_PIN_DISABLE>; 409b457e191SSvyatoslav Ryhel }; 410b457e191SSvyatoslav Ryhel 411b457e191SSvyatoslav Ryhel /* SPI pinmux */ 412b457e191SSvyatoslav Ryhel spi1-out { 413b457e191SSvyatoslav Ryhel nvidia,pins = "ulpi_clk_py0", 414b457e191SSvyatoslav Ryhel "ulpi_nxt_py2", 415b457e191SSvyatoslav Ryhel "ulpi_stp_py3"; 416b457e191SSvyatoslav Ryhel nvidia,function = "spi1"; 417724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 418724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 419724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 420724ba675SRob Herring }; 421b457e191SSvyatoslav Ryhel 422b457e191SSvyatoslav Ryhel spi1-in { 423b457e191SSvyatoslav Ryhel nvidia,pins = "ulpi_dir_py1"; 424b457e191SSvyatoslav Ryhel nvidia,function = "spi1"; 425b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 426b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 427b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 428724ba675SRob Herring }; 429724ba675SRob Herring 430b457e191SSvyatoslav Ryhel spi2 { 431b457e191SSvyatoslav Ryhel nvidia,pins = "ulpi_data4_po5", 432b457e191SSvyatoslav Ryhel "ulpi_data7_po0"; 433b457e191SSvyatoslav Ryhel nvidia,function = "spi2"; 434b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 435b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 436b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 437b457e191SSvyatoslav Ryhel }; 438b457e191SSvyatoslav Ryhel 439b457e191SSvyatoslav Ryhel spi4-out { 440b457e191SSvyatoslav Ryhel nvidia,pins = "gmi_ad6_pg6", 441b457e191SSvyatoslav Ryhel "gmi_wr_n_pi0"; 442b457e191SSvyatoslav Ryhel nvidia,function = "spi4"; 443b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 444b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 445b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 446b457e191SSvyatoslav Ryhel }; 447b457e191SSvyatoslav Ryhel 448b457e191SSvyatoslav Ryhel spi4-in { 449b457e191SSvyatoslav Ryhel nvidia,pins = "gmi_ad5_pg5", 450b457e191SSvyatoslav Ryhel "gmi_ad7_pg7"; 451b457e191SSvyatoslav Ryhel nvidia,function = "spi4"; 452b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 453b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 454b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 455b457e191SSvyatoslav Ryhel }; 456b457e191SSvyatoslav Ryhel 457b457e191SSvyatoslav Ryhel /* GPIO keys pinmux */ 458b457e191SSvyatoslav Ryhel hall-switch { 459724ba675SRob Herring nvidia,pins = "ulpi_data4_po5"; 460724ba675SRob Herring nvidia,function = "spi2"; 461724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 462724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 463724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 464724ba675SRob Herring }; 465b457e191SSvyatoslav Ryhel 466b457e191SSvyatoslav Ryhel lineout-switch { 467b457e191SSvyatoslav Ryhel nvidia,pins = "gpio_x5_aud_px5"; 468b457e191SSvyatoslav Ryhel nvidia,function = "rsvd1"; 469b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 470b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 471b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 472724ba675SRob Herring }; 473724ba675SRob Herring 474b457e191SSvyatoslav Ryhel power-key { 475724ba675SRob Herring nvidia,pins = "kb_col0_pq0"; 476724ba675SRob Herring nvidia,function = "kbc"; 477724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 478724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 479724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 480724ba675SRob Herring }; 481724ba675SRob Herring 482b457e191SSvyatoslav Ryhel volume-keys { 483724ba675SRob Herring nvidia,pins = "kb_row1_pr1", 484724ba675SRob Herring "kb_row2_pr2"; 485724ba675SRob Herring nvidia,function = "rsvd2"; 486724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 487724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_ENABLE>; 488724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 489724ba675SRob Herring }; 490724ba675SRob Herring 491b457e191SSvyatoslav Ryhel /* Sensors pinmux */ 492b457e191SSvyatoslav Ryhel nct-irq { 493b457e191SSvyatoslav Ryhel nvidia,pins = "ulpi_data3_po4"; 494b457e191SSvyatoslav Ryhel nvidia,function = "ulpi"; 495724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_UP>; 496724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 497724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 498724ba675SRob Herring }; 499724ba675SRob Herring 500b457e191SSvyatoslav Ryhel mpu-irq { 501724ba675SRob Herring nvidia,pins = "kb_row3_pr3"; 502724ba675SRob Herring nvidia,function = "rsvd3"; 503724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 504724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 505724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_ENABLE>; 506724ba675SRob Herring }; 507b457e191SSvyatoslav Ryhel 508b457e191SSvyatoslav Ryhel /* HDMI pinmux */ 509b457e191SSvyatoslav Ryhel hdmi-hpd { 510b457e191SSvyatoslav Ryhel nvidia,pins = "hdmi_int_pn7"; 511b457e191SSvyatoslav Ryhel nvidia,function = "rsvd1"; 512b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 513b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 514b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 515724ba675SRob Herring }; 516724ba675SRob Herring 517b457e191SSvyatoslav Ryhel hdmi-en { 518b457e191SSvyatoslav Ryhel nvidia,pins = "dap3_dout_pp2"; 519b457e191SSvyatoslav Ryhel nvidia,function = "i2s2"; 520b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 521b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 522b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 523b457e191SSvyatoslav Ryhel }; 524b457e191SSvyatoslav Ryhel 525b457e191SSvyatoslav Ryhel hdmi-cec { 526b457e191SSvyatoslav Ryhel nvidia,pins = "hdmi_cec_pee3"; 527b457e191SSvyatoslav Ryhel nvidia,function = "cec"; 528b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 529b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 530b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 531b457e191SSvyatoslav Ryhel }; 532b457e191SSvyatoslav Ryhel 533b457e191SSvyatoslav Ryhel /* LED pinmux */ 534b457e191SSvyatoslav Ryhel backlight-pwm { 535724ba675SRob Herring nvidia,pins = "gmi_ad9_ph1"; 536724ba675SRob Herring nvidia,function = "pwm1"; 537724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 538724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 539724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 540724ba675SRob Herring }; 541b457e191SSvyatoslav Ryhel 542b457e191SSvyatoslav Ryhel backlight-en { 543b457e191SSvyatoslav Ryhel nvidia,pins = "gmi_ad10_ph2"; 544b457e191SSvyatoslav Ryhel nvidia,function = "gmi"; 545b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 546b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 547b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 548724ba675SRob Herring }; 549724ba675SRob Herring 550b457e191SSvyatoslav Ryhel /* Touchscreen pinmux */ 551b457e191SSvyatoslav Ryhel touch-irq { 552b457e191SSvyatoslav Ryhel nvidia,pins = "gmi_cs4_n_pk2"; 553b457e191SSvyatoslav Ryhel nvidia,function = "gmi"; 554b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 555b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 556b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 557b457e191SSvyatoslav Ryhel }; 558b457e191SSvyatoslav Ryhel 559b457e191SSvyatoslav Ryhel touch-rst { 560b457e191SSvyatoslav Ryhel nvidia,pins = "gmi_cs3_n_pk4"; 561b457e191SSvyatoslav Ryhel nvidia,function = "gmi"; 562b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 563b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 564b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 565b457e191SSvyatoslav Ryhel }; 566b457e191SSvyatoslav Ryhel 567b457e191SSvyatoslav Ryhel touch-pwr { 568b457e191SSvyatoslav Ryhel nvidia,pins = "gmi_ad8_ph0"; 569b457e191SSvyatoslav Ryhel nvidia,function = "gmi"; 570b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 571b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 572b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 573b457e191SSvyatoslav Ryhel }; 574b457e191SSvyatoslav Ryhel 575b457e191SSvyatoslav Ryhel touch-vio { 576b457e191SSvyatoslav Ryhel nvidia,pins = "gmi_ad12_ph4"; 577b457e191SSvyatoslav Ryhel nvidia,function = "rsvd4"; 578b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 579b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 580b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 581b457e191SSvyatoslav Ryhel }; 582b457e191SSvyatoslav Ryhel 583b457e191SSvyatoslav Ryhel /* AUDIO pinmux */ 584b457e191SSvyatoslav Ryhel audio-ldo1 { 585b457e191SSvyatoslav Ryhel nvidia,pins = "sdmmc1_wp_n_pv3"; 586b457e191SSvyatoslav Ryhel nvidia,function = "sdmmc1"; 587b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 588b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 589b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 590b457e191SSvyatoslav Ryhel }; 591b457e191SSvyatoslav Ryhel 592b457e191SSvyatoslav Ryhel hp-detect { 593b457e191SSvyatoslav Ryhel nvidia,pins = "kb_row7_pr7"; 594b457e191SSvyatoslav Ryhel nvidia,function = "rsvd2"; 595b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 596b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 597b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 598b457e191SSvyatoslav Ryhel }; 599b457e191SSvyatoslav Ryhel 600b457e191SSvyatoslav Ryhel dap-i2s0-in { 601b457e191SSvyatoslav Ryhel nvidia,pins = "dap1_din_pn1"; 602b457e191SSvyatoslav Ryhel nvidia,function = "i2s0"; 603b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 604b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 605b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 606b457e191SSvyatoslav Ryhel }; 607b457e191SSvyatoslav Ryhel 608b457e191SSvyatoslav Ryhel dap-i2s0-out { 609b457e191SSvyatoslav Ryhel nvidia,pins = "dap1_dout_pn2", 610b457e191SSvyatoslav Ryhel "dap1_fs_pn0", 611b457e191SSvyatoslav Ryhel "dap1_sclk_pn3"; 612b457e191SSvyatoslav Ryhel nvidia,function = "i2s0"; 613b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 614b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 615b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 616b457e191SSvyatoslav Ryhel }; 617b457e191SSvyatoslav Ryhel 618b457e191SSvyatoslav Ryhel dap-i2s1-in { 619b457e191SSvyatoslav Ryhel nvidia,pins = "dap2_din_pa4"; 620b457e191SSvyatoslav Ryhel nvidia,function = "i2s1"; 621b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 622b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 623b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 624b457e191SSvyatoslav Ryhel }; 625b457e191SSvyatoslav Ryhel 626b457e191SSvyatoslav Ryhel dap-i2s1-out { 627b457e191SSvyatoslav Ryhel nvidia,pins = "dap2_dout_pa5", 628b457e191SSvyatoslav Ryhel "dap2_fs_pa2", 629b457e191SSvyatoslav Ryhel "dap2_sclk_pa3"; 630b457e191SSvyatoslav Ryhel nvidia,function = "i2s1"; 631b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 632b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 633b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 634b457e191SSvyatoslav Ryhel }; 635b457e191SSvyatoslav Ryhel 636b457e191SSvyatoslav Ryhel dap-i2s2-in { 637b457e191SSvyatoslav Ryhel nvidia,pins = "dap3_fs_pp0", 638b457e191SSvyatoslav Ryhel "dap3_sclk_pp3"; 639b457e191SSvyatoslav Ryhel nvidia,function = "i2s2"; 640b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 641b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_ENABLE>; 642b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 643b457e191SSvyatoslav Ryhel }; 644b457e191SSvyatoslav Ryhel 645b457e191SSvyatoslav Ryhel dap-i2s2-out { 646b457e191SSvyatoslav Ryhel nvidia,pins = "dap3_din_pp1"; 647b457e191SSvyatoslav Ryhel nvidia,function = "i2s2"; 648b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 649b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 650b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 651b457e191SSvyatoslav Ryhel }; 652b457e191SSvyatoslav Ryhel 653b457e191SSvyatoslav Ryhel spdif-in { 654b457e191SSvyatoslav Ryhel nvidia,pins = "spdif_in_pk6"; 655b457e191SSvyatoslav Ryhel nvidia,function = "rsvd3"; 656b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 657b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 658b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 659b457e191SSvyatoslav Ryhel }; 660b457e191SSvyatoslav Ryhel 661b457e191SSvyatoslav Ryhel spdif-out { 662b457e191SSvyatoslav Ryhel nvidia,pins = "spdif_out_pk5"; 663b457e191SSvyatoslav Ryhel nvidia,function = "rsvd2"; 664b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 665b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_ENABLE>; 666b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 667b457e191SSvyatoslav Ryhel }; 668b457e191SSvyatoslav Ryhel 669b457e191SSvyatoslav Ryhel /* AsusEC pinmux */ 670b457e191SSvyatoslav Ryhel ec-irq { 671b457e191SSvyatoslav Ryhel nvidia,pins = "kb_col5_pq5"; 672b457e191SSvyatoslav Ryhel nvidia,function = "kbc"; 673b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 674b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 675b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 676b457e191SSvyatoslav Ryhel }; 677b457e191SSvyatoslav Ryhel 678b457e191SSvyatoslav Ryhel ec-req { 679b457e191SSvyatoslav Ryhel nvidia,pins = "kb_col2_pq2"; 680b457e191SSvyatoslav Ryhel nvidia,function = "kbc"; 681b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 682b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 683b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 684b457e191SSvyatoslav Ryhel }; 685b457e191SSvyatoslav Ryhel 686b457e191SSvyatoslav Ryhel hotplug-i2c { 687b457e191SSvyatoslav Ryhel nvidia,pins = "ulpi_data7_po0"; 688b457e191SSvyatoslav Ryhel nvidia,function = "spi2"; 689b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 690b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 691b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 692b457e191SSvyatoslav Ryhel }; 693b457e191SSvyatoslav Ryhel 694b457e191SSvyatoslav Ryhel ps2-irq { 695b457e191SSvyatoslav Ryhel nvidia,pins = "gpio_w2_aud_pw2"; 696b457e191SSvyatoslav Ryhel nvidia,function = "spi6"; 697b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 698b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 699b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 700b457e191SSvyatoslav Ryhel }; 701b457e191SSvyatoslav Ryhel 702b457e191SSvyatoslav Ryhel kbd-irq { 703b457e191SSvyatoslav Ryhel nvidia,pins = "gmi_cs0_n_pj0"; 704b457e191SSvyatoslav Ryhel nvidia,function = "rsvd1"; 705b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 706b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 707b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 708b457e191SSvyatoslav Ryhel }; 709b457e191SSvyatoslav Ryhel 710b457e191SSvyatoslav Ryhel dvfs-pin { 711b457e191SSvyatoslav Ryhel nvidia,pins = "dvfs_pwm_px0", 712b457e191SSvyatoslav Ryhel "dvfs_clk_px2"; 713b457e191SSvyatoslav Ryhel nvidia,function = "cldvfs"; 714b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 715b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 716b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 717b457e191SSvyatoslav Ryhel }; 718b457e191SSvyatoslav Ryhel 719b457e191SSvyatoslav Ryhel /* Core pinmux */ 720b457e191SSvyatoslav Ryhel clk-32k-out { 721b457e191SSvyatoslav Ryhel nvidia,pins = "clk_32k_out_pa0"; 722b457e191SSvyatoslav Ryhel nvidia,function = "soc"; 723b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 724b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 725b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 726b457e191SSvyatoslav Ryhel }; 727b457e191SSvyatoslav Ryhel 728b457e191SSvyatoslav Ryhel sys-clk-req { 729b457e191SSvyatoslav Ryhel nvidia,pins = "sys_clk_req_pz5"; 730b457e191SSvyatoslav Ryhel nvidia,function = "sysclk"; 731b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 732b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 733b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 734b457e191SSvyatoslav Ryhel }; 735b457e191SSvyatoslav Ryhel 736b457e191SSvyatoslav Ryhel core-pwr-req { 737b457e191SSvyatoslav Ryhel nvidia,pins = "core_pwr_req"; 738b457e191SSvyatoslav Ryhel nvidia,function = "pwron"; 739b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 740b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 741b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 742b457e191SSvyatoslav Ryhel }; 743b457e191SSvyatoslav Ryhel 744b457e191SSvyatoslav Ryhel cpu-pwr-req { 745b457e191SSvyatoslav Ryhel nvidia,pins = "cpu_pwr_req"; 746b457e191SSvyatoslav Ryhel nvidia,function = "cpu"; 747b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 748b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 749b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 750b457e191SSvyatoslav Ryhel }; 751b457e191SSvyatoslav Ryhel 752b457e191SSvyatoslav Ryhel pwr-int-n { 753b457e191SSvyatoslav Ryhel nvidia,pins = "pwr_int_n"; 754b457e191SSvyatoslav Ryhel nvidia,function = "pmi"; 755b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 756b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 757b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 758b457e191SSvyatoslav Ryhel }; 759b457e191SSvyatoslav Ryhel 760b457e191SSvyatoslav Ryhel clk-32k-in { 761b457e191SSvyatoslav Ryhel nvidia,pins = "clk_32k_in"; 762b457e191SSvyatoslav Ryhel nvidia,function = "clk"; 763b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 764b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 765b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 766b457e191SSvyatoslav Ryhel }; 767b457e191SSvyatoslav Ryhel 768b457e191SSvyatoslav Ryhel owr { 769b457e191SSvyatoslav Ryhel nvidia,pins = "owr"; 770b457e191SSvyatoslav Ryhel nvidia,function = "rsvd2"; 771b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 772b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_ENABLE>; 773b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 774b457e191SSvyatoslav Ryhel }; 775b457e191SSvyatoslav Ryhel 776b457e191SSvyatoslav Ryhel reset-out-n { 777b457e191SSvyatoslav Ryhel nvidia,pins = "reset_out_n"; 778b457e191SSvyatoslav Ryhel nvidia,function = "reset_out_n"; 779b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 780b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 781b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 782b457e191SSvyatoslav Ryhel }; 783b457e191SSvyatoslav Ryhel 784b457e191SSvyatoslav Ryhel /* ULPI pinmux */ 785b457e191SSvyatoslav Ryhel ulpi-data0-6 { 786b457e191SSvyatoslav Ryhel nvidia,pins = "ulpi_data0_po1", 787b457e191SSvyatoslav Ryhel "ulpi_data6_po7"; 788b457e191SSvyatoslav Ryhel nvidia,function = "ulpi"; 789b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 790b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 791b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 792b457e191SSvyatoslav Ryhel }; 793b457e191SSvyatoslav Ryhel 794b457e191SSvyatoslav Ryhel ulpi-data1-5 { 795b457e191SSvyatoslav Ryhel nvidia,pins = "ulpi_data1_po2", 796b457e191SSvyatoslav Ryhel "ulpi_data5_po6"; 797b457e191SSvyatoslav Ryhel nvidia,function = "ulpi"; 798b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 799b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_ENABLE>; 800b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 801b457e191SSvyatoslav Ryhel }; 802b457e191SSvyatoslav Ryhel 803b457e191SSvyatoslav Ryhel ulpi-data2-3 { 804b457e191SSvyatoslav Ryhel nvidia,pins = "ulpi_data2_po3", 805b457e191SSvyatoslav Ryhel "ulpi_data3_po4"; 806b457e191SSvyatoslav Ryhel nvidia,function = "ulpi"; 807b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 808b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 809b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 810b457e191SSvyatoslav Ryhel }; 811b457e191SSvyatoslav Ryhel 812b457e191SSvyatoslav Ryhel /* PORT V */ 813b457e191SSvyatoslav Ryhel pv0-gpio { 814b457e191SSvyatoslav Ryhel nvidia,pins = "pv0"; 815b457e191SSvyatoslav Ryhel nvidia,function = "rsvd2"; 816b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 817b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 818b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 819b457e191SSvyatoslav Ryhel }; 820b457e191SSvyatoslav Ryhel 821b457e191SSvyatoslav Ryhel pv1-gpio { 822b457e191SSvyatoslav Ryhel nvidia,pins = "pv1"; 823b457e191SSvyatoslav Ryhel nvidia,function = "rsvd1"; 824b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 825b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 826b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 827b457e191SSvyatoslav Ryhel }; 828b457e191SSvyatoslav Ryhel 829b457e191SSvyatoslav Ryhel /* PORT U */ 830b457e191SSvyatoslav Ryhel pu0-gpio { 831b457e191SSvyatoslav Ryhel nvidia,pins = "pu0"; 832b457e191SSvyatoslav Ryhel nvidia,function = "rsvd3"; 833b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 834b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 835b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 836b457e191SSvyatoslav Ryhel }; 837b457e191SSvyatoslav Ryhel 838b457e191SSvyatoslav Ryhel pu2-gpio { 839b457e191SSvyatoslav Ryhel nvidia,pins = "pu2"; 840b457e191SSvyatoslav Ryhel nvidia,function = "rsvd1"; 841b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 842b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 843b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 844b457e191SSvyatoslav Ryhel }; 845b457e191SSvyatoslav Ryhel 846b457e191SSvyatoslav Ryhel /* PWM pinmux */ 847b457e191SSvyatoslav Ryhel pwm0 { 848b457e191SSvyatoslav Ryhel nvidia,pins = "pu3"; 849b457e191SSvyatoslav Ryhel nvidia,function = "pwm0"; 850b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 851b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 852b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 853b457e191SSvyatoslav Ryhel }; 854b457e191SSvyatoslav Ryhel 855b457e191SSvyatoslav Ryhel pwm1 { 856b457e191SSvyatoslav Ryhel nvidia,pins = "pu4"; 857724ba675SRob Herring nvidia,function = "pwm1"; 858724ba675SRob Herring nvidia,pull = <TEGRA_PIN_PULL_NONE>; 859724ba675SRob Herring nvidia,tristate = <TEGRA_PIN_DISABLE>; 860724ba675SRob Herring nvidia,enable-input = <TEGRA_PIN_DISABLE>; 861724ba675SRob Herring }; 862b457e191SSvyatoslav Ryhel 863b457e191SSvyatoslav Ryhel /* EXTPERIPH pinmux */ 864b457e191SSvyatoslav Ryhel clk1-out { 865b457e191SSvyatoslav Ryhel nvidia,pins = "clk1_out_pw4"; 866b457e191SSvyatoslav Ryhel nvidia,function = "extperiph1"; 867b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 868b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 869b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 870724ba675SRob Herring }; 871724ba675SRob Herring 872b457e191SSvyatoslav Ryhel clk2-out { 873b457e191SSvyatoslav Ryhel nvidia,pins = "clk2_out_pw5"; 874b457e191SSvyatoslav Ryhel nvidia,function = "extperiph2"; 875b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 876b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 877b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 878b457e191SSvyatoslav Ryhel }; 879b457e191SSvyatoslav Ryhel 880b457e191SSvyatoslav Ryhel clk3-out { 881b457e191SSvyatoslav Ryhel nvidia,pins = "clk3_out_pee0"; 882b457e191SSvyatoslav Ryhel nvidia,function = "extperiph3"; 883b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 884b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 885b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 886b457e191SSvyatoslav Ryhel }; 887b457e191SSvyatoslav Ryhel 888b457e191SSvyatoslav Ryhel clk1-req { 889b457e191SSvyatoslav Ryhel nvidia,pins = "clk1_req_pee2"; 890b457e191SSvyatoslav Ryhel nvidia,function = "rsvd3"; 891b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 892b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_ENABLE>; 893b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 894b457e191SSvyatoslav Ryhel }; 895b457e191SSvyatoslav Ryhel 896b457e191SSvyatoslav Ryhel /* GMI pinmux */ 897b457e191SSvyatoslav Ryhel gmi-wp-n { 898b457e191SSvyatoslav Ryhel nvidia,pins = "gmi_wp_n_pc7"; 899b457e191SSvyatoslav Ryhel nvidia,function = "rsvd1"; 900b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 901b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_ENABLE>; 902b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 903b457e191SSvyatoslav Ryhel }; 904b457e191SSvyatoslav Ryhel 905b457e191SSvyatoslav Ryhel gmi-adv { 906b457e191SSvyatoslav Ryhel nvidia,pins = "gmi_adv_n_pk0"; 907b457e191SSvyatoslav Ryhel nvidia,function = "rsvd1"; 908b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 909b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 910b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 911b457e191SSvyatoslav Ryhel }; 912b457e191SSvyatoslav Ryhel 913b457e191SSvyatoslav Ryhel gmi-ad0-ad1 { 914b457e191SSvyatoslav Ryhel nvidia,pins = "gmi_ad0_pg0", 915b457e191SSvyatoslav Ryhel "gmi_ad1_pg1"; 916b457e191SSvyatoslav Ryhel nvidia,function = "rsvd1"; 917b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 918b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 919b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 920b457e191SSvyatoslav Ryhel }; 921b457e191SSvyatoslav Ryhel 922b457e191SSvyatoslav Ryhel gmi-ad2-ad3 { 923b457e191SSvyatoslav Ryhel nvidia,pins = "gmi_ad2_pg2", 924b457e191SSvyatoslav Ryhel "gmi_ad3_pg3"; 925b457e191SSvyatoslav Ryhel nvidia,function = "rsvd1"; 926b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 927b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 928b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 929b457e191SSvyatoslav Ryhel }; 930b457e191SSvyatoslav Ryhel 931b457e191SSvyatoslav Ryhel gmi-iordy { 932b457e191SSvyatoslav Ryhel nvidia,pins = "gmi_iordy_pi5"; 933b457e191SSvyatoslav Ryhel nvidia,function = "rsvd2"; 934b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 935b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 936b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 937b457e191SSvyatoslav Ryhel }; 938b457e191SSvyatoslav Ryhel 939b457e191SSvyatoslav Ryhel gmi-a18 { 940b457e191SSvyatoslav Ryhel nvidia,pins = "gmi_a18_pb1"; 941b457e191SSvyatoslav Ryhel nvidia,function = "rsvd2"; 942b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 943b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_ENABLE>; 944b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 945b457e191SSvyatoslav Ryhel }; 946b457e191SSvyatoslav Ryhel 947b457e191SSvyatoslav Ryhel gmi-wait { 948b457e191SSvyatoslav Ryhel nvidia,pins = "gmi_wait_pi7"; 949b457e191SSvyatoslav Ryhel nvidia,function = "nand"; 950b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 951b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 952b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 953b457e191SSvyatoslav Ryhel }; 954b457e191SSvyatoslav Ryhel 955b457e191SSvyatoslav Ryhel gmi-cs6-n { 956b457e191SSvyatoslav Ryhel nvidia,pins = "gmi_cs6_n_pi3"; 957b457e191SSvyatoslav Ryhel nvidia,function = "nand"; 958b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 959b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_ENABLE>; 960b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 961b457e191SSvyatoslav Ryhel }; 962b457e191SSvyatoslav Ryhel 963b457e191SSvyatoslav Ryhel gmi-cs7-n { 964b457e191SSvyatoslav Ryhel nvidia,pins = "gmi_cs7_n_pi6"; 965b457e191SSvyatoslav Ryhel nvidia,function = "nand"; 966b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 967b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 968b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 969b457e191SSvyatoslav Ryhel }; 970b457e191SSvyatoslav Ryhel 971b457e191SSvyatoslav Ryhel gmi-dqs-p { 972b457e191SSvyatoslav Ryhel nvidia,pins = "gmi_dqs_p_pj3"; 973b457e191SSvyatoslav Ryhel nvidia,function = "nand"; 974b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 975b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_ENABLE>; 976b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 977b457e191SSvyatoslav Ryhel }; 978b457e191SSvyatoslav Ryhel 979b457e191SSvyatoslav Ryhel gmi-cs2-ad { 980b457e191SSvyatoslav Ryhel nvidia,pins = "gmi_cs2_n_pk3", 981b457e191SSvyatoslav Ryhel "gmi_ad14_ph6", 982b457e191SSvyatoslav Ryhel "gmi_ad15_ph7"; 983b457e191SSvyatoslav Ryhel nvidia,function = "gmi"; 984b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 985b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_ENABLE>; 986b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 987b457e191SSvyatoslav Ryhel }; 988b457e191SSvyatoslav Ryhel 989b457e191SSvyatoslav Ryhel gmi-cs4-clk { 990b457e191SSvyatoslav Ryhel nvidia,pins = "gmi_cs4_n_pk2", 991b457e191SSvyatoslav Ryhel "gmi_clk_lb"; 992b457e191SSvyatoslav Ryhel nvidia,function = "gmi"; 993b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 994b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 995b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 996b457e191SSvyatoslav Ryhel }; 997b457e191SSvyatoslav Ryhel 998b457e191SSvyatoslav Ryhel gmi-ad11 { 999b457e191SSvyatoslav Ryhel nvidia,pins = "gmi_ad11_ph3"; 1000b457e191SSvyatoslav Ryhel nvidia,function = "gmi"; 1001b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1002b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 1003b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1004b457e191SSvyatoslav Ryhel }; 1005b457e191SSvyatoslav Ryhel 1006b457e191SSvyatoslav Ryhel gmi-cs1-oe { 1007b457e191SSvyatoslav Ryhel nvidia,pins = "gmi_cs1_n_pj2", 1008b457e191SSvyatoslav Ryhel "gmi_oe_n_pi1"; 1009b457e191SSvyatoslav Ryhel nvidia,function = "soc"; 1010b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 1011b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 1012b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1013b457e191SSvyatoslav Ryhel }; 1014b457e191SSvyatoslav Ryhel 1015b457e191SSvyatoslav Ryhel gmi-ad4 { 1016b457e191SSvyatoslav Ryhel nvidia,pins = "gmi_ad4_pg4"; 1017b457e191SSvyatoslav Ryhel nvidia,function = "rsvd4"; 1018b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1019b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 1020b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1021b457e191SSvyatoslav Ryhel }; 1022b457e191SSvyatoslav Ryhel 1023b457e191SSvyatoslav Ryhel gmi-ad13 { 1024b457e191SSvyatoslav Ryhel nvidia,pins = "gmi_ad13_ph5"; 1025b457e191SSvyatoslav Ryhel nvidia,function = "rsvd4"; 1026b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1027b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_ENABLE>; 1028b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1029b457e191SSvyatoslav Ryhel }; 1030b457e191SSvyatoslav Ryhel 1031b457e191SSvyatoslav Ryhel gmi-rst-n { 1032b457e191SSvyatoslav Ryhel nvidia,pins = "gmi_rst_n_pi4"; 1033b457e191SSvyatoslav Ryhel nvidia,function = "rsvd4"; 1034b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1035b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 1036b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1037b457e191SSvyatoslav Ryhel }; 1038b457e191SSvyatoslav Ryhel 1039b457e191SSvyatoslav Ryhel /* PORT CC */ 1040b457e191SSvyatoslav Ryhel pcc-gpio { 1041b457e191SSvyatoslav Ryhel nvidia,pins = "pcc1", "pcc2"; 1042b457e191SSvyatoslav Ryhel nvidia,function = "rsvd2"; 1043b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1044b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 1045b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1046b457e191SSvyatoslav Ryhel }; 1047b457e191SSvyatoslav Ryhel 1048b457e191SSvyatoslav Ryhel /* PORT BB */ 1049b457e191SSvyatoslav Ryhel pbb3-gpio { 1050b457e191SSvyatoslav Ryhel nvidia,pins = "pbb3"; 1051b457e191SSvyatoslav Ryhel nvidia,function = "rsvd4"; 1052b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1053b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 1054b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1055b457e191SSvyatoslav Ryhel }; 1056b457e191SSvyatoslav Ryhel 1057b457e191SSvyatoslav Ryhel pbb4-5-6-gpio { 1058b457e191SSvyatoslav Ryhel nvidia,pins = "pbb4", "pbb5", "pbb6"; 1059b457e191SSvyatoslav Ryhel nvidia,function = "rsvd4"; 1060b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1061b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 1062b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1063b457e191SSvyatoslav Ryhel }; 1064b457e191SSvyatoslav Ryhel 1065b457e191SSvyatoslav Ryhel pbb7-gpio { 1066b457e191SSvyatoslav Ryhel nvidia,pins = "pbb7"; 1067b457e191SSvyatoslav Ryhel nvidia,function = "rsvd2"; 1068b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1069b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 1070b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1071b457e191SSvyatoslav Ryhel }; 1072b457e191SSvyatoslav Ryhel 1073b457e191SSvyatoslav Ryhel /* KBC pinmux */ 1074b457e191SSvyatoslav Ryhel kb-r0-c1 { 1075b457e191SSvyatoslav Ryhel nvidia,pins = "kb_row0_pr0", 1076b457e191SSvyatoslav Ryhel "kb_col1_pq1"; 1077b457e191SSvyatoslav Ryhel nvidia,function = "rsvd2"; 1078b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 1079b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 1080b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1081b457e191SSvyatoslav Ryhel }; 1082b457e191SSvyatoslav Ryhel 1083b457e191SSvyatoslav Ryhel kb-row4 { 1084b457e191SSvyatoslav Ryhel nvidia,pins = "kb_row4_pr4"; 1085b457e191SSvyatoslav Ryhel nvidia,function = "kbc"; 1086b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1087b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_ENABLE>; 1088b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1089b457e191SSvyatoslav Ryhel }; 1090b457e191SSvyatoslav Ryhel 1091b457e191SSvyatoslav Ryhel kb-row5 { 1092b457e191SSvyatoslav Ryhel nvidia,pins = "kb_row5_pr5"; 1093b457e191SSvyatoslav Ryhel nvidia,function = "kbc"; 1094b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 1095b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_ENABLE>; 1096b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1097b457e191SSvyatoslav Ryhel }; 1098b457e191SSvyatoslav Ryhel 1099b457e191SSvyatoslav Ryhel kb-row6 { 1100b457e191SSvyatoslav Ryhel nvidia,pins = "kb_row6_pr6"; 1101b457e191SSvyatoslav Ryhel nvidia,function = "kbc"; 1102b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1103b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 1104b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1105b457e191SSvyatoslav Ryhel }; 1106b457e191SSvyatoslav Ryhel 1107b457e191SSvyatoslav Ryhel kb-r8-c3 { 1108b457e191SSvyatoslav Ryhel nvidia,pins = "kb_row8_ps0", 1109b457e191SSvyatoslav Ryhel "kb_col3_pq3"; 1110b457e191SSvyatoslav Ryhel nvidia,function = "kbc"; 1111b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 1112b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 1113b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1114b457e191SSvyatoslav Ryhel }; 1115b457e191SSvyatoslav Ryhel 1116b457e191SSvyatoslav Ryhel /* VI pinmux */ 1117b457e191SSvyatoslav Ryhel cam-mclk { 1118b457e191SSvyatoslav Ryhel nvidia,pins = "cam_mclk_pcc0", 1119b457e191SSvyatoslav Ryhel "pbb0"; 1120b457e191SSvyatoslav Ryhel nvidia,function = "vi_alt3"; 1121b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1122b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 1123b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1124b457e191SSvyatoslav Ryhel }; 1125b457e191SSvyatoslav Ryhel 1126b457e191SSvyatoslav Ryhel /* AUD pinmux */ 1127b457e191SSvyatoslav Ryhel gpio-x4-aud { 1128b457e191SSvyatoslav Ryhel nvidia,pins = "gpio_x4_aud_px4"; 1129b457e191SSvyatoslav Ryhel nvidia,function = "rsvd1"; 1130b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1131b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 1132b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1133b457e191SSvyatoslav Ryhel }; 1134b457e191SSvyatoslav Ryhel 1135b457e191SSvyatoslav Ryhel gpio-x1-aud { 1136b457e191SSvyatoslav Ryhel nvidia,pins = "gpio_x1_aud_px1"; 1137b457e191SSvyatoslav Ryhel nvidia,function = "rsvd2"; 1138b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 1139b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 1140b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1141b457e191SSvyatoslav Ryhel }; 1142b457e191SSvyatoslav Ryhel 1143b457e191SSvyatoslav Ryhel gpio-x3-aud { 1144b457e191SSvyatoslav Ryhel nvidia,pins = "gpio_x3_aud_px3"; 1145b457e191SSvyatoslav Ryhel nvidia,function = "rsvd3"; 1146b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 1147b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 1148b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1149b457e191SSvyatoslav Ryhel }; 1150b457e191SSvyatoslav Ryhel 1151b457e191SSvyatoslav Ryhel gpio-x6-aud { 1152b457e191SSvyatoslav Ryhel nvidia,pins = "gpio_x6_aud_px6"; 1153b457e191SSvyatoslav Ryhel nvidia,function = "rsvd4"; 1154b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 1155b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 1156b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1157b457e191SSvyatoslav Ryhel }; 1158b457e191SSvyatoslav Ryhel 1159b457e191SSvyatoslav Ryhel usb-vbus { 1160b457e191SSvyatoslav Ryhel nvidia,pins = "usb_vbus_en0_pn4", 1161b457e191SSvyatoslav Ryhel "usb_vbus_en1_pn5"; 1162b457e191SSvyatoslav Ryhel nvidia,function = "rsvd2"; 1163b457e191SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1164b457e191SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_ENABLE>; 1165b457e191SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1166b457e191SSvyatoslav Ryhel }; 1167b457e191SSvyatoslav Ryhel 1168b457e191SSvyatoslav Ryhel /* GPIO power/drive control */ 1169b457e191SSvyatoslav Ryhel drive-sdio1 { 1170b457e191SSvyatoslav Ryhel nvidia,pins = "drive_sdio1"; 1171b457e191SSvyatoslav Ryhel nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; 1172b457e191SSvyatoslav Ryhel nvidia,schmitt = <TEGRA_PIN_DISABLE>; 1173b457e191SSvyatoslav Ryhel nvidia,pull-down-strength = <36>; 1174b457e191SSvyatoslav Ryhel nvidia,pull-up-strength = <20>; 1175b457e191SSvyatoslav Ryhel nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>; 1176b457e191SSvyatoslav Ryhel nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>; 1177b457e191SSvyatoslav Ryhel }; 1178b457e191SSvyatoslav Ryhel 1179b457e191SSvyatoslav Ryhel drive-sdio3 { 1180724ba675SRob Herring nvidia,pins = "drive_sdio3"; 1181724ba675SRob Herring nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; 1182724ba675SRob Herring nvidia,schmitt = <TEGRA_PIN_DISABLE>; 1183724ba675SRob Herring nvidia,pull-down-strength = <22>; 1184724ba675SRob Herring nvidia,pull-up-strength = <36>; 1185724ba675SRob Herring nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; 1186724ba675SRob Herring nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; 1187724ba675SRob Herring }; 1188724ba675SRob Herring 1189b457e191SSvyatoslav Ryhel drive-gma { 1190b457e191SSvyatoslav Ryhel nvidia,pins = "drive_gma"; 1191b457e191SSvyatoslav Ryhel nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; 1192b457e191SSvyatoslav Ryhel nvidia,schmitt = <TEGRA_PIN_DISABLE>; 1193b457e191SSvyatoslav Ryhel nvidia,pull-down-strength = <2>; 1194b457e191SSvyatoslav Ryhel nvidia,pull-up-strength = <2>; 1195b457e191SSvyatoslav Ryhel nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; 1196b457e191SSvyatoslav Ryhel nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; 1197724ba675SRob Herring }; 1198724ba675SRob Herring }; 1199724ba675SRob Herring }; 1200724ba675SRob Herring 1201724ba675SRob Herring serial@70006040 { 1202724ba675SRob Herring /* GPS */ 1203724ba675SRob Herring }; 1204724ba675SRob Herring 1205724ba675SRob Herring serial@70006200 { 12066ca426a0SSvyatoslav Ryhel compatible = "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart"; 12076ca426a0SSvyatoslav Ryhel reset-names = "serial"; 12086ca426a0SSvyatoslav Ryhel /delete-property/ reg-shift; 12096ca426a0SSvyatoslav Ryhel status = "okay"; 12106ca426a0SSvyatoslav Ryhel 12116ca426a0SSvyatoslav Ryhel nvidia,adjust-baud-rates = <0 9600 100>, 12126ca426a0SSvyatoslav Ryhel <9600 115200 200>, 12136ca426a0SSvyatoslav Ryhel <1000000 4000000 136>; 12146ca426a0SSvyatoslav Ryhel 12156ca426a0SSvyatoslav Ryhel bluetooth { 12166ca426a0SSvyatoslav Ryhel compatible = "brcm,bcm4334-bt"; 12176ca426a0SSvyatoslav Ryhel max-speed = <4000000>; 12186ca426a0SSvyatoslav Ryhel 12196ca426a0SSvyatoslav Ryhel clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; 12206ca426a0SSvyatoslav Ryhel clock-names = "txco"; 12216ca426a0SSvyatoslav Ryhel 12226ca426a0SSvyatoslav Ryhel interrupt-parent = <&gpio>; 12236ca426a0SSvyatoslav Ryhel interrupts = <TEGRA_GPIO(U, 6) IRQ_TYPE_EDGE_RISING>; 12246ca426a0SSvyatoslav Ryhel interrupt-names = "host-wakeup"; 12256ca426a0SSvyatoslav Ryhel 12266ca426a0SSvyatoslav Ryhel device-wakeup-gpios = <&gpio TEGRA_GPIO(EE, 1) GPIO_ACTIVE_HIGH>; 12276ca426a0SSvyatoslav Ryhel shutdown-gpios = <&gpio TEGRA_GPIO(Q, 7) GPIO_ACTIVE_HIGH>; 12286ca426a0SSvyatoslav Ryhel reset-gpios = <&gpio TEGRA_GPIO(Q, 6) GPIO_ACTIVE_LOW>; 12296ca426a0SSvyatoslav Ryhel 12306ca426a0SSvyatoslav Ryhel vbat-supply = <&vdd_3v3_com>; 12316ca426a0SSvyatoslav Ryhel vddio-supply = <&vdd_1v8_vio>; 12326ca426a0SSvyatoslav Ryhel }; 1233724ba675SRob Herring }; 1234724ba675SRob Herring 1235724ba675SRob Herring serial@70006300 { 12369766116aSThierry Reding /delete-property/ dmas; 12379766116aSThierry Reding /delete-property/ dma-names; 1238724ba675SRob Herring status = "okay"; 1239724ba675SRob Herring }; 1240724ba675SRob Herring 1241724ba675SRob Herring pwm@7000a000 { 1242724ba675SRob Herring status = "okay"; 1243724ba675SRob Herring }; 1244724ba675SRob Herring 1245724ba675SRob Herring i2c@7000c000 { 1246724ba675SRob Herring status = "okay"; 1247724ba675SRob Herring clock-frequency = <100000>; 1248724ba675SRob Herring 1249724ba675SRob Herring magnetometer@c { 1250724ba675SRob Herring compatible = "asahi-kasei,ak09911"; 1251724ba675SRob Herring reg = <0xc>; 1252724ba675SRob Herring 1253c79e35e6SSvyatoslav Ryhel /* no DRDY (polling) */ 1254c79e35e6SSvyatoslav Ryhel 1255c79e35e6SSvyatoslav Ryhel vdd-supply = <&vdd_2v85_sen>; 1256c79e35e6SSvyatoslav Ryhel vid-supply = <&vdd_1v8_vio>; 1257c79e35e6SSvyatoslav Ryhel 1258c79e35e6SSvyatoslav Ryhel mount-matrix = "0", "1", "0", 1259c79e35e6SSvyatoslav Ryhel "1", "0", "0", 1260c79e35e6SSvyatoslav Ryhel "0", "0","-1"; 1261724ba675SRob Herring }; 1262724ba675SRob Herring 1263724ba675SRob Herring rt5639: audio-codec@1c { 1264724ba675SRob Herring compatible = "realtek,rt5639"; 1265724ba675SRob Herring reg = <0x1c>; 1266724ba675SRob Herring 1267e4cee354SSvyatoslav Ryhel realtek,ldo1-en-gpios = 1268e4cee354SSvyatoslav Ryhel <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>; 1269724ba675SRob Herring 1270e4cee354SSvyatoslav Ryhel clocks = <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; 1271e4cee354SSvyatoslav Ryhel clock-names = "mclk"; 1272724ba675SRob Herring }; 1273724ba675SRob Herring 1274724ba675SRob Herring temp_sensor: temperature-sensor@4c { 1275724ba675SRob Herring compatible = "onnn,nct1008"; 1276724ba675SRob Herring reg = <0x4c>; 1277724ba675SRob Herring 1278c79e35e6SSvyatoslav Ryhel interrupt-parent = <&gpio>; 1279c79e35e6SSvyatoslav Ryhel interrupts = <TEGRA_GPIO(O, 4) IRQ_TYPE_EDGE_FALLING>; 1280c79e35e6SSvyatoslav Ryhel 1281c79e35e6SSvyatoslav Ryhel vcc-supply = <&vdd_1v8_vio>; 1282724ba675SRob Herring #thermal-sensor-cells = <1>; 1283724ba675SRob Herring }; 1284724ba675SRob Herring 1285724ba675SRob Herring motion-tracker@68 { 1286724ba675SRob Herring compatible = "invensense,mpu6500"; 1287724ba675SRob Herring reg = <0x68>; 1288724ba675SRob Herring 1289724ba675SRob Herring interrupt-parent = <&gpio>; 1290724ba675SRob Herring interrupts = <TEGRA_GPIO(R, 3) IRQ_TYPE_LEVEL_HIGH>; 1291724ba675SRob Herring 1292c79e35e6SSvyatoslav Ryhel vdd-supply = <&vdd_2v85_sen>; 1293c79e35e6SSvyatoslav Ryhel vddio-supply = <&vdd_1v8_vio>; 1294c79e35e6SSvyatoslav Ryhel 1295724ba675SRob Herring mount-matrix = "0", "-1", "0", 1296724ba675SRob Herring "1", "0", "0", 1297724ba675SRob Herring "0", "0", "1"; 1298724ba675SRob Herring }; 1299724ba675SRob Herring }; 1300724ba675SRob Herring 1301724ba675SRob Herring i2c@7000c400 { 1302724ba675SRob Herring status = "okay"; 1303724ba675SRob Herring clock-frequency = <100000>; 1304724ba675SRob Herring 1305724ba675SRob Herring power-sensor@44 { 1306724ba675SRob Herring compatible = "ti,ina230"; 1307724ba675SRob Herring reg = <0x44>; 1308c79e35e6SSvyatoslav Ryhel 1309c79e35e6SSvyatoslav Ryhel shunt-resistor = <5000>; 1310724ba675SRob Herring }; 1311724ba675SRob Herring }; 1312724ba675SRob Herring 1313724ba675SRob Herring i2c@7000c500 { 1314724ba675SRob Herring status = "okay"; 1315724ba675SRob Herring clock-frequency = <400000>; 1316724ba675SRob Herring 1317724ba675SRob Herring light-sensor@1c { 1318724ba675SRob Herring compatible = "dynaimage,al3320a"; 1319724ba675SRob Herring reg = <0x1c>; 1320724ba675SRob Herring 1321c79e35e6SSvyatoslav Ryhel vdd-supply = <&vdd_1v8_vio>; 1322724ba675SRob Herring }; 1323724ba675SRob Herring }; 1324724ba675SRob Herring 1325fceb6acdSSvyatoslav Ryhel hdmi_ddc: i2c@7000c700 { 1326fceb6acdSSvyatoslav Ryhel status = "okay"; 1327fceb6acdSSvyatoslav Ryhel clock-frequency = <10000>; 1328724ba675SRob Herring }; 1329724ba675SRob Herring 1330724ba675SRob Herring i2c@7000d000 { 1331724ba675SRob Herring status = "okay"; 1332724ba675SRob Herring clock-frequency = <400000>; 1333724ba675SRob Herring 1334724ba675SRob Herring palmas: pmic@58 { 1335724ba675SRob Herring compatible = "ti,tps65913", "ti,palmas"; 1336724ba675SRob Herring reg = <0x58>; 1337724ba675SRob Herring interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1338724ba675SRob Herring 1339724ba675SRob Herring #interrupt-cells = <2>; 1340724ba675SRob Herring interrupt-controller; 1341724ba675SRob Herring 1342724ba675SRob Herring ti,system-power-controller; 1343724ba675SRob Herring 13441f02c9fbSSvyatoslav Ryhel palmas_gpadc: adc { 13451f02c9fbSSvyatoslav Ryhel compatible = "ti,palmas-gpadc"; 13461f02c9fbSSvyatoslav Ryhel interrupts = <18 IRQ_TYPE_NONE>, 13471f02c9fbSSvyatoslav Ryhel <16 IRQ_TYPE_NONE>, 13481f02c9fbSSvyatoslav Ryhel <17 IRQ_TYPE_NONE>; 13491f02c9fbSSvyatoslav Ryhel 13501f02c9fbSSvyatoslav Ryhel ti,channel0-current-microamp = <5>; 13511f02c9fbSSvyatoslav Ryhel ti,channel3-current-microamp = <400>; 13521f02c9fbSSvyatoslav Ryhel ti,enable-extended-delay; 13531f02c9fbSSvyatoslav Ryhel 13541f02c9fbSSvyatoslav Ryhel #io-channel-cells = <1>; 13551f02c9fbSSvyatoslav Ryhel }; 13561f02c9fbSSvyatoslav Ryhel 13571f02c9fbSSvyatoslav Ryhel palmas_extcon: extcon { 13581f02c9fbSSvyatoslav Ryhel compatible = "ti,palmas-usb-vid"; 13591f02c9fbSSvyatoslav Ryhel ti,enable-vbus-detection; 13601f02c9fbSSvyatoslav Ryhel ti,enable-id-detection; 13611f02c9fbSSvyatoslav Ryhel }; 13621f02c9fbSSvyatoslav Ryhel 1363724ba675SRob Herring palmas_gpio: gpio { 1364724ba675SRob Herring compatible = "ti,palmas-gpio"; 1365724ba675SRob Herring gpio-controller; 1366724ba675SRob Herring #gpio-cells = <2>; 1367724ba675SRob Herring }; 1368724ba675SRob Herring 13691f02c9fbSSvyatoslav Ryhel palmas_clk32kg@0 { 13701f02c9fbSSvyatoslav Ryhel compatible = "ti,palmas-clk32kg"; 13711f02c9fbSSvyatoslav Ryhel #clock-cells = <0>; 13721f02c9fbSSvyatoslav Ryhel }; 13731f02c9fbSSvyatoslav Ryhel 1374724ba675SRob Herring pinmux { 1375724ba675SRob Herring compatible = "ti,tps65913-pinctrl"; 1376724ba675SRob Herring ti,palmas-enable-dvfs1; 1377724ba675SRob Herring 1378724ba675SRob Herring pinctrl-names = "default"; 1379724ba675SRob Herring pinctrl-0 = <&palmas_default>; 1380724ba675SRob Herring 1381724ba675SRob Herring palmas_default: pinmux { 1382724ba675SRob Herring pin_gpio0 { 1383724ba675SRob Herring pins = "gpio0"; 1384724ba675SRob Herring function = "gpio"; 1385724ba675SRob Herring }; 1386724ba675SRob Herring 1387724ba675SRob Herring pin_gpio1 { 1388724ba675SRob Herring pins = "gpio1"; 1389724ba675SRob Herring function = "gpio"; 1390724ba675SRob Herring }; 1391724ba675SRob Herring 1392724ba675SRob Herring pin_gpio2 { 1393724ba675SRob Herring pins = "gpio2"; 1394724ba675SRob Herring function = "gpio"; 1395724ba675SRob Herring }; 1396724ba675SRob Herring 1397724ba675SRob Herring pin_gpio3 { 1398724ba675SRob Herring pins = "gpio3"; 1399724ba675SRob Herring function = "gpio"; 1400724ba675SRob Herring }; 1401724ba675SRob Herring 1402724ba675SRob Herring pin_gpio4 { 1403724ba675SRob Herring pins = "gpio4"; 1404724ba675SRob Herring function = "gpio"; 1405724ba675SRob Herring }; 1406724ba675SRob Herring 1407724ba675SRob Herring pin_gpio5 { 1408724ba675SRob Herring pins = "gpio5"; 1409724ba675SRob Herring function = "gpio"; 1410724ba675SRob Herring }; 1411724ba675SRob Herring 1412724ba675SRob Herring pin_gpio6 { 1413724ba675SRob Herring pins = "gpio6"; 1414724ba675SRob Herring function = "gpio"; 1415724ba675SRob Herring }; 1416724ba675SRob Herring 1417724ba675SRob Herring pin_gpio7 { 1418724ba675SRob Herring pins = "gpio7"; 1419724ba675SRob Herring function = "gpio"; 1420724ba675SRob Herring }; 1421724ba675SRob Herring 1422724ba675SRob Herring pin_powergood { 1423724ba675SRob Herring pins = "powergood"; 1424724ba675SRob Herring function = "powergood"; 1425724ba675SRob Herring }; 1426724ba675SRob Herring 1427724ba675SRob Herring pin_vac { 1428724ba675SRob Herring pins = "vac"; 1429724ba675SRob Herring function = "vac"; 1430724ba675SRob Herring }; 1431724ba675SRob Herring }; 1432724ba675SRob Herring }; 1433724ba675SRob Herring 1434724ba675SRob Herring pmic { 1435724ba675SRob Herring compatible = "ti,tps65913-pmic", "ti,palmas-pmic"; 1436724ba675SRob Herring 14371f02c9fbSSvyatoslav Ryhel ldo1-in-supply = <&vddio_ddr>; 14381f02c9fbSSvyatoslav Ryhel ldo2-in-supply = <&vddio_ddr>; 14391f02c9fbSSvyatoslav Ryhel ldo4-in-supply = <&vdd_1v8_vio>; 14401f02c9fbSSvyatoslav Ryhel ldo5-in-supply = <&vcore_emmc>; 14411f02c9fbSSvyatoslav Ryhel ldo6-in-supply = <&vcore_emmc>; 14421f02c9fbSSvyatoslav Ryhel ldo7-in-supply = <&vcore_emmc>; 14431f02c9fbSSvyatoslav Ryhel ldo9-in-supply = <&vcore_emmc>; 14441f02c9fbSSvyatoslav Ryhel ldoln-in-supply = <&vdd_smps10_out2>; 1445724ba675SRob Herring 1446724ba675SRob Herring regulators { 14471f02c9fbSSvyatoslav Ryhel vdd_cpu: smps123 { 14481f02c9fbSSvyatoslav Ryhel regulator-name = "vdd_cpu"; 1449724ba675SRob Herring regulator-min-microvolt = <900000>; 1450724ba675SRob Herring regulator-max-microvolt = <1350000>; 1451724ba675SRob Herring regulator-always-on; 1452724ba675SRob Herring regulator-boot-on; 1453724ba675SRob Herring ti,roof-floor = <1>; 1454724ba675SRob Herring ti,mode-sleep = <3>; 1455724ba675SRob Herring }; 1456724ba675SRob Herring 14571f02c9fbSSvyatoslav Ryhel vdd_core: smps45 { 14581f02c9fbSSvyatoslav Ryhel regulator-name = "vdd_core"; 1459724ba675SRob Herring regulator-min-microvolt = <900000>; 1460724ba675SRob Herring regulator-max-microvolt = <1400000>; 1461724ba675SRob Herring regulator-always-on; 1462724ba675SRob Herring regulator-boot-on; 1463724ba675SRob Herring ti,roof-floor = <3>; 1464724ba675SRob Herring }; 1465724ba675SRob Herring 14661f02c9fbSSvyatoslav Ryhel /* smps6 disabled */ 1467724ba675SRob Herring 14681f02c9fbSSvyatoslav Ryhel vddio_ddr: smps7 { 14691f02c9fbSSvyatoslav Ryhel regulator-name = "vddio_ddr"; 1470724ba675SRob Herring regulator-min-microvolt = <1350000>; 1471724ba675SRob Herring regulator-max-microvolt = <1350000>; 1472724ba675SRob Herring regulator-always-on; 1473724ba675SRob Herring regulator-boot-on; 1474724ba675SRob Herring }; 1475724ba675SRob Herring 14761f02c9fbSSvyatoslav Ryhel vdd_1v8_vio: smps8 { 14771f02c9fbSSvyatoslav Ryhel regulator-name = "vdd_1v8"; 1478724ba675SRob Herring regulator-min-microvolt = <1800000>; 1479724ba675SRob Herring regulator-max-microvolt = <1800000>; 1480724ba675SRob Herring regulator-always-on; 1481724ba675SRob Herring regulator-boot-on; 1482724ba675SRob Herring }; 1483724ba675SRob Herring 14841f02c9fbSSvyatoslav Ryhel vcore_emmc: smps9 { 14851f02c9fbSSvyatoslav Ryhel regulator-name = "vdd_emmc"; 1486724ba675SRob Herring regulator-min-microvolt = <2900000>; 1487724ba675SRob Herring regulator-max-microvolt = <2900000>; 14881f02c9fbSSvyatoslav Ryhel regulator-boot-on; 1489724ba675SRob Herring }; 1490724ba675SRob Herring 14911f02c9fbSSvyatoslav Ryhel smps10_out1 { 14921f02c9fbSSvyatoslav Ryhel regulator-name = "vd_smps10_out1"; 1493724ba675SRob Herring regulator-min-microvolt = <5000000>; 1494724ba675SRob Herring regulator-max-microvolt = <5000000>; 1495724ba675SRob Herring regulator-always-on; 1496724ba675SRob Herring regulator-boot-on; 1497724ba675SRob Herring }; 1498724ba675SRob Herring 14991f02c9fbSSvyatoslav Ryhel vdd_smps10_out2: smps10_out2 { 15001f02c9fbSSvyatoslav Ryhel regulator-name = "vd_smps10_out2"; 1501724ba675SRob Herring regulator-min-microvolt = <5000000>; 1502724ba675SRob Herring regulator-max-microvolt = <5000000>; 1503724ba675SRob Herring regulator-always-on; 1504724ba675SRob Herring regulator-boot-on; 1505724ba675SRob Herring }; 1506724ba675SRob Herring 15071f02c9fbSSvyatoslav Ryhel avdd_hdmi_pll: ldo1 { 15081f02c9fbSSvyatoslav Ryhel regulator-name = "avdd_hdmi_pll"; 1509724ba675SRob Herring regulator-min-microvolt = <1050000>; 1510724ba675SRob Herring regulator-max-microvolt = <1050000>; 1511724ba675SRob Herring regulator-always-on; 15121f02c9fbSSvyatoslav Ryhel regulator-boot-on; 1513724ba675SRob Herring ti,roof-floor = <3>; 1514724ba675SRob Herring }; 1515724ba675SRob Herring 15161f02c9fbSSvyatoslav Ryhel avdd_dsi_csi: ldo2 { 15171f02c9fbSSvyatoslav Ryhel regulator-name = "avdd_dsi_csi"; 1518724ba675SRob Herring regulator-min-microvolt = <1200000>; 1519724ba675SRob Herring regulator-max-microvolt = <1200000>; 1520724ba675SRob Herring regulator-boot-on; 1521724ba675SRob Herring }; 1522724ba675SRob Herring 1523724ba675SRob Herring ldo3 { 15241f02c9fbSSvyatoslav Ryhel regulator-name = "vpp_fuse"; 1525724ba675SRob Herring regulator-min-microvolt = <1800000>; 1526724ba675SRob Herring regulator-max-microvolt = <1800000>; 1527724ba675SRob Herring }; 1528724ba675SRob Herring 15291f02c9fbSSvyatoslav Ryhel vdd_1v2_cam: ldo4 { 15301f02c9fbSSvyatoslav Ryhel regulator-name = "vdd_1v2_cam"; 1531724ba675SRob Herring regulator-min-microvolt = <1200000>; 1532724ba675SRob Herring regulator-max-microvolt = <1200000>; 1533724ba675SRob Herring }; 1534724ba675SRob Herring 15351f02c9fbSSvyatoslav Ryhel avdd_2v8_cam: ldo5 { 15361f02c9fbSSvyatoslav Ryhel regulator-name = "avdd_cam2"; 1537724ba675SRob Herring regulator-min-microvolt = <2800000>; 1538724ba675SRob Herring regulator-max-microvolt = <2800000>; 1539724ba675SRob Herring }; 1540724ba675SRob Herring 15411f02c9fbSSvyatoslav Ryhel vdd_2v85_sen: ldo6 { 15421f02c9fbSSvyatoslav Ryhel regulator-name = "vdd_dev"; 1543724ba675SRob Herring regulator-min-microvolt = <2850000>; 1544724ba675SRob Herring regulator-max-microvolt = <2850000>; 1545724ba675SRob Herring }; 1546724ba675SRob Herring 15471f02c9fbSSvyatoslav Ryhel avdd_2v8_af: ldo7 { 15481f02c9fbSSvyatoslav Ryhel regulator-name = "avdd_2v8_cam"; 1549724ba675SRob Herring regulator-min-microvolt = <2800000>; 1550724ba675SRob Herring regulator-max-microvolt = <2800000>; 1551724ba675SRob Herring }; 1552724ba675SRob Herring 15531f02c9fbSSvyatoslav Ryhel ldo8 { 15541f02c9fbSSvyatoslav Ryhel regulator-name = "vdd_rtc"; 1555724ba675SRob Herring regulator-min-microvolt = <950000>; 1556724ba675SRob Herring regulator-max-microvolt = <950000>; 1557724ba675SRob Herring regulator-always-on; 1558724ba675SRob Herring regulator-boot-on; 1559724ba675SRob Herring ti,enable-ldo8-tracking; 1560724ba675SRob Herring }; 1561724ba675SRob Herring 15621f02c9fbSSvyatoslav Ryhel vddio_usd: ldo9 { 15631f02c9fbSSvyatoslav Ryhel regulator-name = "vddio_usd"; 15641f02c9fbSSvyatoslav Ryhel /* min voltage of 1.8v is not stable */ 15651f02c9fbSSvyatoslav Ryhel regulator-min-microvolt = <2900000>; 1566724ba675SRob Herring regulator-max-microvolt = <2900000>; 1567724ba675SRob Herring }; 1568724ba675SRob Herring 15691f02c9fbSSvyatoslav Ryhel avdd_hdmi: ldoln { 15701f02c9fbSSvyatoslav Ryhel regulator-name = "avdd_hdmi"; 1571724ba675SRob Herring regulator-min-microvolt = <3300000>; 1572724ba675SRob Herring regulator-max-microvolt = <3300000>; 15731f02c9fbSSvyatoslav Ryhel regulator-boot-on; 1574724ba675SRob Herring }; 1575724ba675SRob Herring 15761f02c9fbSSvyatoslav Ryhel avdd_usb: ldousb { 15771f02c9fbSSvyatoslav Ryhel regulator-name = "avdd_usb"; 1578724ba675SRob Herring regulator-min-microvolt = <3300000>; 1579724ba675SRob Herring regulator-max-microvolt = <3300000>; 1580724ba675SRob Herring regulator-boot-on; 1581724ba675SRob Herring }; 1582724ba675SRob Herring }; 1583724ba675SRob Herring }; 1584724ba675SRob Herring 1585724ba675SRob Herring rtc { 1586724ba675SRob Herring compatible = "ti,palmas-rtc"; 1587724ba675SRob Herring interrupt-parent = <&palmas>; 15881f02c9fbSSvyatoslav Ryhel interrupts = <8 IRQ_TYPE_NONE>; 1589724ba675SRob Herring }; 1590724ba675SRob Herring }; 1591724ba675SRob Herring }; 1592724ba675SRob Herring 15931f02c9fbSSvyatoslav Ryhel pmc@7000e400 { 15941f02c9fbSSvyatoslav Ryhel status = "okay"; 15951f02c9fbSSvyatoslav Ryhel nvidia,suspend-mode = <2>; 15961f02c9fbSSvyatoslav Ryhel nvidia,cpu-pwr-good-time = <300>; 15971f02c9fbSSvyatoslav Ryhel nvidia,cpu-pwr-off-time = <300>; 15981f02c9fbSSvyatoslav Ryhel nvidia,core-pwr-good-time = <641 3845>; 15991f02c9fbSSvyatoslav Ryhel nvidia,core-pwr-off-time = <2000>; 16001f02c9fbSSvyatoslav Ryhel nvidia,core-power-req-active-high; 16011f02c9fbSSvyatoslav Ryhel nvidia,sys-clock-req-active-high; 16021f02c9fbSSvyatoslav Ryhel 16031f02c9fbSSvyatoslav Ryhel /* Clear DEV_ON bit in DEV_CTRL register of TPS65913 PMIC */ 16041f02c9fbSSvyatoslav Ryhel i2c-thermtrip { 16051f02c9fbSSvyatoslav Ryhel nvidia,i2c-controller-id = <4>; 16061f02c9fbSSvyatoslav Ryhel nvidia,bus-addr = <0x58>; 16071f02c9fbSSvyatoslav Ryhel nvidia,reg-addr = <0xA0>; 16081f02c9fbSSvyatoslav Ryhel nvidia,reg-data = <0x00>; 16091f02c9fbSSvyatoslav Ryhel }; 16101f02c9fbSSvyatoslav Ryhel }; 16111f02c9fbSSvyatoslav Ryhel 1612724ba675SRob Herring ahub@70080000 { 1613e4cee354SSvyatoslav Ryhel /* HIFI CODEC (i2s1) */ 1614e4cee354SSvyatoslav Ryhel i2s@70080400 { 1615e4cee354SSvyatoslav Ryhel status = "okay"; 1616e4cee354SSvyatoslav Ryhel }; 1617e4cee354SSvyatoslav Ryhel 1618e4cee354SSvyatoslav Ryhel /* BT SCO (i2s3) */ 1619e4cee354SSvyatoslav Ryhel i2s@70080600 { 1620724ba675SRob Herring status = "okay"; 1621724ba675SRob Herring }; 1622724ba675SRob Herring }; 1623724ba675SRob Herring 16241731cbbaSSvyatoslav Ryhel brcm_wifi_pwrseq: pwrseq-wifi { 16251731cbbaSSvyatoslav Ryhel compatible = "mmc-pwrseq-simple"; 16261731cbbaSSvyatoslav Ryhel 16271731cbbaSSvyatoslav Ryhel clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; 16281731cbbaSSvyatoslav Ryhel clock-names = "ext_clock"; 16291731cbbaSSvyatoslav Ryhel 16301731cbbaSSvyatoslav Ryhel reset-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; 16311731cbbaSSvyatoslav Ryhel post-power-on-delay-ms = <300>; 16321731cbbaSSvyatoslav Ryhel power-off-delay-us = <300>; 16331731cbbaSSvyatoslav Ryhel }; 16341731cbbaSSvyatoslav Ryhel 1635724ba675SRob Herring /* WiFi */ 16361731cbbaSSvyatoslav Ryhel mmc@78000000 { 16371731cbbaSSvyatoslav Ryhel status = "okay"; 16381731cbbaSSvyatoslav Ryhel 16391731cbbaSSvyatoslav Ryhel #address-cells = <1>; 16401731cbbaSSvyatoslav Ryhel #size-cells = <0>; 16411731cbbaSSvyatoslav Ryhel 16421731cbbaSSvyatoslav Ryhel assigned-clocks = <&tegra_car TEGRA114_CLK_SDMMC1>; 16431731cbbaSSvyatoslav Ryhel assigned-clock-parents = <&tegra_car TEGRA114_CLK_PLL_P>; 16441731cbbaSSvyatoslav Ryhel assigned-clock-rates = <82000000>; 16451731cbbaSSvyatoslav Ryhel 16461731cbbaSSvyatoslav Ryhel max-frequency = <82000000>; 16471731cbbaSSvyatoslav Ryhel keep-power-in-suspend; 16481731cbbaSSvyatoslav Ryhel bus-width = <4>; 16491731cbbaSSvyatoslav Ryhel non-removable; 16501731cbbaSSvyatoslav Ryhel 16511731cbbaSSvyatoslav Ryhel sd-uhs-ddr50; 16521731cbbaSSvyatoslav Ryhel mmc-ddr-1_8v; 16531731cbbaSSvyatoslav Ryhel 16541731cbbaSSvyatoslav Ryhel power-gpios = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_HIGH>; 16551731cbbaSSvyatoslav Ryhel 16561731cbbaSSvyatoslav Ryhel nvidia,default-tap = <0x2>; 16571731cbbaSSvyatoslav Ryhel nvidia,default-trim = <0x2>; 16581731cbbaSSvyatoslav Ryhel 16591731cbbaSSvyatoslav Ryhel mmc-pwrseq = <&brcm_wifi_pwrseq>; 16601731cbbaSSvyatoslav Ryhel vmmc-supply = <&vdd_3v3_com>; 16611731cbbaSSvyatoslav Ryhel vqmmc-supply = <&vdd_1v8_vio>; 16621731cbbaSSvyatoslav Ryhel 16631731cbbaSSvyatoslav Ryhel wifi@1 { 16641731cbbaSSvyatoslav Ryhel compatible = "brcm,bcm4329-fmac"; 16651731cbbaSSvyatoslav Ryhel reg = <1>; 16661731cbbaSSvyatoslav Ryhel 16671731cbbaSSvyatoslav Ryhel interrupt-parent = <&gpio>; 16681731cbbaSSvyatoslav Ryhel interrupts = <TEGRA_GPIO(U, 5) IRQ_TYPE_LEVEL_HIGH>; 16691731cbbaSSvyatoslav Ryhel interrupt-names = "host-wake"; 16701731cbbaSSvyatoslav Ryhel }; 1671724ba675SRob Herring }; 1672724ba675SRob Herring 1673724ba675SRob Herring /* MicroSD card */ 1674724ba675SRob Herring mmc@78000400 { 1675724ba675SRob Herring status = "okay"; 1676724ba675SRob Herring 1677724ba675SRob Herring bus-width = <4>; 1678724ba675SRob Herring cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; 1679724ba675SRob Herring 1680724ba675SRob Herring nvidia,default-tap = <0x3>; 1681724ba675SRob Herring nvidia,default-trim = <0x3>; 1682724ba675SRob Herring 16831f02c9fbSSvyatoslav Ryhel vmmc-supply = <&vdd_2v9_usd>; 16841f02c9fbSSvyatoslav Ryhel vqmmc-supply = <&vddio_usd>; 1685724ba675SRob Herring }; 1686724ba675SRob Herring 1687724ba675SRob Herring /* eMMC */ 16881731cbbaSSvyatoslav Ryhel mmc@78000600 { 16891731cbbaSSvyatoslav Ryhel status = "okay"; 16901731cbbaSSvyatoslav Ryhel bus-width = <8>; 16911731cbbaSSvyatoslav Ryhel 16921731cbbaSSvyatoslav Ryhel non-removable; 16931731cbbaSSvyatoslav Ryhel mmc-ddr-1_8v; 16941731cbbaSSvyatoslav Ryhel 16951731cbbaSSvyatoslav Ryhel vmmc-supply = <&vcore_emmc>; 16961731cbbaSSvyatoslav Ryhel vqmmc-supply = <&vdd_1v8_vio>; 1697724ba675SRob Herring }; 1698724ba675SRob Herring 1699*c6d17e1aSSvyatoslav Ryhel /* Peripheral USB via ASUS connector */ 1700724ba675SRob Herring usb@7d000000 { 1701724ba675SRob Herring compatible = "nvidia,tegra114-udc"; 1702724ba675SRob Herring status = "okay"; 1703724ba675SRob Herring dr_mode = "peripheral"; 1704724ba675SRob Herring }; 1705724ba675SRob Herring 1706724ba675SRob Herring usb-phy@7d000000 { 1707724ba675SRob Herring status = "okay"; 1708*c6d17e1aSSvyatoslav Ryhel dr_mode = "peripheral"; 1709*c6d17e1aSSvyatoslav Ryhel vbus-supply = <&avdd_usb>; 1710724ba675SRob Herring }; 1711724ba675SRob Herring 1712*c6d17e1aSSvyatoslav Ryhel /* Host USB via dock */ 1713724ba675SRob Herring usb@7d008000 { 1714724ba675SRob Herring status = "okay"; 1715724ba675SRob Herring }; 1716724ba675SRob Herring 1717724ba675SRob Herring usb-phy@7d008000 { 1718724ba675SRob Herring status = "okay"; 1719724ba675SRob Herring vbus-supply = <&vdd_5v0_sys>; 1720724ba675SRob Herring }; 1721724ba675SRob Herring 1722724ba675SRob Herring backlight: backlight { 1723724ba675SRob Herring compatible = "pwm-backlight"; 1724724ba675SRob Herring 17258c80f441SSvyatoslav Ryhel power-supply = <&vdd_3v7_bl>; 1726724ba675SRob Herring pwms = <&pwm 1 1000000>; 1727724ba675SRob Herring 1728724ba675SRob Herring brightness-levels = <1 255>; 1729724ba675SRob Herring num-interpolated-steps = <254>; 1730724ba675SRob Herring default-brightness-level = <224>; 1731724ba675SRob Herring }; 1732724ba675SRob Herring 1733724ba675SRob Herring /* PMIC has a built-in 32KHz oscillator which is used by PMC */ 1734724ba675SRob Herring clk32k_in: clock-32k { 1735724ba675SRob Herring compatible = "fixed-clock"; 1736724ba675SRob Herring #clock-cells = <0>; 1737724ba675SRob Herring clock-frequency = <32768>; 1738724ba675SRob Herring clock-output-names = "pmic-oscillator"; 1739724ba675SRob Herring }; 1740724ba675SRob Herring 1741fceb6acdSSvyatoslav Ryhel connector { 1742fceb6acdSSvyatoslav Ryhel compatible = "hdmi-connector"; 1743fceb6acdSSvyatoslav Ryhel type = "d"; 1744fceb6acdSSvyatoslav Ryhel 1745fceb6acdSSvyatoslav Ryhel hpd-gpios = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; 1746fceb6acdSSvyatoslav Ryhel ddc-i2c-bus = <&hdmi_ddc>; 1747fceb6acdSSvyatoslav Ryhel 1748fceb6acdSSvyatoslav Ryhel port { 1749fceb6acdSSvyatoslav Ryhel connector_in: endpoint { 1750fceb6acdSSvyatoslav Ryhel remote-endpoint = <&hdmi_out>; 1751fceb6acdSSvyatoslav Ryhel }; 1752fceb6acdSSvyatoslav Ryhel }; 1753fceb6acdSSvyatoslav Ryhel }; 1754fceb6acdSSvyatoslav Ryhel 1755003b99aaSSvyatoslav Ryhel extcon-keys { 1756724ba675SRob Herring compatible = "gpio-keys"; 1757724ba675SRob Herring 1758724ba675SRob Herring switch-hall-sensor { 1759724ba675SRob Herring label = "Hall Effect Sensor"; 1760724ba675SRob Herring gpios = <&gpio TEGRA_GPIO(O, 5) GPIO_ACTIVE_LOW>; 1761724ba675SRob Herring linux,input-type = <EV_SW>; 1762724ba675SRob Herring linux,code = <SW_LID>; 1763724ba675SRob Herring linux,can-disable; 1764724ba675SRob Herring wakeup-source; 1765724ba675SRob Herring }; 1766003b99aaSSvyatoslav Ryhel 1767003b99aaSSvyatoslav Ryhel switch-lineout-detect { 1768003b99aaSSvyatoslav Ryhel label = "Audio dock line-out detect"; 1769003b99aaSSvyatoslav Ryhel gpios = <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_LOW>; 1770003b99aaSSvyatoslav Ryhel linux,input-type = <EV_SW>; 1771003b99aaSSvyatoslav Ryhel linux,code = <SW_LINEOUT_INSERT>; 1772003b99aaSSvyatoslav Ryhel debounce-interval = <10>; 1773003b99aaSSvyatoslav Ryhel }; 1774724ba675SRob Herring }; 1775724ba675SRob Herring 1776724ba675SRob Herring gpio-keys { 1777724ba675SRob Herring compatible = "gpio-keys"; 1778724ba675SRob Herring 1779003b99aaSSvyatoslav Ryhel key-power { 1780724ba675SRob Herring label = "Power"; 1781724ba675SRob Herring gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; 1782724ba675SRob Herring linux,code = <KEY_POWER>; 1783724ba675SRob Herring debounce-interval = <10>; 1784724ba675SRob Herring wakeup-source; 1785724ba675SRob Herring }; 1786724ba675SRob Herring 1787003b99aaSSvyatoslav Ryhel key-volume-down { 1788724ba675SRob Herring label = "Volume Down"; 1789724ba675SRob Herring gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; 1790724ba675SRob Herring linux,code = <KEY_VOLUMEDOWN>; 1791724ba675SRob Herring debounce-interval = <10>; 1792724ba675SRob Herring }; 1793724ba675SRob Herring 1794003b99aaSSvyatoslav Ryhel key-volume-up { 1795724ba675SRob Herring label = "Volume Up"; 1796724ba675SRob Herring gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; 1797724ba675SRob Herring linux,code = <KEY_VOLUMEUP>; 1798724ba675SRob Herring debounce-interval = <10>; 1799724ba675SRob Herring }; 1800724ba675SRob Herring }; 1801724ba675SRob Herring 1802724ba675SRob Herring sound { 1803724ba675SRob Herring compatible = "asus,tegra-audio-rt5639-tf701t", 1804724ba675SRob Herring "nvidia,tegra-audio-rt5640"; 1805724ba675SRob Herring nvidia,model = "Asus Transformer Pad TF701T RT5639"; 1806724ba675SRob Herring 1807724ba675SRob Herring nvidia,audio-routing = 1808724ba675SRob Herring "Headphones", "HPOR", 1809724ba675SRob Herring "Headphones", "HPOL", 1810724ba675SRob Herring "Speakers", "SPORP", 1811724ba675SRob Herring "Speakers", "SPORN", 1812724ba675SRob Herring "Speakers", "SPOLP", 1813724ba675SRob Herring "Speakers", "SPOLN", 1814e4cee354SSvyatoslav Ryhel "IN1P", "Mic Jack", 1815e4cee354SSvyatoslav Ryhel "IN1N", "Mic Jack", 1816e4cee354SSvyatoslav Ryhel "DMIC1", "Int Mic", 1817e4cee354SSvyatoslav Ryhel "DMIC2", "Int Mic"; 1818724ba675SRob Herring 1819e4cee354SSvyatoslav Ryhel nvidia,i2s-controller = <&tegra_i2s1>; 1820724ba675SRob Herring nvidia,audio-codec = <&rt5639>; 1821724ba675SRob Herring 1822724ba675SRob Herring nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_LOW>; 1823e4cee354SSvyatoslav Ryhel nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_HIGH>; 1824724ba675SRob Herring 1825724ba675SRob Herring clocks = <&tegra_car TEGRA114_CLK_PLL_A>, 1826724ba675SRob Herring <&tegra_car TEGRA114_CLK_PLL_A_OUT0>, 1827724ba675SRob Herring <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; 1828724ba675SRob Herring clock-names = "pll_a", "pll_a_out0", "mclk"; 1829724ba675SRob Herring 1830724ba675SRob Herring assigned-clocks = <&tegra_car TEGRA114_CLK_EXTERN1>, 1831724ba675SRob Herring <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; 1832724ba675SRob Herring 1833724ba675SRob Herring assigned-clock-parents = <&tegra_car TEGRA114_CLK_PLL_A_OUT0>, 1834724ba675SRob Herring <&tegra_car TEGRA114_CLK_EXTERN1>; 1835724ba675SRob Herring }; 1836724ba675SRob Herring 1837724ba675SRob Herring vdd_5v0_sys: regulator-5v0-sys { 1838724ba675SRob Herring compatible = "regulator-fixed"; 18391f02c9fbSSvyatoslav Ryhel regulator-name = "vdd_5v0_sys"; 1840724ba675SRob Herring regulator-min-microvolt = <5000000>; 1841724ba675SRob Herring regulator-max-microvolt = <5000000>; 1842724ba675SRob Herring regulator-always-on; 1843724ba675SRob Herring regulator-boot-on; 1844724ba675SRob Herring }; 1845724ba675SRob Herring 1846724ba675SRob Herring vdd_3v3_sys: regulator-3v3-sys { 1847724ba675SRob Herring compatible = "regulator-fixed"; 18481f02c9fbSSvyatoslav Ryhel regulator-name = "vdd_3v3_sys"; 1849724ba675SRob Herring regulator-min-microvolt = <3300000>; 1850724ba675SRob Herring regulator-max-microvolt = <3300000>; 1851724ba675SRob Herring regulator-always-on; 1852724ba675SRob Herring regulator-boot-on; 1853724ba675SRob Herring }; 1854724ba675SRob Herring 18551f02c9fbSSvyatoslav Ryhel dvdd_1v8_lcd: regulator-vdd-lcd { 1856724ba675SRob Herring compatible = "regulator-fixed"; 18571f02c9fbSSvyatoslav Ryhel regulator-name = "dvdd_1v8_lcd"; 1858724ba675SRob Herring regulator-min-microvolt = <1800000>; 1859724ba675SRob Herring regulator-max-microvolt = <1800000>; 1860724ba675SRob Herring regulator-boot-on; 18611f02c9fbSSvyatoslav Ryhel gpio = <&palmas_gpio 4 GPIO_ACTIVE_HIGH>; 18621f02c9fbSSvyatoslav Ryhel enable-active-high; 18631f02c9fbSSvyatoslav Ryhel vin-supply = <&vdd_1v8_vio>; 1864724ba675SRob Herring }; 1865724ba675SRob Herring 18661f02c9fbSSvyatoslav Ryhel vdd_3v7_bl: regulator-bl-en { 18671f02c9fbSSvyatoslav Ryhel compatible = "regulator-fixed"; 18681f02c9fbSSvyatoslav Ryhel regulator-name = "vdd_3v7_bl"; 18691f02c9fbSSvyatoslav Ryhel regulator-min-microvolt = <3700000>; 18701f02c9fbSSvyatoslav Ryhel regulator-max-microvolt = <3700000>; 18711f02c9fbSSvyatoslav Ryhel regulator-boot-on; 18721f02c9fbSSvyatoslav Ryhel gpio = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; 18731f02c9fbSSvyatoslav Ryhel enable-active-high; 18741f02c9fbSSvyatoslav Ryhel vin-supply = <&vdd_5v0_sys>; 18751f02c9fbSSvyatoslav Ryhel }; 18761f02c9fbSSvyatoslav Ryhel 18771f02c9fbSSvyatoslav Ryhel hdmi_5v0_sys: regulator-hdmi { 18781f02c9fbSSvyatoslav Ryhel compatible = "regulator-fixed"; 18791f02c9fbSSvyatoslav Ryhel regulator-name = "vdd_5v0_hdmi"; 18801f02c9fbSSvyatoslav Ryhel regulator-min-microvolt = <5000000>; 18811f02c9fbSSvyatoslav Ryhel regulator-max-microvolt = <5000000>; 18821f02c9fbSSvyatoslav Ryhel regulator-boot-on; 18831f02c9fbSSvyatoslav Ryhel gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; 18841f02c9fbSSvyatoslav Ryhel enable-active-high; 18851f02c9fbSSvyatoslav Ryhel vin-supply = <&vdd_smps10_out2>; 18861f02c9fbSSvyatoslav Ryhel }; 18871f02c9fbSSvyatoslav Ryhel 18881f02c9fbSSvyatoslav Ryhel vdd_2v9_usd: regulator-vdd-usd { 1889724ba675SRob Herring compatible = "regulator-fixed"; 1890724ba675SRob Herring regulator-name = "vdd_sd_slot"; 1891724ba675SRob Herring regulator-min-microvolt = <2900000>; 1892724ba675SRob Herring regulator-max-microvolt = <2900000>; 18931f02c9fbSSvyatoslav Ryhel regulator-boot-on; 1894724ba675SRob Herring gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; 18951f02c9fbSSvyatoslav Ryhel enable-active-high; 18961f02c9fbSSvyatoslav Ryhel vin-supply = <&vcore_emmc>; 18971f02c9fbSSvyatoslav Ryhel }; 18981f02c9fbSSvyatoslav Ryhel 18991f02c9fbSSvyatoslav Ryhel vdd_1v8_cam: regulator-cam-vio { 19001f02c9fbSSvyatoslav Ryhel compatible = "regulator-fixed"; 19011f02c9fbSSvyatoslav Ryhel regulator-name = "vdd_1v8_cam"; 19021f02c9fbSSvyatoslav Ryhel regulator-min-microvolt = <1800000>; 19031f02c9fbSSvyatoslav Ryhel regulator-max-microvolt = <1800000>; 19041f02c9fbSSvyatoslav Ryhel regulator-boot-on; 19051f02c9fbSSvyatoslav Ryhel gpio = <&palmas_gpio 6 GPIO_ACTIVE_HIGH>; 19061f02c9fbSSvyatoslav Ryhel enable-active-high; 19071f02c9fbSSvyatoslav Ryhel vin-supply = <&vdd_1v8_vio>; 19081f02c9fbSSvyatoslav Ryhel }; 19091f02c9fbSSvyatoslav Ryhel 19101f02c9fbSSvyatoslav Ryhel vdd_1v2_xusb: regulator-xusb-vio { 19111f02c9fbSSvyatoslav Ryhel compatible = "regulator-fixed"; 19121f02c9fbSSvyatoslav Ryhel regulator-name = "avddio_1v2_xusb"; 19131f02c9fbSSvyatoslav Ryhel regulator-min-microvolt = <1200000>; 19141f02c9fbSSvyatoslav Ryhel regulator-max-microvolt = <1200000>; 19151f02c9fbSSvyatoslav Ryhel regulator-boot-on; 19161f02c9fbSSvyatoslav Ryhel gpio = <&palmas_gpio 3 GPIO_ACTIVE_HIGH>; 19171f02c9fbSSvyatoslav Ryhel enable-active-high; 19181f02c9fbSSvyatoslav Ryhel }; 19191f02c9fbSSvyatoslav Ryhel 19201f02c9fbSSvyatoslav Ryhel vdd_3v3_xusb: regulator-xusb-vdd { 19211f02c9fbSSvyatoslav Ryhel compatible = "regulator-fixed"; 19221f02c9fbSSvyatoslav Ryhel regulator-name = "hvdd_3v3_xusb"; 19231f02c9fbSSvyatoslav Ryhel regulator-min-microvolt = <3300000>; 19241f02c9fbSSvyatoslav Ryhel regulator-max-microvolt = <3300000>; 19251f02c9fbSSvyatoslav Ryhel regulator-boot-on; 19261f02c9fbSSvyatoslav Ryhel gpio = <&palmas_gpio 1 GPIO_ACTIVE_HIGH>; 19271f02c9fbSSvyatoslav Ryhel enable-active-high; 19281f02c9fbSSvyatoslav Ryhel }; 19291f02c9fbSSvyatoslav Ryhel 19301f02c9fbSSvyatoslav Ryhel vdd_3v3_com: regulator-com { 19311f02c9fbSSvyatoslav Ryhel compatible = "regulator-fixed"; 19321f02c9fbSSvyatoslav Ryhel regulator-name = "vdd_3v3_com"; 19331f02c9fbSSvyatoslav Ryhel regulator-min-microvolt = <3300000>; 19341f02c9fbSSvyatoslav Ryhel regulator-max-microvolt = <3300000>; 19351f02c9fbSSvyatoslav Ryhel regulator-always-on; 19361f02c9fbSSvyatoslav Ryhel regulator-boot-on; 19371f02c9fbSSvyatoslav Ryhel gpio = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>; 19381f02c9fbSSvyatoslav Ryhel enable-active-high; 19391f02c9fbSSvyatoslav Ryhel vin-supply = <&vdd_3v3_sys>; 19401f02c9fbSSvyatoslav Ryhel }; 19411f02c9fbSSvyatoslav Ryhel 19421f02c9fbSSvyatoslav Ryhel vdd_3v3_touch: regulator-touch-pwr { 19431f02c9fbSSvyatoslav Ryhel compatible = "regulator-fixed"; 19441f02c9fbSSvyatoslav Ryhel regulator-name = "vdd_3v3_touch"; 19451f02c9fbSSvyatoslav Ryhel regulator-min-microvolt = <3300000>; 19461f02c9fbSSvyatoslav Ryhel regulator-max-microvolt = <3300000>; 19471f02c9fbSSvyatoslav Ryhel regulator-boot-on; 19481f02c9fbSSvyatoslav Ryhel gpio = <&gpio TEGRA_GPIO(H, 0) GPIO_ACTIVE_HIGH>; 19491f02c9fbSSvyatoslav Ryhel enable-active-high; 19501f02c9fbSSvyatoslav Ryhel vin-supply = <&vdd_3v3_sys>; 19511f02c9fbSSvyatoslav Ryhel }; 19521f02c9fbSSvyatoslav Ryhel 19531f02c9fbSSvyatoslav Ryhel vdd_1v8_touch: regulator-touch-vio { 19541f02c9fbSSvyatoslav Ryhel compatible = "regulator-fixed"; 19551f02c9fbSSvyatoslav Ryhel regulator-name = "vdd_1v8_touch"; 19561f02c9fbSSvyatoslav Ryhel regulator-min-microvolt = <1800000>; 19571f02c9fbSSvyatoslav Ryhel regulator-max-microvolt = <1800000>; 19581f02c9fbSSvyatoslav Ryhel regulator-boot-on; 19591f02c9fbSSvyatoslav Ryhel gpio = <&gpio TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>; 19601f02c9fbSSvyatoslav Ryhel enable-active-high; 19611f02c9fbSSvyatoslav Ryhel vin-supply = <&vdd_3v3_sys>; 1962724ba675SRob Herring }; 1963724ba675SRob Herring}; 1964