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/linux/Documentation/devicetree/bindings/clock/
H A Dallwinner,sun6i-a31-pll6-clk.yaml4 $id: http://devicetree.org/schemas/clock/allwinner,sun6i-a31-pll6-clk.yaml#
23 const: allwinner,sun6i-a31-pll6-clk
47 compatible = "allwinner,sun6i-a31-pll6-clk";
50 clock-output-names = "pll6", "pll6x2";
H A Dallwinner,sun4i-a10-pll6-clk.yaml4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll6-clk.yaml#
23 const: allwinner,sun4i-a10-pll6-clk
47 compatible = "allwinner,sun4i-a10-pll6-clk";
50 clock-output-names = "pll6_sata", "pll6_other", "pll6";
H A Dallwinner,sun4i-a10-mbus-clk.yaml50 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
59 clocks = <&osc24M>, <&pll6 1>, <&pll5>;
H A Dallwinner,sun4i-a10-usb-clk.yaml116 clocks = <&pll6 1>;
126 clocks = <&pll6 1>;
H A Dallwinner,sun5i-a13-ahb-clk.yaml48 clocks = <&axi>, <&cpu>, <&pll6 1>;
H A Dallwinner,sun4i-a10-apb1-clk.yaml48 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
H A Dallwinner,sun4i-a10-mmc-clk.yaml71 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
H A Dallwinner,sun4i-a10-mod0-clk.yaml67 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
H A Dallwinner,sun4i-a10-ahb-clk.yaml95 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
/linux/drivers/clk/sunxi/
H A Dclk-sunxi.c259 * can work at speeds up to 300M, just after reparenting to pll6 in sun5i_a13_get_ahb_factors()
284 * if parent is pll6, then
285 * parent_rate = pll6 rate / (m + 1)
301 /* calculate pre-divider if parent is pll6 */ in sun6i_get_ahb1_factors()
331 /* apply pre-divider first if parent is pll6 */ in sun6i_ahb1_recalc()
908 { .fixed = 4 }, /* pll6 / 4, used as ahb input */
1110 CLK_OF_DECLARE(sun4i_pll6, "allwinner,sun4i-a10-pll6-clk",
1117 CLK_OF_DECLARE(sun6i_pll6, "allwinner,sun6i-a31-pll6-clk",
H A Dclk-factors.c195 * some factor clocks, such as pll5 and pll6, may have multiple in __sunxi_factors_register()
/linux/Documentation/devicetree/bindings/ata/
H A Dallwinner,sun4i-a10-ahci.yaml45 clocks = <&pll6 0>, <&ahb_gates 25>;
/linux/drivers/clk/renesas/
H A Dr8a779f0-cpg-mssr.c65 DEF_GEN4_PLL_V9_24(".pll6", 6, CLK_PLL6, CLK_MAIN),
179 * MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC
H A Dr9a07g044-cpg.c110 static const char * const sel_gpu2[] = { ".pll6", ".pll3_div2_2" };
137 DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6),
H A Dr9a07g043-cpg.c127 DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6),
/linux/drivers/clk/
H A Dclk-milbeaut.c23 #define M10V_PLL6 "pll6"
24 #define M10V_PLL6DIV2 "pll6-2"
25 #define M10V_PLL6DIV3 "pll6-3"
/linux/include/dt-bindings/clock/
H A Dqcom,gcc-msm8660.h259 #define PLL6 250 macro
H A Dqcom,gcc-mdm9615.h293 #define PLL6 283 macro
H A Dqcom,gcc-msm8960.h291 #define PLL6 283 macro
/linux/drivers/clk/imx/
H A Dclk-imx6sll.c28 static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", };
128 …hws[IMX6SLL_CLK_PLL6] = imx_clk_hw_pllv3(IMX_PLLV3_ENET, "pll6", "pll6_bypass_src", base + 0xe0, … in imx6sll_clocks_init()
H A Dclk-vf610.c82 static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", };
224 clk[VF610_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_AV, "pll6", "pll6_bypass_src", PLL6_CTRL, 0x7f); in vf610_clocks_init()
H A Dclk-imx6sl.c69 static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", };
222 hws[IMX6SL_CLK_PLL6] = imx_clk_hw_pllv3(IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3); in imx6sl_clocks_init()
/linux/drivers/gpu/drm/i915/display/
H A Dintel_dpll_mgr.h209 u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12; member
H A Dintel_dpll_mgr.c2092 temp |= hw_state->pll6; in bxt_ddi_pll_enable()
2204 hw_state->pll6 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 6)); in bxt_ddi_pll_get_hw_state()
2205 hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK | in bxt_ddi_pll_get_hw_state()
2343 hw_state->pll6 = PORT_PLL_PROP_COEFF(prop_coef) | in bxt_ddi_set_dpll_hw_state()
2463 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n", in bxt_dump_hw_state()
2466 hw_state->pll6, hw_state->pll8, hw_state->pll9, hw_state->pll10, in bxt_dump_hw_state()
2482 a->pll6 == b->pll6 && in bxt_compare_hw_state()
/linux/drivers/clk/sunxi-ng/
H A Dccu-sun6i-a31.c1250 /* Force AHB1 to PLL6 / 3 */ in sun6i_a31_ccu_probe()
1252 /* set PLL6 pre-div = 3 */ in sun6i_a31_ccu_probe()
1255 /* select PLL6 / pre-div */ in sun6i_a31_ccu_probe()

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