xref: /linux/Documentation/devicetree/bindings/clock/allwinner,sun6i-a31-pll6-clk.yaml (revision 4f2c0a4acffbec01079c28f839422e64ddeff004)
1f95cad74SMaxime Ripard# SPDX-License-Identifier: GPL-2.0
2f95cad74SMaxime Ripard%YAML 1.2
3f95cad74SMaxime Ripard---
4f95cad74SMaxime Ripard$id: http://devicetree.org/schemas/clock/allwinner,sun6i-a31-pll6-clk.yaml#
5f95cad74SMaxime Ripard$schema: http://devicetree.org/meta-schemas/core.yaml#
6f95cad74SMaxime Ripard
7*dd3cb467SAndrew Lunntitle: Allwinner A31 Peripheral PLL
8f95cad74SMaxime Ripard
9f95cad74SMaxime Ripardmaintainers:
10f95cad74SMaxime Ripard  - Chen-Yu Tsai <wens@csie.org>
11f95cad74SMaxime Ripard  - Maxime Ripard <mripard@kernel.org>
12f95cad74SMaxime Ripard
13f95cad74SMaxime Riparddeprecated: true
14f95cad74SMaxime Ripard
15f95cad74SMaxime Ripardproperties:
16f95cad74SMaxime Ripard  "#clock-cells":
17f95cad74SMaxime Ripard    const: 1
18f95cad74SMaxime Ripard    description: >
19f95cad74SMaxime Ripard      The first output is the regular PLL output, the second is a PLL
20f95cad74SMaxime Ripard      output at twice the rate.
21f95cad74SMaxime Ripard
22f95cad74SMaxime Ripard  compatible:
23f95cad74SMaxime Ripard    const: allwinner,sun6i-a31-pll6-clk
24f95cad74SMaxime Ripard
25f95cad74SMaxime Ripard  reg:
26f95cad74SMaxime Ripard    maxItems: 1
27f95cad74SMaxime Ripard
28f95cad74SMaxime Ripard  clocks:
29f95cad74SMaxime Ripard    maxItems: 1
30f95cad74SMaxime Ripard
31f95cad74SMaxime Ripard  clock-output-names:
32f95cad74SMaxime Ripard    maxItems: 2
33f95cad74SMaxime Ripard
34f95cad74SMaxime Ripardrequired:
35f95cad74SMaxime Ripard  - "#clock-cells"
36f95cad74SMaxime Ripard  - compatible
37f95cad74SMaxime Ripard  - reg
38f95cad74SMaxime Ripard  - clocks
39f95cad74SMaxime Ripard  - clock-output-names
40f95cad74SMaxime Ripard
41f95cad74SMaxime RipardadditionalProperties: false
42f95cad74SMaxime Ripard
43f95cad74SMaxime Ripardexamples:
44f95cad74SMaxime Ripard  - |
45f95cad74SMaxime Ripard    clk@1c20028 {
46f95cad74SMaxime Ripard        #clock-cells = <1>;
47f95cad74SMaxime Ripard        compatible = "allwinner,sun6i-a31-pll6-clk";
48f95cad74SMaxime Ripard        reg = <0x01c20028 0x4>;
49f95cad74SMaxime Ripard        clocks = <&osc24M>;
50f95cad74SMaxime Ripard        clock-output-names = "pll6", "pll6x2";
51f95cad74SMaxime Ripard    };
52f95cad74SMaxime Ripard
53f95cad74SMaxime Ripard...
54