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Searched +full:pll0 +full:- +full:refclk (Results 1 – 10 of 10) sorted by relevance

/linux/Documentation/devicetree/bindings/clock/
H A Dmicrochip,mpfs-ccc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/microchip,mpfs-ccc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Conor Dooley <conor.dooley@microchip.com>
16 https://onlinedocs.microchip.com/pr/GUID-8F0CC4C0-0317-4262-89CA-CE7773ED1931-en-US-1/index.html
20 const: microchip,mpfs-ccc
24 - description: PLL0's control registers
25 - description: PLL1's control registers
26 - description: DLL0's control registers
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/linux/Documentation/devicetree/bindings/phy/
H A Dphy-cadence-torrent.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 - Swapnil Jakhade <sjakhade@cadence.com>
17 - Yuti Amonkar <yamonkar@cadence.com>
22 - cdns,torrent-phy
23 - ti,j7200-serdes-10g
24 - ti,j721e-serdes-10g
26 '#address-cells':
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H A Dti,phy-j721e-wiz.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 - ti,j721e-wiz-16g
17 - ti,j721e-wiz-10g
18 - ti,j721s2-wiz-10g
19 - ti,am64-wiz-10g
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/linux/drivers/ata/
H A Dahci_da850.c1 // SPDX-License-Identifier: GPL-2.0-or-later
51 * the refclk rate by ten. in ahci_da850_calculate_mpy()
56 WARN((refclk_rate % 10) != 0, "refclk must be divisible by 10"); in ahci_da850_calculate_mpy()
86 * We should have divided evenly - if not, return an invalid in ahci_da850_calculate_mpy()
108 if (pmp && ret == -EBUSY) in ahci_da850_softreset()
123 * we increased the PLL0 frequency to 456MHz from the default 300MHz. in ahci_da850_hardreset()
133 } while (retry--); in ahci_da850_hardreset()
142 * No need to override .pmp_softreset - it's only used for actual
143 * PMP-enabled ports.
162 struct device *dev = &pdev->dev; in ahci_da850_probe()
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/linux/drivers/phy/ti/
H A Dphy-j721e-wiz.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/phy/phy-ti.h>
13 #include <linux/clk-provider.h>
25 #include <linux/reset-controller.h>
125 [TI_WIZ_PLL0_REFCLK] = "pll0-refclk",
126 [TI_WIZ_PLL1_REFCLK] = "pll1-refclk",
127 [TI_WIZ_REFCLK_DIG] = "refclk-dig",
128 [TI_WIZ_PHY_EN_REFCLK] = "phy-en-refclk",
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/linux/drivers/clk/
H A Dclk-npcm7xx.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/clk-provider.h>
20 #include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
51 val = readl_relaxed(pll->pllcon); in npcm7xx_clk_pll_recalc_rate()
79 return ERR_PTR(-ENOMEM); in npcm7xx_clk_register_pll()
89 pll->pllcon = pllcon; in npcm7xx_clk_register_pll()
90 pll->hw.init = &init; in npcm7xx_clk_register_pll()
92 hw = &pll->hw; in npcm7xx_clk_register_pll()
142 * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for
143 * this specific clock. Otherwise, set to -1.
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/linux/drivers/phy/cadence/
H A Dphy-cadence-torrent.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/phy/phy-cadence.h>
12 #include <linux/clk-provider.h>
243 [CDNS_TORRENT_REFCLK_DRIVER] = "refclk-driver",
244 [CDNS_TORRENT_DERIVED_REFCLK] = "refclk-der",
245 [CDNS_TORRENT_RECEIVED_REFCLK] = "refclk-rec",
473 for (i = 0; i < tbl->num_entries; i++) { in cdns_torrent_get_tbl_vals()
474 if (tbl->entries[i].key == key) in cdns_torrent_get_tbl_vals()
475 return tbl->entries[i].vals; in cdns_torrent_get_tbl_vals()
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/linux/arch/arm/boot/dts/ti/davinci/
H A Dda850.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/interrupt-controller/irq.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
20 #address-cells = <1>;
21 #size-cells = <0>;
24 compatible = "arm,arm926ej-s";
28 operating-points-v2 = <&opp_table>;
32 opp_table: opp-table {
33 compatible = "operating-points-v2";
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/linux/drivers/phy/broadcom/
H A Dphy-brcm-sata.c1 // SPDX-License-Identifier: GPL-2.0-or-later
196 struct brcm_sata_phy *priv = port->phy_priv; in brcm_sata_ctrl_base()
199 switch (priv->version) { in brcm_sata_ctrl_base()
204 dev_err(priv->dev, "invalid phy version\n"); in brcm_sata_ctrl_base()
208 return priv->ctrl_base + (port->portnum * size); in brcm_sata_ctrl_base()
214 struct brcm_sata_phy *priv = port->phy_priv; in brcm_sata_phy_wr()
215 void __iomem *pcb_base = priv->phy_base; in brcm_sata_phy_wr()
218 if (priv->version == BRCM_SATA_PHY_STB_40NM) in brcm_sata_phy_wr()
219 bank += (port->portnum * SATA_PCB_REG_40NM_SPACE_SIZE); in brcm_sata_phy_wr()
221 pcb_base += (port->portnum * SATA_PCB_REG_28NM_SPACE_SIZE); in brcm_sata_phy_wr()
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/linux/drivers/clk/thead/
H A Dclk-th1520-ap.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/thead,th1520-clk-ap.h>
10 #include <linux/clk-provider.h>
84 .mask = GENMASK(_width - 1, 0), \
132 regmap_read(common->map, common->cfg0, &val); in ccu_get_parent_helper()
133 parent = val >> mux->shift; in ccu_get_parent_helper()
134 parent &= GENMASK(mux->width - 1, 0); in ccu_get_parent_helper()
143 return regmap_update_bits(common->map, common->cfg0, in ccu_set_parent_helper()
144 GENMASK(mux->width - 1, 0) << mux->shift, in ccu_set_parent_helper()
145 index << mux->shift); in ccu_set_parent_helper()
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