Lines Matching +full:pll0 +full:- +full:refclk
1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/interrupt-controller/irq.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
20 #address-cells = <1>;
21 #size-cells = <0>;
24 compatible = "arm,arm926ej-s";
28 operating-points-v2 = <&opp_table>;
32 opp_table: opp-table {
33 compatible = "operating-points-v2";
35 opp_100: opp100-100000000 {
36 opp-hz = /bits/ 64 <100000000>;
37 opp-microvolt = <1000000 950000 1050000>;
40 opp_200: opp110-200000000 {
41 opp-hz = /bits/ 64 <200000000>;
42 opp-microvolt = <1100000 1050000 1160000>;
45 opp_300: opp120-300000000 {
46 opp-hz = /bits/ 64 <300000000>;
47 opp-microvolt = <1200000 1140000 1320000>;
52 * need to be enabled on a per-board basis if the chip is
56 opp_375: opp120-375000000 {
58 opp-hz = /bits/ 64 <375000000>;
59 opp-microvolt = <1200000 1140000 1320000>;
62 opp_456: opp130-456000000 {
64 opp-hz = /bits/ 64 <456000000>;
65 opp-microvolt = <1300000 1250000 1350000>;
70 #address-cells = <1>;
71 #size-cells = <1>;
73 intc: interrupt-controller@fffee000 {
74 compatible = "ti,cp-intc";
75 interrupt-controller;
76 #interrupt-cells = <1>;
77 ti,intc-size = <101>;
83 compatible = "fixed-clock";
84 #clock-cells = <0>;
85 clock-output-names = "ref_clk";
88 compatible = "fixed-clock";
89 #clock-cells = <0>;
90 clock-output-names = "sata_refclk";
94 compatible = "fixed-clock";
95 #clock-cells = <0>;
96 clock-output-names = "usb_refclkin";
101 compatible = "ti,da850-dsp";
107 reg-names = "l2sram", "l1pram", "l1dram", "host1cfg", "chipsig";
108 interrupt-parent = <&intc>;
115 compatible = "simple-bus";
117 #address-cells = <1>;
118 #size-cells = <1>;
120 interrupt-parent = <&intc>;
122 psc0: clock-controller@10000 {
123 compatible = "ti,da850-psc0";
125 #clock-cells = <1>;
126 #reset-cells = <1>;
127 #power-domain-cells = <1>;
131 clock-names = "pll0_sysclk1", "pll0_sysclk2",
135 pll0: clock-controller@11000 { label
136 compatible = "ti,da850-pll0";
139 clock-names = "clksrc", "extclksrc";
142 #clock-cells = <0>;
145 #clock-cells = <1>;
148 #clock-cells = <0>;
151 #clock-cells = <0>;
155 compatible = "pinctrl-single";
157 #pinctrl-cells = <2>;
158 pinctrl-single,bit-per-mux;
159 pinctrl-single,register-width = <32>;
160 pinctrl-single,function-mask = <0xf>;
162 pinctrl-single,gpio-range = <&range 0 17 0x8>,
169 range: gpio-range {
170 #pinctrl-single,gpio-range-cells = <3>;
173 serial0_rtscts_pins: serial0-rtscts-pins {
174 pinctrl-single,bits = <
179 serial0_rxtx_pins: serial0-rxtx-pins {
180 pinctrl-single,bits = <
185 serial1_rtscts_pins: serial1-rtscts-pins {
186 pinctrl-single,bits = <
191 serial1_rxtx_pins: serial1-rxtx-pins {
192 pinctrl-single,bits = <
197 serial2_rtscts_pins: serial2-rtscts-pins {
198 pinctrl-single,bits = <
203 serial2_rxtx_pins: serial2-rxtx-pins {
204 pinctrl-single,bits = <
209 i2c0_pins: i2c0-pins {
210 pinctrl-single,bits = <
215 i2c1_pins: i2c1-pins {
216 pinctrl-single,bits = <
221 mmc0_pins: mmc-pins {
222 pinctrl-single,bits = <
230 ehrpwm0a_pins: ehrpwm0a-pins {
231 pinctrl-single,bits = <
236 ehrpwm0b_pins: ehrpwm0b-pins {
237 pinctrl-single,bits = <
242 ehrpwm1a_pins: ehrpwm1a-pins {
243 pinctrl-single,bits = <
248 ehrpwm1b_pins: ehrpwm1b-pins {
249 pinctrl-single,bits = <
254 ecap0_pins: ecap0-pins {
255 pinctrl-single,bits = <
260 ecap1_pins: ecap1-pins {
261 pinctrl-single,bits = <
266 ecap2_pins: ecap2-pins {
267 pinctrl-single,bits = <
272 spi0_pins: spi0-pins {
273 pinctrl-single,bits = <
278 spi0_cs0_pin: spi0-cs0-pins {
279 pinctrl-single,bits = <
284 spi0_cs3_pin: spi0-cs3-pins {
285 pinctrl-single,bits = <
290 spi1_pins: spi1-pins {
291 pinctrl-single,bits = <
296 spi1_cs0_pin: spi1-cs0-pins {
297 pinctrl-single,bits = <
302 mdio_pins: mdio-pins {
303 pinctrl-single,bits = <
308 mii_pins: mii-pins {
309 pinctrl-single,bits = <
324 lcd_pins: lcd-pins {
325 pinctrl-single,bits = <
345 vpif_capture_pins: vpif-capture-pins {
346 pinctrl-single,bits = <
355 vpif_display_pins: vpif-display-pins {
356 pinctrl-single,bits = <
371 prictrl: priority-controller@14110 {
372 compatible = "ti,da850-mstpri";
376 cfgchip: chip-controller@1417c {
377 compatible = "ti,da830-cfgchip", "syscon", "simple-mfd";
380 usb_phy: usb-phy {
381 compatible = "ti,da830-usb-phy";
382 #phy-cells = <1>;
384 clock-names = "usb0_clk48", "usb1_clk48";
387 usb_phy_clk: usb-phy-clocks {
388 compatible = "ti,da830-usb-phy-clocks";
389 #clock-cells = <1>;
392 clock-names = "fck", "usb_refclkin", "auxclk";
395 compatible = "ti,da830-tbclksync";
396 #clock-cells = <0>;
398 clock-names = "fck";
401 compatible = "ti,da830-div4p5ena";
402 #clock-cells = <0>;
404 clock-names = "pll0_pllout";
407 compatible = "ti,da850-async1-clksrc";
408 #clock-cells = <0>;
410 clock-names = "pll0_sysclk3", "div4.5";
413 compatible = "ti,da850-async3-clksrc";
414 #clock-cells = <0>;
416 clock-names = "pll0_sysclk2", "pll1_sysclk2";
420 compatible = "ti,edma3-tpcc";
421 /* eDMA3 CC0: 0x01c0 0000 - 0x01c0 7fff */
423 reg-names = "edma3_cc";
425 interrupt-names = "edma3_ccint", "edma3_ccerrint";
426 #dma-cells = <2>;
429 power-domains = <&psc0 0>;
432 compatible = "ti,edma3-tptc";
435 interrupt-names = "edm3_tcerrint";
436 power-domains = <&psc0 1>;
439 compatible = "ti,edma3-tptc";
442 interrupt-names = "edm3_tcerrint";
443 power-domains = <&psc0 2>;
446 compatible = "ti,edma3-tpcc";
447 /* eDMA3 CC1: 0x01e3 0000 - 0x01e3 7fff */
449 reg-names = "edma3_cc";
451 interrupt-names = "edma3_ccint", "edma3_ccerrint";
452 #dma-cells = <2>;
455 power-domains = <&psc1 0>;
458 compatible = "ti,edma3-tptc";
461 interrupt-names = "edm3_tcerrint";
462 power-domains = <&psc1 21>;
465 compatible = "ti,da830-uart", "ns16550a";
467 reg-io-width = <4>;
468 reg-shift = <2>;
471 power-domains = <&psc0 9>;
475 compatible = "ti,da830-uart", "ns16550a";
477 reg-io-width = <4>;
478 reg-shift = <2>;
481 power-domains = <&psc1 12>;
485 compatible = "ti,da830-uart", "ns16550a";
487 reg-io-width = <4>;
488 reg-shift = <2>;
491 power-domains = <&psc1 13>;
495 compatible = "ti,da830-rtc";
499 clock-names = "int-clk";
503 compatible = "ti,davinci-i2c";
506 #address-cells = <1>;
507 #size-cells = <0>;
512 compatible = "ti,davinci-i2c";
515 #address-cells = <1>;
516 #size-cells = <0>;
518 power-domains = <&psc1 11>;
522 compatible = "ti,da830-timer";
525 interrupt-names = "tint12", "tint34";
529 compatible = "ti,davinci-wdt";
535 compatible = "ti,da830-mmc";
537 cap-sd-highspeed;
538 cap-mmc-highspeed;
541 dma-names = "rx", "tx";
546 compatible = "ti,da850-vpif";
549 power-domains = <&psc1 9>;
554 #address-cells = <1>;
555 #size-cells = <0>;
560 #address-cells = <1>;
561 #size-cells = <0>;
565 compatible = "ti,da830-mmc";
567 cap-sd-highspeed;
568 cap-mmc-highspeed;
571 dma-names = "rx", "tx";
576 compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm";
577 #pwm-cells = <3>;
580 clock-names = "fck", "tbclk";
581 power-domains = <&psc1 17>;
585 compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm";
586 #pwm-cells = <3>;
589 clock-names = "fck", "tbclk";
590 power-domains = <&psc1 17>;
594 compatible = "ti,da850-ecap", "ti,am3352-ecap";
595 #pwm-cells = <3>;
598 clock-names = "fck";
599 power-domains = <&psc1 20>;
603 compatible = "ti,da850-ecap", "ti,am3352-ecap";
604 #pwm-cells = <3>;
607 clock-names = "fck";
608 power-domains = <&psc1 20>;
612 compatible = "ti,da850-ecap", "ti,am3352-ecap";
613 #pwm-cells = <3>;
616 clock-names = "fck";
617 power-domains = <&psc1 20>;
621 #address-cells = <1>;
622 #size-cells = <0>;
623 compatible = "ti,da830-spi";
625 num-cs = <6>;
626 ti,davinci-spi-intr-line = <1>;
629 dma-names = "rx", "tx";
631 power-domains = <&psc0 4>;
635 #address-cells = <1>;
636 #size-cells = <0>;
637 compatible = "ti,da830-spi";
639 num-cs = <4>;
640 ti,davinci-spi-intr-line = <1>;
643 dma-names = "rx", "tx";
645 power-domains = <&psc1 10>;
649 compatible = "ti,da830-musb";
653 interrupt-names = "mc";
656 phy-names = "usb-phy";
658 clock-ranges;
661 #address-cells = <1>;
662 #size-cells = <1>;
668 dma-names =
672 cppi41dma: dma-controller@201000 {
673 compatible = "ti,da830-cppi41";
677 reg-names = "controller",
680 #dma-cells = <2>;
682 #dma-channels = <4>;
683 dma-channels = <4>;
684 power-domains = <&psc1 1>;
689 compatible = "ti,da850-ahci";
693 clock-names = "fck", "refclk";
696 pll1: clock-controller@21a000 {
697 compatible = "ti,da850-pll1";
700 clock-names = "clksrc";
703 #clock-cells = <1>;
706 #clock-cells = <0>;
711 #address-cells = <1>;
712 #size-cells = <0>;
715 clock-names = "fck";
716 power-domains = <&psc1 5>;
720 compatible = "ti,davinci-dm6467-emac";
722 ti,davinci-ctrl-reg-offset = <0x3000>;
723 ti,davinci-ctrl-mod-reg-offset = <0x2000>;
724 ti,davinci-ctrl-ram-offset = <0>;
725 ti,davinci-ctrl-ram-size = <0x2000>;
726 local-mac-address = [ 00 00 00 00 00 00 ];
729 power-domains = <&psc1 5>;
733 compatible = "ti,da830-ohci";
737 phy-names = "usb-phy";
742 compatible = "ti,dm6441-gpio";
743 gpio-controller;
744 #gpio-cells = <2>;
748 ti,davinci-gpio-unbanked = <0>;
750 clock-names = "gpio";
752 interrupt-controller;
753 #interrupt-cells = <2>;
754 gpio-ranges = <&pmx_core 0 15 1>,
899 psc1: clock-controller@227000 {
900 compatible = "ti,da850-psc1";
902 #clock-cells = <1>;
903 #power-domain-cells = <1>;
906 clock-names = "pll0_sysclk2", "pll0_sysclk4", "async3";
907 assigned-clocks = <&async3_clk>;
908 assigned-clock-parents = <&pll1_sysclk 2>;
910 pinconf: pin-controller@22c00c {
911 compatible = "ti,da850-pupd";
917 compatible = "ti,da830-mcasp-audio";
920 reg-names = "mpu", "dat";
922 interrupt-names = "common";
923 power-domains = <&psc1 7>;
927 dma-names = "tx", "rx";
931 compatible = "ti,da850-tilcdc";
934 max-pixelclock = <37500>;
936 clock-names = "fck";
937 power-domains = <&psc1 16>;
942 compatible = "ti,da850-aemif";
943 #address-cells = <2>;
944 #size-cells = <1>;
950 clock-names = "aemif";
951 clock-ranges;
954 memctrl: memory-controller@b0000000 {
955 compatible = "ti,da850-ddr-controller";