| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | qoriq-clock.txt | 1 * Clock Block on Freescale QorIQ Platforms
4 SYSCLK signal. The SYSCLK input (frequency) is multiplied using
5 multiple phase locked loops (PLL) to create a variety of frequencies
14 --------------- -------------
18 1. Clock Block Binding
21 - compatible: Should contain a chip-specific clock block compatible
22 string and (if applicable) may contain a chassis-version clock
25 Chip-specific strings are of the form "fsl,<chip>-clockgen", such as:
26 * "fsl,p2041-clockgen"
27 * "fsl,p3041-clockgen"
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| H A D | fsl,qoriq-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/fsl,qoriq-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Clock Block on Freescale QorIQ Platforms
10 - Frank Li <Frank.Li@nxp.com>
14 SYSCLK signal. The SYSCLK input (frequency) is multiplied using
15 multiple phase locked loops (PLL) to create a variety of frequencies
24 --------------- -------------
28 Clock Provider
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| H A D | silabs,si5351.txt | 1 Binding for Silicon Labs Si5351a/b/c programmable i2c clock generator.
5 https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf
7 The Si5351a/b/c are programmable i2c clock generators with up to 8 output
8 clocks. Si5351a also has a reduced pin-count package (MSOP10) where only
9 3 output clocks are accessible. The internal structure of the clock
15 - compatible: shall be one of the following:
16 "silabs,si5351a" - Si5351a, QFN20 package
17 "silabs,si5351a-msop" - Si5351a, MSOP10 package
18 "silabs,si5351b" - Si5351b, QFN20 package
19 "silabs,si5351c" - Si5351c, QFN20 package
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| H A D | fsl,qoriq-clock-legacy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/fsl,qoriq-clock-legacy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Legacy Clock Block on Freescale QorIQ Platforms
10 - Frank Li <Frank.Li@nxp.com>
16 Most of the bindings are from the common clock binding[1].
17 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
22 - fsl,qoriq-core-pll-1.0
23 - fsl,qoriq-core-pll-2.0
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| H A D | silabs,si5341.txt | 2 i2c clock generator.
6 https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
8 https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf
10 https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf
12 The Si5341 and Si5340 are programmable i2c clock generators with up to 10 output
13 clocks. The chip contains a PLL that sources 5 (or 4) multisynth clocks, which
15 The internal structure of the clock generators can be found in [2].
21 chip at boot, in case you have a (pre-)programmed device. If the PLL is not
33 - compatible: shall be one of the following:
34 "silabs,si5340" - Si5340 A/B/C/D
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| H A D | fsl,plldig.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/fsl,plldig.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP QorIQ Layerscape LS1028A Display PIXEL Clock
10 - Wen He <wen.he_1@nxp.com>
13 NXP LS1028A has a clock domain PXLCLK0 used for the Display output
14 interface in the display core, as implemented in TSMC CLN28HPM PLL.
19 const: fsl,ls1028a-plldig
27 '#clock-cells':
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| H A D | ti,cdce925.txt | 1 Binding for TI CDCE913/925/937/949 programmable I2C clock synthesizers.
4 This binding uses the common clock binding[1].
6 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
12 The driver provides clock sources for each output Y1 through Y5.
15 - compatible: Shall be one of the following:
16 - "ti,cdce913": 1-PLL, 3 Outputs
17 - "ti,cdce925": 2-PLL, 5 Outputs
18 - "ti,cdce937": 3-PLL, 7 Outputs
19 - "ti,cdce949": 4-PLL, 9 Outputs
20 - reg: I2C device address.
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| H A D | baikal,bt1-ccu-pll.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baika
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| H A D | ti,cdce925.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/t
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| H A D | brcm,iproc-clocks.txt | 3 This binding uses the common clock binding:
4 Documentation/devicetree/bindings/clock/clock-bindings.txt
6 The iProc clock controller manages clocks that are common to the iProc family.
8 LCPLL0, MIPIPLL, and etc., all derived from an onboard crystal. Each PLL
11 Required properties for a PLL and its leaf clocks:
13 - compatible:
14 Should have a value of the form "brcm,<soc>-<pll>". For example, GENPLL on
15 Cygnus has a compatible string of "brcm,cygnus-genpll"
17 - #clock-cells:
18 Have a value of <1> since there are more than 1 leaf clock of a given PLL
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| H A D | snps,hsdk-pll-clock.txt | 1 Binding for the HSDK Generic PLL clock
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible: should be "snps,hsdk-<name>-pll-clock"
9 "snps,hsdk-core-pll-clock"
10 "snps,hsdk-gp-pll-clock"
11 "snps,hsdk-hdmi-pll-clock"
12 - reg : should contain base register location and length.
13 - clocks: shall be the input parent clock phandle for the PLL.
14 - #clock-cells: from common clock binding; Should always be set to 0.
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| H A D | snps,pll-clock.txt | 1 Binding for the AXS10X Generic PLL clock
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible: should be "snps,axs10x-<name>-pll-clock"
9 "snps,axs10x-arc-pll-clock"
10 "snps,axs10x-pgu-pll-clock"
11 - reg: should always contain 2 pairs address - length: first for PLL config
13 - clocks: shall be the input parent clock phandle for the PLL.
14 - #clock-cells: from common clock binding; Should always be set to 0.
17 input-clk: input-clk {
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| H A D | vt8500.txt | 1 Device Tree Clock bindings for arch-vt8500
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "via,vt8500-pll-clock" - for a VT8500/WM8505 PLL clock
10 "wm,wm8650-pll-clock" - for a WM8650 PLL clock
11 "wm,wm8750-pll-clock" - for a WM8750 PLL clock
12 "wm,wm8850-pll-clock" - for a WM8850 PLL clock
13 "via,vt8500-device-clock" - for a VT/WM device clock
15 Required properties for PLL clocks:
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| /freebsd/sys/contrib/device-tree/Bindings/c6x/ |
| H A D | clocks.txt | 1 C6X PLL Clock Controllers
2 -------------------------
4 This is a first-cut support for the SoC clock controllers. This is still
6 clock support is added to the kernel.
10 - compatible: "ti,c64x+pll"
11 May also have SoC-specific value to support SoC-specific initialization
13 "ti,c6455-pll"
14 "ti,c6457-pll"
15 "ti,c6472-pll"
16 "ti,c6474-pll"
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| /freebsd/contrib/ntp/html/ |
| H A D | discipline.html | 1 <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
4 <meta http-equiv="content-type" content="text/html;charset=iso-8859-1">
6 <title>Clock Discipline Algorithm</title>
7 <!-- Changed by: stenn, 03-Jan-2020 -->
11 <h3>Clock Discipline Algorithm</h3>
13 <!-- #BeginDate format:En2m -->3-Jan-2020 02:12<!-- #EndDate -->
18 <li class="inline"><a href="#pll">Phase-Lock Loop Operations</a></li>
20 <li class="inline"><a href="#house">Clock Initialization and Management</a></li>
24 …clock discipline algorithm, which is best described as an adaptive parameter, hybrid phase/frequen…
26 <p>Figure 1. Clock Discipline Algorithm</p>
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| /freebsd/contrib/ntp/kernel/sys/ |
| H A D | timex.h | 21 * Added defines for hybrid phase/frequency-lock loop.
25 * defines for PPS phase-lock loop.
28 * Revised status codes and structures for external clock and PPS
45 * ntp_gettime - NTP user application interface
56 * ntp_adjtime - NTP daemon application interface
76 * phase-lock loop (PLL) model used in the kernel implementation. These
81 * establishes the timer interrupt frequency, 100 Hz for the SunOS
86 * SHIFT_KG and SHIFT_KF establish the damping of the PLL and are chosen
91 * MAXTC establishes the maximum time constant of the PLL. With the
93 * zero to MAXTC, the PLL will converge in 15 minutes to 16 hours,
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| /freebsd/lib/libsys/ |
| H A D | ntp_adjtime.2 | 55 function is used by the NTP daemon to adjust the system clock to an
61 to adjust the phase and frequency of the phase- or frequency-lock loop
62 (PLL resp. FLL) which controls the system clock.
78 .Bd -literal
80 unsigned int modes; /* clock mode bits (wo) */
82 long freq; /* frequency offset (scaled ppm) (rw) */
85 int status; /* clock status bits (rw) */
86 long constant; /* pll time constant (rw) */
87 long precision; /* clock precision (us) (ro) */
88 long tolerance; /* clock frequency tolerance (scaled
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| /freebsd/sys/contrib/device-tree/Bindings/display/exynos/ |
| H A D | exynos_dsim.txt | 4 - compatible: value should be one of the following
5 "samsung,exynos3250-mipi-dsi" /* for Exynos3250/3472 SoCs */
6 "samsung,exynos4210-mipi-dsi" /* for Exynos4 SoCs */
7 "samsung,exynos5410-mipi-dsi" /* for Exynos5410/5420/5440 SoCs */
8 "samsung,exynos5422-mipi-dsi" /* for Exynos5422/5800 SoCs */
9 "samsung,exynos5433-mipi-dsi" /* for Exynos5433 SoCs */
10 - reg: physical base address and length of the registers set for the device
11 - interrupts: should contain DSI interrupt
12 - clocks: list of clock specifiers, must contain an entry for each required
13 entry in clock-names
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| /freebsd/sys/contrib/device-tree/src/mips/mobileye/ |
| H A D | eyeq5-fixed-clocks.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
7 /* Fixed clock */
8 pll_cpu: pll-cpu {
9 compatible = "fixed-clock";
10 #clock-cells = <0>;
11 clock-frequency = <1500000000>;
14 pll_vdi: pll-vdi {
15 compatible = "fixed-clock";
16 #clock-cells = <0>;
17 clock-frequency = <1280000000>;
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| /freebsd/sys/arm/xilinx/ |
| H A D | zy7_slcr.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
30 * Zynq-700 SLCR driver. Provides hooks for cpu_reset and PL control stuff.
31 * In the future, maybe MIO control, clock control, etc. could go here.
33 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
66 #define ZSLCR_LOCK(sc) mtx_lock(&(sc)->sc_mtx)
67 #define ZSLCR_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx)
69 mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), \
71 #define ZSLCR_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
73 #define RD4(sc, off) (bus_read_4((sc)->mem_res, (off)))
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| /freebsd/sys/contrib/device-tree/Bindings/display/bridge/ |
| H A D | samsung,mipi-dsim.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/samsung,mipi-dsim.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Inki Dae <inki.dae@samsung.com>
11 - Jagan Teki <jagan@amarulasolutions.com>
12 - Marek Szyprowski <m.szyprowski@samsung.com>
21 - enum:
22 - samsung,exynos3250-mipi-dsi
23 - samsung,exynos4210-mipi-dsi
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| /freebsd/sys/contrib/device-tree/include/dt-bindings/clock/ |
| H A D | tegra186-clock.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
8 * @defgroup clock_ids Clock Identifiers
235 * @defgroup nafll_clks NAFLL clock sources
355 * pwrclk. @warning: This is almost certainly not the clock you think
356 * it is. If you're looking for the clock of the graphics engine, see
417 * @brief controls the EMC clock frequency.
418 * @details Doing a clk_set_rate on this clock will select the
419 * appropriate clock source, program the source rate and execute a
420 * specific sequence to switch to the new clock source for both memory
677 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSC. This clock object is read…
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| /freebsd/sys/contrib/device-tree/src/arm64/zte/ |
| H A D | zx296718.dtsi | 5 * This file is dual-licensed: you can use it either under the terms
44 #include <dt-bindings/input/input.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/gpio/gpio.h>
47 #include <dt-bindings/clock/zx296718-clock.h>
51 #address-cells = <1>;
52 #size-cells = <1>;
53 interrupt-parent = <&gic>;
67 #address-cells = <2>;
68 #size-cells = <0>;
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| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | motorcomm,yt8xxx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
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| /freebsd/sys/sys/ |
| H A D | timex.h | 1 /*-
4 * Copyright (c) David L. Mills 1993-2001 *
5 * Copyright (c) Poul-Henning Kamp 2000-2001 *
29 * a joint work between Poul-Henning Kamp and David L. Mills.
44 * kernel discipline loop. Phase or frequency errors greater than
46 * less than MINSEC, the loop always operates in PLL mode; while, for
55 #define MAXSEC 2048 /* max PLL update interval (s) */
64 #define MOD_FREQUENCY 0x0002 /* set frequency offset */
67 #define MOD_STATUS 0x0010 /* set clock status bits */
68 #define MOD_TIMECONST 0x0020 /* set PLL time constant */
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