Lines Matching +full:pll +full:- +full:clock +full:- +full:frequency

1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/fsl,plldig.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP QorIQ Layerscape LS1028A Display PIXEL Clock
10   - Wen He <wen.he_1@nxp.com>
13   NXP LS1028A has a clock domain PXLCLK0 used for the Display output
14   interface in the display core, as implemented in TSMC CLN28HPM PLL.
19     const: fsl,ls1028a-plldig
27   '#clock-cells':
30   fsl,vco-hz:
31     description: Optional for VCO frequency of the PLL in Hertz. The VCO frequency
32       of this PLL cannot be changed during runtime only at startup. Therefore,
34       the requested frequency. To work around this restriction the user may specify
35       its own desired VCO frequency for the PLL.
41   - compatible
42   - reg
43   - clocks
44   - '#clock-cells'
49   # Display PIXEL Clock node:
50   - |
51     dpclk: clock-display@f1f0000 {
52         compatible = "fsl,ls1028a-plldig";
54         #clock-cells = <0>;