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/linux/drivers/gpu/drm/i915/display/
H A Dintel_cx0_phy.c1 // SPDX-License-Identifier: MIT
30 for ((__lane) = 0; (__lane) < 2; (__lane)++) \
33 #define INTEL_CX0_LANE0 BIT(0)
48 if (display->platform.pantherlake && phy < PHY_C) in intel_encoder_is_c10phy()
51 if ((display->platform.lunarlake || display->platform.meteorlake) && phy < PHY_C) in intel_encoder_is_c10phy()
61 return 0; in lane_mask_to_lane()
74 * In DP-alt with pin assignment D, only PHY lane 0 is owned in intel_cx0_get_owned_lane_mask()
87 drm_WARN_ON(display->drm, !enabled); in assert_dc_off()
97 XELPDP_PORT_MSGBUS_TIMER(display, encoder->port, lane), in intel_cx0_program_msgbus_timer()
139 XELPDP_PORT_P2M_MSGBUS_STATUS(display, encoder->port, lane), in intel_clear_response_ready_flag()
[all …]
/linux/drivers/clk/qcom/
H A Dclk-alpha-pll.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (c) 2021, 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
9 #include <linux/clk-provider.h>
13 #include "clk-alpha-pll.h"
16 #define PLL_MODE(p) ((p)->offset + 0x0)
17 # define PLL_OUTCTRL BIT(0)
22 # define PLL_LOCK_COUNT_MASK 0x3f
24 # define PLL_BIAS_COUNT_MASK 0x3f
36 #define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL])
37 #define PLL_CAL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL])
[all …]
H A Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/clk-provider.h>
17 #include "clk-pll.h"
20 #define PLL_OUTCTRL BIT(0)
26 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_enable() local
31 ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val); in clk_pll_enable()
37 return 0; in clk_pll_enable()
39 /* Disable PLL bypass mode. */ in clk_pll_enable()
40 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL, in clk_pll_enable()
47 * de-asserting the reset. Delay 10us just to be safe. in clk_pll_enable()
[all …]
/linux/drivers/clk/tegra/
H A Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk-provider.h>
24 #define PLL_BASE_DIVM_SHIFT 0
26 #define PLLU_POST_DIVP_MASK 0x1
31 #define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1)
34 #define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1)
35 #define PLL_MISC_VCOCON_SHIFT 0
37 #define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1)
41 #define PMC_PLLP_WB0_OVERRIDE 0xf8
50 #define PLLE_BASE_DIVCML_MASK 0xf
[all …]
/linux/drivers/clk/mediatek/
H A Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
16 #include "clk-pll.h"
20 #define REG_CON0 0
23 #define CON0_BASE_EN BIT(0)
24 #define CON0_PWR_ON BIT(0)
35 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); in mtk_pll_is_prepared() local
37 return (readl(pll->en_addr) & BIT(pll->data->pll_en_bit)) != 0; in mtk_pll_is_prepared()
42 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); in mtk_pll_fenc_is_prepared() local
44 return !!(readl(pll->fenc_addr) & BIT(pll->data->fenc_sta_bit)); in mtk_pll_fenc_is_prepared()
[all …]
/linux/drivers/clk/rockchip/
H A Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Author: Xing Zheng <zhengxing@rock-chips.com>
14 #include <linux/clk-provider.h>
20 #define PLL_MODE_MASK 0x3
21 #define PLL_MODE_SLOW 0x0
22 #define PLL_MODE_NORM 0x1
23 #define PLL_MODE_DEEP 0x2
24 #define PLL_RK3328_MODE_MASK 0x1
51 struct rockchip_clk_pll *pll, unsigned long rate) in rockchip_get_pll_settings() argument
53 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; in rockchip_get_pll_settings()
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/linux/drivers/clk/sprd/
H A Dpll.c1 // SPDX-License-Identifier: GPL-2.0
3 // Spreadtrum pll clock driver
13 #include "pll.h"
18 #define pindex(pll, member) \ argument
19 (pll->factors[member].shift / (8 * sizeof(pll->regs_num)))
21 #define pshift(pll, member) \ argument
22 (pll->factors[member].shift % (8 * sizeof(pll->regs_num)))
24 #define pwidth(pll, member) \ argument
25 pll->factors[member].width
27 #define pmask(pll, member) \ argument
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/linux/drivers/clk/bcm/
H A Dclk-iproc-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
13 #include "clk-iproc.h"
19 * PLL MACRO_SELECT modes 0 to 5 choose pre-calculated PLL output frequencies
20 * from a look-up table. Mode 7 allows user to manipulate PLL clock dividers
24 /* number of delay loops waiting for PLL to lock */
32 KP_BAND_MID = 0,
75 struct iproc_pll *pll; member
90 return -EINVAL; in pll_calc_param()
92 residual = target_rate - (ndiv_int * parent_rate); in pll_calc_param()
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H A Dclk-iproc-armpll.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
13 #include "clk-iproc.h"
15 #define IPROC_CLK_MAX_FREQ_POLICY 0x3
16 #define IPROC_CLK_POLICY_FREQ_OFFSET 0x008
18 #define IPROC_CLK_POLICY_FREQ_POLICY_FREQ_MASK 0x7
20 #define IPROC_CLK_PLLARMA_OFFSET 0xc00
23 #define IPROC_CLK_PLLARMA_PDIV_MASK 0xf
25 #define IPROC_CLK_PLLARMA_NDIV_INT_MASK 0x3ff
27 #define IPROC_CLK_PLLARMB_OFFSET 0xc04
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/linux/drivers/clk/samsung/
H A Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * This file contains the utility functions to register the pll clocks.
15 #include <linux/clk-provider.h>
18 #include "clk-pll.h"
27 /* PLL enable control bit offset in @con_reg register */
29 /* PLL lock status bit offset in @con_reg register */
39 struct samsung_clk_pll *pll, unsigned long rate) in samsung_get_pll_settings() argument
41 const struct samsung_pll_rate_table *rate_table = pll->rate_table; in samsung_get_pll_settings()
44 for (i = 0; i < pll->rate_count; i++) { in samsung_get_pll_settings()
55 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll_determine_rate() local
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/linux/drivers/video/fbdev/aty/
H A Dmach64_ct.c1 // SPDX-License-Identifier: GPL-2.0
18 static int aty_valid_pll_ct (const struct fb_info *info, u32 vclk_per, struct pll_ct *pll);
19 static int aty_dsp_gt (const struct fb_info *info, u32 bpp, struct pll_ct *pll);
20 static int aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll);
21 static u32 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll);
51 * CLK = ----------------------
68 * XCLK The clock rate of the on-chip memory
75 * SCLK Multi-purpose clock
77 * - MCLK and XCLK use the same FB_DIV
78 * - VCLK0 .. VCLK3 use the same FB_DIV
[all …]
/linux/drivers/clk/visconti/
H A Dpll.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Toshiba Visconti PLL driver
12 #include <linux/clk-provider.h>
17 #include "pll.h"
29 #define PLL_CONF_REG 0x0000
30 #define PLL_CTRL_REG 0x0004
31 #define PLL_FRACMODE_REG 0x0010
32 #define PLL_INTIN_REG 0x0014
33 #define PLL_FRACIN_REG 0x0018
34 #define PLL_REFDIV_REG 0x001c
[all …]
/linux/drivers/clk/at91/
H A Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk-provider.h>
17 #define PLL_DIV_MASK 0xff
20 #define PLL_MUL(reg, layout) (((reg) >> (layout)->mul_shift) & \
21 (layout)->mul_mask)
23 #define PLL_MUL_MASK(layout) ((layout)->mul_mask)
26 #define PLL_ICPR_MASK(id) (0xffff << PLL_ICPR_SHIFT(id))
27 #define PLL_MAX_COUNT 0x3f
52 return status & PLL_STATUS_MASK(id) ? 1 : 0; in clk_pll_ready()
57 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_prepare() local
[all …]
/linux/drivers/clk/sophgo/
H A Dclk-cv18xx-pll.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
11 #include "clk-cv18xx-pll.h"
36 struct cv1800_clk_pll *pll = hw_to_cv1800_clk_pll(hw); in ipll_recalc_rate() local
39 value = readl(pll->common.base + pll->pll_reg); in ipll_recalc_rate()
51 unsigned long best_rate = 0; in ipll_find_rate()
53 unsigned long pre_div_sel = 0, div_sel = 0, post_div_sel = 0; in ipll_find_rate()
58 for_each_pll_limit_range(pre, &limit->pre_div) { in ipll_find_rate()
59 for_each_pll_limit_range(div, &limit->div) { in ipll_find_rate()
60 for_each_pll_limit_range(post, &limit->post_div) { in ipll_find_rate()
[all …]
H A Dclk-sg2044-pll.c1 // SPDX-License-Identifier: GPL-2.0
3 * Sophgo SG2044 PLL clock controller driver
13 #include <linux/clk-provider.h>
22 #include <dt-bindings/clock/sophgo,sg2044-pll.h>
28 #define PLL_FBDIV_MASK GENMASK(11, 0)
46 #define PLL_VCOSEL_1G6 0x2
47 #define PLL_VCOSEL_2G4 0x3
49 #define PLL_LIMIT_FOUTVCO 0
57 for (_var = (_limit)->min; _var <= (_limit)->max; _var++)
85 struct sg2044_pll_internal pll; member
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/linux/drivers/clk/pistachio/
H A Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk-provider.h>
16 #define PLL_STATUS 0x0
17 #define PLL_STATUS_LOCK BIT(0)
19 #define PLL_CTRL1 0x4
20 #define PLL_CTRL1_REFDIV_SHIFT 0
21 #define PLL_CTRL1_REFDIV_MASK 0x3f
23 #define PLL_CTRL1_FBDIV_MASK 0xfff
25 #define PLL_INT_CTRL1_POSTDIV1_MASK 0x7
27 #define PLL_INT_CTRL1_POSTDIV2_MASK 0x7
[all …]
/linux/drivers/clk/baikal-t1/
H A Dccu-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * Baikal-T1 CCU PLL interface driver
12 #define pr_fmt(fmt) "bt1-ccu-pll: " fmt
20 #include <linux/clk-provider.h>
29 #include "ccu-pll.h"
31 #define CCU_PLL_CTL 0x000
32 #define CCU_PLL_CTL_EN BIT(0)
42 #define CCU_PLL_CTL1 0x004
88 static int ccu_pll_reset(struct ccu_pll *pll, unsigned long ref_clk, in ccu_pll_reset() argument
97 regmap_update_bits(pll->sys_regs, pll->reg_ctl, in ccu_pll_reset()
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/linux/drivers/gpu/drm/sprd/
H A Dmegacores_pll.c1 // SPDX-License-Identifier: GPL-2.0
15 #define L 0
17 #define CLK 0
19 #define INFINITY 0xffffffff
22 #define AVERAGE(a, b) (min(a, b) + abs((b) - (a)) / 2)
30 static int dphy_calc_pll_param(struct dphy_pll *pll) in dphy_calc_pll_param() argument
38 pll->potential_fvco = pll->freq / khz; in dphy_calc_pll_param()
39 pll->ref_clk = PHY_REF_CLK / khz; in dphy_calc_pll_param()
41 for (i = 0; i < 4; ++i) { in dphy_calc_pll_param()
42 if (pll->potential_fvco >= VCO_BAND_LOW && in dphy_calc_pll_param()
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/linux/drivers/clk/st/
H A Dclkgen-pll.c1 // SPDX-License-Identifier: GPL-2.0-or-later
15 #include <linux/clk-provider.h>
24 * PLL configuration register bits for PLL3200 C32
26 #define C32_NDIV_MASK (0xff)
27 #define C32_IDF_MASK (0x7)
28 #define C32_ODF_MASK (0x3f)
29 #define C32_LDF_MASK (0x7f)
30 #define C32_CP_MASK (0x1f)
35 * PLL configuration register bits for PLL4600 C28
37 #define C28_NDIV_MASK (0xff)
[all …]
/linux/drivers/clk/mmp/
H A Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * MMP PLL clock rate calculation
8 #include <linux/clk-provider.h>
31 struct mmp_clk_pll *pll = to_clk_mmp_pll(hw); in mmp_clk_pll_is_enabled() local
34 val = readl_relaxed(pll->enable_reg); in mmp_clk_pll_is_enabled()
35 if ((val & pll->enable) == pll->enable) in mmp_clk_pll_is_enabled()
39 if (pll->default_rate > 0) in mmp_clk_pll_is_enabled()
42 return 0; in mmp_clk_pll_is_enabled()
48 struct mmp_clk_pll *pll = to_clk_mmp_pll(hw); in mmp_clk_pll_recalc_rate() local
53 val = readl_relaxed(pll->enable_reg); in mmp_clk_pll_recalc_rate()
[all …]
/linux/drivers/gpu/drm/omapdrm/dss/
H A Dhdmi_pll.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * HDMI PLL
5 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
23 void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s) in hdmi_pll_dump() argument
25 #define DUMPPLL(r) seq_printf(s, "%-35s %08x\n", #r,\ in hdmi_pll_dump()
26 hdmi_read_reg(pll->base, r)) in hdmi_pll_dump()
41 struct hdmi_pll_data *pll = container_of(dsspll, struct hdmi_pll_data, pll); in hdmi_pll_enable() local
42 struct hdmi_wp_data *wp = pll->wp; in hdmi_pll_enable()
45 r = pm_runtime_get_sync(&pll->pdev->dev); in hdmi_pll_enable()
46 WARN_ON(r < 0); in hdmi_pll_enable()
[all …]
/linux/drivers/clk/nuvoton/
H A Dclk-ma35d1-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Chi-Fang Li <cfli0@nuvoton.com>
8 #include <linux/clk-provider.h>
16 #include <dt-bindings/clock/nuvoton,ma35d1-clk.h>
18 #include "clk-ma35d1.h"
20 /* PLL frequency limits */
29 #define PLL_SS_RATE 0x77
30 #define PLL_SLOPE 0x58CFA
32 #define REG_PLL_CTL0_OFFSET 0x0
33 #define REG_PLL_CTL1_OFFSET 0x4
[all …]
/linux/drivers/clk/x86/
H A Dclk-cgu-pll.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020-2022 MaxLinear, Inc.
9 #include <linux/clk-provider.h>
15 #include "clk-cgu.h"
18 #define PLL_REF_DIV(x) ((x) + 0x08)
42 struct lgm_clk_pll *pll = to_lgm_clk_pll(hw); in lgm_pll_recalc_rate() local
45 mult = lgm_get_clk_val(pll->membase, PLL_REF_DIV(pll->reg), 0, 12); in lgm_pll_recalc_rate()
46 div = lgm_get_clk_val(pll->membase, PLL_REF_DIV(pll->reg), 18, 6); in lgm_pll_recalc_rate()
47 frac = lgm_get_clk_val(pll->membase, pll->reg, 2, 24); in lgm_pll_recalc_rate()
49 if (pll->type == TYPE_LJPLL) in lgm_pll_recalc_rate()
[all …]
/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A Dhdmi_pll.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * HDMI PLL
23 void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s) in hdmi_pll_dump() argument
25 #define DUMPPLL(r) seq_printf(s, "%-35s %08x\n", #r,\ in hdmi_pll_dump()
26 hdmi_read_reg(pll->base, r)) in hdmi_pll_dump()
39 void hdmi_pll_compute(struct hdmi_pll_data *pll, in hdmi_pll_compute() argument
47 const struct dss_pll_hw *hw = pll->pll.hw; in hdmi_pll_compute()
49 clkin = clk_get_rate(pll->pll.clkin); in hdmi_pll_compute()
56 n = DIV_ROUND_UP(clkin, hw->fint_max); in hdmi_pll_compute()
60 min_dco = roundup(hw->clkdco_min, fint); in hdmi_pll_compute()
[all …]
/linux/drivers/clk/imx/
H A Dclk-sscg-pll.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 * Documentation for this SCCG pll can be found at:
8 * https://www.nxp.com/docs/en/reference-manual/IMX8MDQLQRM.pdf#page=834
11 #include <linux/clk-provider.h>
21 /* PLL CFGs */
22 #define PLL_CFG0 0x0
23 #define PLL_CFG1 0x4
24 #define PLL_CFG2 0x8
31 #define PLL_REF_MASK GENMASK(2, 0)
36 /* These are the specification limits for the SSCG PLL */
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