1 // SPDX-License-Identifier: GPL-2.0
3  * Copyright (C) 2020-2022 MaxLinear, Inc.
9 #include <linux/clk-provider.h>
15 #include "clk-cgu.h"
18 #define PLL_REF_DIV(x)		((x) + 0x08)
42 	struct lgm_clk_pll *pll = to_lgm_clk_pll(hw);  in lgm_pll_recalc_rate()  local
45 	mult = lgm_get_clk_val(pll->membase, PLL_REF_DIV(pll->reg), 0, 12);  in lgm_pll_recalc_rate()
46 	div = lgm_get_clk_val(pll->membase, PLL_REF_DIV(pll->reg), 18, 6);  in lgm_pll_recalc_rate()
47 	frac = lgm_get_clk_val(pll->membase, pll->reg, 2, 24);  in lgm_pll_recalc_rate()
49 	if (pll->type == TYPE_LJPLL)  in lgm_pll_recalc_rate()
57 	struct lgm_clk_pll *pll = to_lgm_clk_pll(hw);  in lgm_pll_is_enabled()  local
60 	ret = lgm_get_clk_val(pll->membase, pll->reg, 0, 1);  in lgm_pll_is_enabled()
67 	struct lgm_clk_pll *pll = to_lgm_clk_pll(hw);  in lgm_pll_enable()  local
71 	lgm_set_clk_val(pll->membase, pll->reg, 0, 1, 1);  in lgm_pll_enable()
72 	ret = regmap_read_poll_timeout_atomic(pll->membase, pll->reg,  in lgm_pll_enable()
73 					      val, (val & 0x1), 1, 100);  in lgm_pll_enable()
81 	struct lgm_clk_pll *pll = to_lgm_clk_pll(hw);  in lgm_pll_disable()  local
83 	lgm_set_clk_val(pll->membase, pll->reg, 0, 1, 0);  in lgm_pll_disable()
98 	struct lgm_clk_pll *pll;  in lgm_clk_register_pll()  local
99 	struct device *dev = ctx->dev;  in lgm_clk_register_pll()
104 	init.name = list->name;  in lgm_clk_register_pll()
105 	init.flags = list->flags;  in lgm_clk_register_pll()
106 	init.parent_data = list->parent_data;  in lgm_clk_register_pll()
107 	init.num_parents = list->num_parents;  in lgm_clk_register_pll()
109 	pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL);  in lgm_clk_register_pll()
110 	if (!pll)  in lgm_clk_register_pll()
111 		return ERR_PTR(-ENOMEM);  in lgm_clk_register_pll()
113 	pll->membase = ctx->membase;  in lgm_clk_register_pll()
114 	pll->reg = list->reg;  in lgm_clk_register_pll()
115 	pll->flags = list->flags;  in lgm_clk_register_pll()
116 	pll->type = list->type;  in lgm_clk_register_pll()
117 	pll->hw.init = &init;  in lgm_clk_register_pll()
119 	hw = &pll->hw;  in lgm_clk_register_pll()
134 	for (i = 0; i < nr_clk; i++, list++) {  in lgm_clk_register_plls()
137 			dev_err(ctx->dev, "failed to register pll: %s\n",  in lgm_clk_register_plls()
138 				list->name);  in lgm_clk_register_plls()
141 		ctx->clk_data.hws[list->id] = hw;  in lgm_clk_register_plls()
144 	return 0;  in lgm_clk_register_plls()