Lines Matching +full:pll +full:- +full:0
1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Author: Xing Zheng <zhengxing@rock-chips.com>
14 #include <linux/clk-provider.h>
20 #define PLL_MODE_MASK 0x3
21 #define PLL_MODE_SLOW 0x0
22 #define PLL_MODE_NORM 0x1
23 #define PLL_MODE_DEEP 0x2
24 #define PLL_RK3328_MODE_MASK 0x1
51 struct rockchip_clk_pll *pll, unsigned long rate) in rockchip_get_pll_settings() argument
53 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; in rockchip_get_pll_settings()
56 for (i = 0; i < pll->rate_count; i++) { in rockchip_get_pll_settings()
67 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_pll_determine_rate() local
68 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; in rockchip_pll_determine_rate()
72 for (i = 0; i < pll->rate_count; i++) { in rockchip_pll_determine_rate()
73 if (req->rate >= rate_table[i].rate) { in rockchip_pll_determine_rate()
74 req->rate = rate_table[i].rate; in rockchip_pll_determine_rate()
76 return 0; in rockchip_pll_determine_rate()
81 req->rate = rate_table[i - 1].rate; in rockchip_pll_determine_rate()
83 return 0; in rockchip_pll_determine_rate()
87 * Wait for the pll to reach the locked state.
91 static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll) in rockchip_pll_wait_lock() argument
93 struct regmap *grf = pll->ctx->grf; in rockchip_pll_wait_lock()
97 ret = regmap_read_poll_timeout(grf, pll->lock_offset, val, in rockchip_pll_wait_lock()
98 val & BIT(pll->lock_shift), 0, 1000); in rockchip_pll_wait_lock()
100 pr_err("%s: timeout waiting for pll to lock\n", __func__); in rockchip_pll_wait_lock()
106 * PLL used in RK3036
109 #define RK3036_PLLCON(i) (i * 0x4)
110 #define RK3036_PLLCON0_FBDIV_MASK 0xfff
111 #define RK3036_PLLCON0_FBDIV_SHIFT 0
112 #define RK3036_PLLCON0_POSTDIV1_MASK 0x7
114 #define RK3036_PLLCON1_REFDIV_MASK 0x3f
115 #define RK3036_PLLCON1_REFDIV_SHIFT 0
116 #define RK3036_PLLCON1_POSTDIV2_MASK 0x7
119 #define RK3036_PLLCON1_DSMPD_MASK 0x1
122 #define RK3036_PLLCON2_FRAC_MASK 0xffffff
123 #define RK3036_PLLCON2_FRAC_SHIFT 0
125 static int rockchip_rk3036_pll_wait_lock(struct rockchip_clk_pll *pll) in rockchip_rk3036_pll_wait_lock() argument
134 ret = readl_relaxed_poll_timeout(pll->reg_base + RK3036_PLLCON(1), in rockchip_rk3036_pll_wait_lock()
137 0, 1000); in rockchip_rk3036_pll_wait_lock()
139 pr_err("%s: timeout waiting for pll to lock\n", __func__); in rockchip_rk3036_pll_wait_lock()
144 static void rockchip_rk3036_pll_get_params(struct rockchip_clk_pll *pll, in rockchip_rk3036_pll_get_params() argument
149 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(0)); in rockchip_rk3036_pll_get_params()
150 rate->fbdiv = ((pllcon >> RK3036_PLLCON0_FBDIV_SHIFT) in rockchip_rk3036_pll_get_params()
152 rate->postdiv1 = ((pllcon >> RK3036_PLLCON0_POSTDIV1_SHIFT) in rockchip_rk3036_pll_get_params()
155 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(1)); in rockchip_rk3036_pll_get_params()
156 rate->refdiv = ((pllcon >> RK3036_PLLCON1_REFDIV_SHIFT) in rockchip_rk3036_pll_get_params()
158 rate->postdiv2 = ((pllcon >> RK3036_PLLCON1_POSTDIV2_SHIFT) in rockchip_rk3036_pll_get_params()
160 rate->dsmpd = ((pllcon >> RK3036_PLLCON1_DSMPD_SHIFT) in rockchip_rk3036_pll_get_params()
163 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2)); in rockchip_rk3036_pll_get_params()
164 rate->frac = ((pllcon >> RK3036_PLLCON2_FRAC_SHIFT) in rockchip_rk3036_pll_get_params()
171 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3036_pll_recalc_rate() local
175 rockchip_rk3036_pll_get_params(pll, &cur); in rockchip_rk3036_pll_recalc_rate()
180 if (cur.dsmpd == 0) { in rockchip_rk3036_pll_recalc_rate()
194 static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll, in rockchip_rk3036_pll_set_params() argument
197 const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; in rockchip_rk3036_pll_set_params()
198 struct clk_mux *pll_mux = &pll->pll_mux; in rockchip_rk3036_pll_set_params()
201 int rate_change_remuxed = 0; in rockchip_rk3036_pll_set_params()
206 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv, in rockchip_rk3036_pll_set_params()
207 rate->postdiv2, rate->dsmpd, rate->frac); in rockchip_rk3036_pll_set_params()
209 rockchip_rk3036_pll_get_params(pll, &cur); in rockchip_rk3036_pll_set_params()
210 cur.rate = 0; in rockchip_rk3036_pll_set_params()
212 if (!(pll->flags & ROCKCHIP_PLL_FIXED_MODE)) { in rockchip_rk3036_pll_set_params()
213 cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); in rockchip_rk3036_pll_set_params()
215 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); in rockchip_rk3036_pll_set_params()
220 /* update pll values */ in rockchip_rk3036_pll_set_params()
221 writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3036_PLLCON0_FBDIV_MASK, in rockchip_rk3036_pll_set_params()
223 HIWORD_UPDATE(rate->postdiv1, RK3036_PLLCON0_POSTDIV1_MASK, in rockchip_rk3036_pll_set_params()
225 pll->reg_base + RK3036_PLLCON(0)); in rockchip_rk3036_pll_set_params()
227 writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3036_PLLCON1_REFDIV_MASK, in rockchip_rk3036_pll_set_params()
229 HIWORD_UPDATE(rate->postdiv2, RK3036_PLLCON1_POSTDIV2_MASK, in rockchip_rk3036_pll_set_params()
231 HIWORD_UPDATE(rate->dsmpd, RK3036_PLLCON1_DSMPD_MASK, in rockchip_rk3036_pll_set_params()
233 pll->reg_base + RK3036_PLLCON(1)); in rockchip_rk3036_pll_set_params()
236 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2)); in rockchip_rk3036_pll_set_params()
238 pllcon |= rate->frac << RK3036_PLLCON2_FRAC_SHIFT; in rockchip_rk3036_pll_set_params()
239 writel_relaxed(pllcon, pll->reg_base + RK3036_PLLCON(2)); in rockchip_rk3036_pll_set_params()
241 /* wait for the pll to lock */ in rockchip_rk3036_pll_set_params()
242 ret = rockchip_rk3036_pll_wait_lock(pll); in rockchip_rk3036_pll_set_params()
244 pr_warn("%s: pll update unsuccessful, trying to restore old params\n", in rockchip_rk3036_pll_set_params()
246 rockchip_rk3036_pll_set_params(pll, &cur); in rockchip_rk3036_pll_set_params()
250 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); in rockchip_rk3036_pll_set_params()
258 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3036_pll_set_rate() local
262 __func__, __clk_get_name(hw->clk), drate, prate); in rockchip_rk3036_pll_set_rate()
265 rate = rockchip_get_pll_settings(pll, drate); in rockchip_rk3036_pll_set_rate()
267 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in rockchip_rk3036_pll_set_rate()
268 drate, __clk_get_name(hw->clk)); in rockchip_rk3036_pll_set_rate()
269 return -EINVAL; in rockchip_rk3036_pll_set_rate()
272 return rockchip_rk3036_pll_set_params(pll, rate); in rockchip_rk3036_pll_set_rate()
277 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3036_pll_enable() local
279 writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 0), in rockchip_rk3036_pll_enable()
280 pll->reg_base + RK3036_PLLCON(1)); in rockchip_rk3036_pll_enable()
281 rockchip_rk3036_pll_wait_lock(pll); in rockchip_rk3036_pll_enable()
283 return 0; in rockchip_rk3036_pll_enable()
288 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3036_pll_disable() local
291 RK3036_PLLCON1_PWRDOWN, 0), in rockchip_rk3036_pll_disable()
292 pll->reg_base + RK3036_PLLCON(1)); in rockchip_rk3036_pll_disable()
297 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3036_pll_is_enabled() local
298 u32 pllcon = readl(pll->reg_base + RK3036_PLLCON(1)); in rockchip_rk3036_pll_is_enabled()
305 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3036_pll_init() local
310 if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE)) in rockchip_rk3036_pll_init()
311 return 0; in rockchip_rk3036_pll_init()
314 rate = rockchip_get_pll_settings(pll, drate); in rockchip_rk3036_pll_init()
318 return 0; in rockchip_rk3036_pll_init()
320 rockchip_rk3036_pll_get_params(pll, &cur); in rockchip_rk3036_pll_init()
322 pr_debug("%s: pll %s@%lu: Hz\n", __func__, __clk_get_name(hw->clk), in rockchip_rk3036_pll_init()
324 pr_debug("old - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n", in rockchip_rk3036_pll_init()
327 pr_debug("new - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n", in rockchip_rk3036_pll_init()
328 rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2, in rockchip_rk3036_pll_init()
329 rate->dsmpd, rate->frac); in rockchip_rk3036_pll_init()
331 if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 || in rockchip_rk3036_pll_init()
332 rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 || in rockchip_rk3036_pll_init()
333 rate->dsmpd != cur.dsmpd || in rockchip_rk3036_pll_init()
334 (!cur.dsmpd && (rate->frac != cur.frac))) { in rockchip_rk3036_pll_init()
335 struct clk *parent = clk_get_parent(hw->clk); in rockchip_rk3036_pll_init()
339 __func__, __clk_get_name(hw->clk)); in rockchip_rk3036_pll_init()
340 return 0; in rockchip_rk3036_pll_init()
343 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n", in rockchip_rk3036_pll_init()
344 __func__, __clk_get_name(hw->clk)); in rockchip_rk3036_pll_init()
345 rockchip_rk3036_pll_set_params(pll, rate); in rockchip_rk3036_pll_init()
348 return 0; in rockchip_rk3036_pll_init()
369 * PLL used in RK3066, RK3188 and RK3288
374 #define RK3066_PLLCON(i) (i * 0x4)
375 #define RK3066_PLLCON0_OD_MASK 0xf
376 #define RK3066_PLLCON0_OD_SHIFT 0
377 #define RK3066_PLLCON0_NR_MASK 0x3f
379 #define RK3066_PLLCON1_NF_MASK 0x1fff
380 #define RK3066_PLLCON1_NF_SHIFT 0
381 #define RK3066_PLLCON2_NB_MASK 0xfff
382 #define RK3066_PLLCON2_NB_SHIFT 0
385 #define RK3066_PLLCON3_BYPASS (1 << 0)
387 static void rockchip_rk3066_pll_get_params(struct rockchip_clk_pll *pll, in rockchip_rk3066_pll_get_params() argument
392 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0)); in rockchip_rk3066_pll_get_params()
393 rate->nr = ((pllcon >> RK3066_PLLCON0_NR_SHIFT) in rockchip_rk3066_pll_get_params()
395 rate->no = ((pllcon >> RK3066_PLLCON0_OD_SHIFT) in rockchip_rk3066_pll_get_params()
398 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1)); in rockchip_rk3066_pll_get_params()
399 rate->nf = ((pllcon >> RK3066_PLLCON1_NF_SHIFT) in rockchip_rk3066_pll_get_params()
402 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(2)); in rockchip_rk3066_pll_get_params()
403 rate->nb = ((pllcon >> RK3066_PLLCON2_NB_SHIFT) in rockchip_rk3066_pll_get_params()
410 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3066_pll_recalc_rate() local
415 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(3)); in rockchip_rk3066_pll_recalc_rate()
417 pr_debug("%s: pll %s is bypassed\n", __func__, in rockchip_rk3066_pll_recalc_rate()
422 rockchip_rk3066_pll_get_params(pll, &cur); in rockchip_rk3066_pll_recalc_rate()
431 static int rockchip_rk3066_pll_set_params(struct rockchip_clk_pll *pll, in rockchip_rk3066_pll_set_params() argument
434 const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; in rockchip_rk3066_pll_set_params()
435 struct clk_mux *pll_mux = &pll->pll_mux; in rockchip_rk3066_pll_set_params()
437 int rate_change_remuxed = 0; in rockchip_rk3066_pll_set_params()
442 __func__, rate->rate, rate->nr, rate->no, rate->nf); in rockchip_rk3066_pll_set_params()
444 rockchip_rk3066_pll_get_params(pll, &cur); in rockchip_rk3066_pll_set_params()
445 cur.rate = 0; in rockchip_rk3066_pll_set_params()
447 cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); in rockchip_rk3066_pll_set_params()
449 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); in rockchip_rk3066_pll_set_params()
454 writel(HIWORD_UPDATE(RK3066_PLLCON3_RESET, RK3066_PLLCON3_RESET, 0), in rockchip_rk3066_pll_set_params()
455 pll->reg_base + RK3066_PLLCON(3)); in rockchip_rk3066_pll_set_params()
457 /* update pll values */ in rockchip_rk3066_pll_set_params()
458 writel(HIWORD_UPDATE(rate->nr - 1, RK3066_PLLCON0_NR_MASK, in rockchip_rk3066_pll_set_params()
460 HIWORD_UPDATE(rate->no - 1, RK3066_PLLCON0_OD_MASK, in rockchip_rk3066_pll_set_params()
462 pll->reg_base + RK3066_PLLCON(0)); in rockchip_rk3066_pll_set_params()
464 writel_relaxed(HIWORD_UPDATE(rate->nf - 1, RK3066_PLLCON1_NF_MASK, in rockchip_rk3066_pll_set_params()
466 pll->reg_base + RK3066_PLLCON(1)); in rockchip_rk3066_pll_set_params()
467 writel_relaxed(HIWORD_UPDATE(rate->nb - 1, RK3066_PLLCON2_NB_MASK, in rockchip_rk3066_pll_set_params()
469 pll->reg_base + RK3066_PLLCON(2)); in rockchip_rk3066_pll_set_params()
472 writel(HIWORD_UPDATE(0, RK3066_PLLCON3_RESET, 0), in rockchip_rk3066_pll_set_params()
473 pll->reg_base + RK3066_PLLCON(3)); in rockchip_rk3066_pll_set_params()
474 udelay(RK3066_PLL_RESET_DELAY(rate->nr)); in rockchip_rk3066_pll_set_params()
476 /* wait for the pll to lock */ in rockchip_rk3066_pll_set_params()
477 ret = rockchip_pll_wait_lock(pll); in rockchip_rk3066_pll_set_params()
479 pr_warn("%s: pll update unsuccessful, trying to restore old params\n", in rockchip_rk3066_pll_set_params()
481 rockchip_rk3066_pll_set_params(pll, &cur); in rockchip_rk3066_pll_set_params()
485 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); in rockchip_rk3066_pll_set_params()
493 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3066_pll_set_rate() local
500 rate = rockchip_get_pll_settings(pll, drate); in rockchip_rk3066_pll_set_rate()
502 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in rockchip_rk3066_pll_set_rate()
504 return -EINVAL; in rockchip_rk3066_pll_set_rate()
507 return rockchip_rk3066_pll_set_params(pll, rate); in rockchip_rk3066_pll_set_rate()
512 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3066_pll_enable() local
514 writel(HIWORD_UPDATE(0, RK3066_PLLCON3_PWRDOWN, 0), in rockchip_rk3066_pll_enable()
515 pll->reg_base + RK3066_PLLCON(3)); in rockchip_rk3066_pll_enable()
516 rockchip_pll_wait_lock(pll); in rockchip_rk3066_pll_enable()
518 return 0; in rockchip_rk3066_pll_enable()
523 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3066_pll_disable() local
526 RK3066_PLLCON3_PWRDOWN, 0), in rockchip_rk3066_pll_disable()
527 pll->reg_base + RK3066_PLLCON(3)); in rockchip_rk3066_pll_disable()
532 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3066_pll_is_enabled() local
533 u32 pllcon = readl(pll->reg_base + RK3066_PLLCON(3)); in rockchip_rk3066_pll_is_enabled()
540 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3066_pll_init() local
545 if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE)) in rockchip_rk3066_pll_init()
546 return 0; in rockchip_rk3066_pll_init()
549 rate = rockchip_get_pll_settings(pll, drate); in rockchip_rk3066_pll_init()
553 return 0; in rockchip_rk3066_pll_init()
555 rockchip_rk3066_pll_get_params(pll, &cur); in rockchip_rk3066_pll_init()
557 pr_debug("%s: pll %s@%lu: nr (%d:%d); no (%d:%d); nf(%d:%d), nb(%d:%d)\n", in rockchip_rk3066_pll_init()
558 __func__, clk_hw_get_name(hw), drate, rate->nr, cur.nr, in rockchip_rk3066_pll_init()
559 rate->no, cur.no, rate->nf, cur.nf, rate->nb, cur.nb); in rockchip_rk3066_pll_init()
560 if (rate->nr != cur.nr || rate->no != cur.no || rate->nf != cur.nf in rockchip_rk3066_pll_init()
561 || rate->nb != cur.nb) { in rockchip_rk3066_pll_init()
562 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n", in rockchip_rk3066_pll_init()
564 rockchip_rk3066_pll_set_params(pll, rate); in rockchip_rk3066_pll_init()
567 return 0; in rockchip_rk3066_pll_init()
588 * PLL used in RK3399
591 #define RK3399_PLLCON(i) (i * 0x4)
592 #define RK3399_PLLCON0_FBDIV_MASK 0xfff
593 #define RK3399_PLLCON0_FBDIV_SHIFT 0
594 #define RK3399_PLLCON1_REFDIV_MASK 0x3f
595 #define RK3399_PLLCON1_REFDIV_SHIFT 0
596 #define RK3399_PLLCON1_POSTDIV1_MASK 0x7
598 #define RK3399_PLLCON1_POSTDIV2_MASK 0x7
600 #define RK3399_PLLCON2_FRAC_MASK 0xffffff
601 #define RK3399_PLLCON2_FRAC_SHIFT 0
603 #define RK3399_PLLCON3_PWRDOWN BIT(0)
604 #define RK3399_PLLCON3_DSMPD_MASK 0x1
607 static int rockchip_rk3399_pll_wait_lock(struct rockchip_clk_pll *pll) in rockchip_rk3399_pll_wait_lock() argument
616 ret = readl_relaxed_poll_timeout(pll->reg_base + RK3399_PLLCON(2), in rockchip_rk3399_pll_wait_lock()
619 0, 1000); in rockchip_rk3399_pll_wait_lock()
621 pr_err("%s: timeout waiting for pll to lock\n", __func__); in rockchip_rk3399_pll_wait_lock()
626 static void rockchip_rk3399_pll_get_params(struct rockchip_clk_pll *pll, in rockchip_rk3399_pll_get_params() argument
631 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(0)); in rockchip_rk3399_pll_get_params()
632 rate->fbdiv = ((pllcon >> RK3399_PLLCON0_FBDIV_SHIFT) in rockchip_rk3399_pll_get_params()
635 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(1)); in rockchip_rk3399_pll_get_params()
636 rate->refdiv = ((pllcon >> RK3399_PLLCON1_REFDIV_SHIFT) in rockchip_rk3399_pll_get_params()
638 rate->postdiv1 = ((pllcon >> RK3399_PLLCON1_POSTDIV1_SHIFT) in rockchip_rk3399_pll_get_params()
640 rate->postdiv2 = ((pllcon >> RK3399_PLLCON1_POSTDIV2_SHIFT) in rockchip_rk3399_pll_get_params()
643 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2)); in rockchip_rk3399_pll_get_params()
644 rate->frac = ((pllcon >> RK3399_PLLCON2_FRAC_SHIFT) in rockchip_rk3399_pll_get_params()
647 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(3)); in rockchip_rk3399_pll_get_params()
648 rate->dsmpd = ((pllcon >> RK3399_PLLCON3_DSMPD_SHIFT) in rockchip_rk3399_pll_get_params()
655 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3399_pll_recalc_rate() local
659 rockchip_rk3399_pll_get_params(pll, &cur); in rockchip_rk3399_pll_recalc_rate()
664 if (cur.dsmpd == 0) { in rockchip_rk3399_pll_recalc_rate()
678 static int rockchip_rk3399_pll_set_params(struct rockchip_clk_pll *pll, in rockchip_rk3399_pll_set_params() argument
681 const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; in rockchip_rk3399_pll_set_params()
682 struct clk_mux *pll_mux = &pll->pll_mux; in rockchip_rk3399_pll_set_params()
685 int rate_change_remuxed = 0; in rockchip_rk3399_pll_set_params()
690 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv, in rockchip_rk3399_pll_set_params()
691 rate->postdiv2, rate->dsmpd, rate->frac); in rockchip_rk3399_pll_set_params()
693 rockchip_rk3399_pll_get_params(pll, &cur); in rockchip_rk3399_pll_set_params()
694 cur.rate = 0; in rockchip_rk3399_pll_set_params()
696 cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); in rockchip_rk3399_pll_set_params()
698 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); in rockchip_rk3399_pll_set_params()
702 /* update pll values */ in rockchip_rk3399_pll_set_params()
703 writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3399_PLLCON0_FBDIV_MASK, in rockchip_rk3399_pll_set_params()
705 pll->reg_base + RK3399_PLLCON(0)); in rockchip_rk3399_pll_set_params()
707 writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3399_PLLCON1_REFDIV_MASK, in rockchip_rk3399_pll_set_params()
709 HIWORD_UPDATE(rate->postdiv1, RK3399_PLLCON1_POSTDIV1_MASK, in rockchip_rk3399_pll_set_params()
711 HIWORD_UPDATE(rate->postdiv2, RK3399_PLLCON1_POSTDIV2_MASK, in rockchip_rk3399_pll_set_params()
713 pll->reg_base + RK3399_PLLCON(1)); in rockchip_rk3399_pll_set_params()
716 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2)); in rockchip_rk3399_pll_set_params()
718 pllcon |= rate->frac << RK3399_PLLCON2_FRAC_SHIFT; in rockchip_rk3399_pll_set_params()
719 writel_relaxed(pllcon, pll->reg_base + RK3399_PLLCON(2)); in rockchip_rk3399_pll_set_params()
721 writel_relaxed(HIWORD_UPDATE(rate->dsmpd, RK3399_PLLCON3_DSMPD_MASK, in rockchip_rk3399_pll_set_params()
723 pll->reg_base + RK3399_PLLCON(3)); in rockchip_rk3399_pll_set_params()
725 /* wait for the pll to lock */ in rockchip_rk3399_pll_set_params()
726 ret = rockchip_rk3399_pll_wait_lock(pll); in rockchip_rk3399_pll_set_params()
728 pr_warn("%s: pll update unsuccessful, trying to restore old params\n", in rockchip_rk3399_pll_set_params()
730 rockchip_rk3399_pll_set_params(pll, &cur); in rockchip_rk3399_pll_set_params()
734 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); in rockchip_rk3399_pll_set_params()
742 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3399_pll_set_rate() local
746 __func__, __clk_get_name(hw->clk), drate, prate); in rockchip_rk3399_pll_set_rate()
749 rate = rockchip_get_pll_settings(pll, drate); in rockchip_rk3399_pll_set_rate()
751 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in rockchip_rk3399_pll_set_rate()
752 drate, __clk_get_name(hw->clk)); in rockchip_rk3399_pll_set_rate()
753 return -EINVAL; in rockchip_rk3399_pll_set_rate()
756 return rockchip_rk3399_pll_set_params(pll, rate); in rockchip_rk3399_pll_set_rate()
761 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3399_pll_enable() local
763 writel(HIWORD_UPDATE(0, RK3399_PLLCON3_PWRDOWN, 0), in rockchip_rk3399_pll_enable()
764 pll->reg_base + RK3399_PLLCON(3)); in rockchip_rk3399_pll_enable()
765 rockchip_rk3399_pll_wait_lock(pll); in rockchip_rk3399_pll_enable()
767 return 0; in rockchip_rk3399_pll_enable()
772 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3399_pll_disable() local
775 RK3399_PLLCON3_PWRDOWN, 0), in rockchip_rk3399_pll_disable()
776 pll->reg_base + RK3399_PLLCON(3)); in rockchip_rk3399_pll_disable()
781 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3399_pll_is_enabled() local
782 u32 pllcon = readl(pll->reg_base + RK3399_PLLCON(3)); in rockchip_rk3399_pll_is_enabled()
789 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3399_pll_init() local
794 if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE)) in rockchip_rk3399_pll_init()
795 return 0; in rockchip_rk3399_pll_init()
798 rate = rockchip_get_pll_settings(pll, drate); in rockchip_rk3399_pll_init()
802 return 0; in rockchip_rk3399_pll_init()
804 rockchip_rk3399_pll_get_params(pll, &cur); in rockchip_rk3399_pll_init()
806 pr_debug("%s: pll %s@%lu: Hz\n", __func__, __clk_get_name(hw->clk), in rockchip_rk3399_pll_init()
808 pr_debug("old - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n", in rockchip_rk3399_pll_init()
811 pr_debug("new - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n", in rockchip_rk3399_pll_init()
812 rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2, in rockchip_rk3399_pll_init()
813 rate->dsmpd, rate->frac); in rockchip_rk3399_pll_init()
815 if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 || in rockchip_rk3399_pll_init()
816 rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 || in rockchip_rk3399_pll_init()
817 rate->dsmpd != cur.dsmpd || in rockchip_rk3399_pll_init()
818 (!cur.dsmpd && (rate->frac != cur.frac))) { in rockchip_rk3399_pll_init()
819 struct clk *parent = clk_get_parent(hw->clk); in rockchip_rk3399_pll_init()
823 __func__, __clk_get_name(hw->clk)); in rockchip_rk3399_pll_init()
824 return 0; in rockchip_rk3399_pll_init()
827 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n", in rockchip_rk3399_pll_init()
828 __func__, __clk_get_name(hw->clk)); in rockchip_rk3399_pll_init()
829 rockchip_rk3399_pll_set_params(pll, rate); in rockchip_rk3399_pll_init()
832 return 0; in rockchip_rk3399_pll_init()
853 * PLL used in RK3588
856 #define RK3588_PLLCON(i) (i * 0x4)
857 #define RK3588_PLLCON0_M_MASK 0x3ff
858 #define RK3588_PLLCON0_M_SHIFT 0
859 #define RK3588_PLLCON1_P_MASK 0x3f
860 #define RK3588_PLLCON1_P_SHIFT 0
861 #define RK3588_PLLCON1_S_MASK 0x7
863 #define RK3588_PLLCON2_K_MASK 0xffff
864 #define RK3588_PLLCON2_K_SHIFT 0
868 static int rockchip_rk3588_pll_wait_lock(struct rockchip_clk_pll *pll) in rockchip_rk3588_pll_wait_lock() argument
877 ret = readl_relaxed_poll_timeout(pll->reg_base + RK3588_PLLCON(6), in rockchip_rk3588_pll_wait_lock()
880 0, 1000); in rockchip_rk3588_pll_wait_lock()
882 pr_err("%s: timeout waiting for pll to lock\n", __func__); in rockchip_rk3588_pll_wait_lock()
887 static void rockchip_rk3588_pll_get_params(struct rockchip_clk_pll *pll, in rockchip_rk3588_pll_get_params() argument
892 pllcon = readl_relaxed(pll->reg_base + RK3588_PLLCON(0)); in rockchip_rk3588_pll_get_params()
893 rate->m = ((pllcon >> RK3588_PLLCON0_M_SHIFT) & RK3588_PLLCON0_M_MASK); in rockchip_rk3588_pll_get_params()
895 pllcon = readl_relaxed(pll->reg_base + RK3588_PLLCON(1)); in rockchip_rk3588_pll_get_params()
896 rate->p = ((pllcon >> RK3588_PLLCON1_P_SHIFT) & RK3588_PLLCON1_P_MASK); in rockchip_rk3588_pll_get_params()
897 rate->s = ((pllcon >> RK3588_PLLCON1_S_SHIFT) & RK3588_PLLCON1_S_MASK); in rockchip_rk3588_pll_get_params()
899 pllcon = readl_relaxed(pll->reg_base + RK3588_PLLCON(2)); in rockchip_rk3588_pll_get_params()
900 rate->k = ((pllcon >> RK3588_PLLCON2_K_SHIFT) & RK3588_PLLCON2_K_MASK); in rockchip_rk3588_pll_get_params()
905 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3588_pll_recalc_rate() local
909 rockchip_rk3588_pll_get_params(pll, &cur); in rockchip_rk3588_pll_recalc_rate()
924 if (pll->type == pll_rk3588_ddr) in rockchip_rk3588_pll_recalc_rate()
930 static int rockchip_rk3588_pll_set_params(struct rockchip_clk_pll *pll, in rockchip_rk3588_pll_set_params() argument
933 const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; in rockchip_rk3588_pll_set_params()
934 struct clk_mux *pll_mux = &pll->pll_mux; in rockchip_rk3588_pll_set_params()
936 int rate_change_remuxed = 0; in rockchip_rk3588_pll_set_params()
941 __func__, rate->rate, rate->p, rate->m, rate->s, rate->k); in rockchip_rk3588_pll_set_params()
943 rockchip_rk3588_pll_get_params(pll, &cur); in rockchip_rk3588_pll_set_params()
944 cur.rate = 0; in rockchip_rk3588_pll_set_params()
946 if (pll->type == pll_rk3588) { in rockchip_rk3588_pll_set_params()
947 cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); in rockchip_rk3588_pll_set_params()
949 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); in rockchip_rk3588_pll_set_params()
954 /* set pll power down */ in rockchip_rk3588_pll_set_params()
956 RK3588_PLLCON1_PWRDOWN, 0), in rockchip_rk3588_pll_set_params()
957 pll->reg_base + RK3399_PLLCON(1)); in rockchip_rk3588_pll_set_params()
959 /* update pll values */ in rockchip_rk3588_pll_set_params()
960 writel_relaxed(HIWORD_UPDATE(rate->m, RK3588_PLLCON0_M_MASK, RK3588_PLLCON0_M_SHIFT), in rockchip_rk3588_pll_set_params()
961 pll->reg_base + RK3399_PLLCON(0)); in rockchip_rk3588_pll_set_params()
963 writel_relaxed(HIWORD_UPDATE(rate->p, RK3588_PLLCON1_P_MASK, RK3588_PLLCON1_P_SHIFT) | in rockchip_rk3588_pll_set_params()
964 HIWORD_UPDATE(rate->s, RK3588_PLLCON1_S_MASK, RK3588_PLLCON1_S_SHIFT), in rockchip_rk3588_pll_set_params()
965 pll->reg_base + RK3399_PLLCON(1)); in rockchip_rk3588_pll_set_params()
967 writel_relaxed(HIWORD_UPDATE(rate->k, RK3588_PLLCON2_K_MASK, RK3588_PLLCON2_K_SHIFT), in rockchip_rk3588_pll_set_params()
968 pll->reg_base + RK3399_PLLCON(2)); in rockchip_rk3588_pll_set_params()
970 /* set pll power up */ in rockchip_rk3588_pll_set_params()
971 writel(HIWORD_UPDATE(0, RK3588_PLLCON1_PWRDOWN, 0), in rockchip_rk3588_pll_set_params()
972 pll->reg_base + RK3588_PLLCON(1)); in rockchip_rk3588_pll_set_params()
974 /* wait for the pll to lock */ in rockchip_rk3588_pll_set_params()
975 ret = rockchip_rk3588_pll_wait_lock(pll); in rockchip_rk3588_pll_set_params()
977 pr_warn("%s: pll update unsuccessful, trying to restore old params\n", in rockchip_rk3588_pll_set_params()
979 rockchip_rk3588_pll_set_params(pll, &cur); in rockchip_rk3588_pll_set_params()
982 if ((pll->type == pll_rk3588) && rate_change_remuxed) in rockchip_rk3588_pll_set_params()
983 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); in rockchip_rk3588_pll_set_params()
991 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3588_pll_set_rate() local
995 __func__, __clk_get_name(hw->clk), drate, prate); in rockchip_rk3588_pll_set_rate()
998 rate = rockchip_get_pll_settings(pll, drate); in rockchip_rk3588_pll_set_rate()
1000 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, in rockchip_rk3588_pll_set_rate()
1001 drate, __clk_get_name(hw->clk)); in rockchip_rk3588_pll_set_rate()
1002 return -EINVAL; in rockchip_rk3588_pll_set_rate()
1005 return rockchip_rk3588_pll_set_params(pll, rate); in rockchip_rk3588_pll_set_rate()
1010 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3588_pll_enable() local
1012 writel(HIWORD_UPDATE(0, RK3588_PLLCON1_PWRDOWN, 0), in rockchip_rk3588_pll_enable()
1013 pll->reg_base + RK3588_PLLCON(1)); in rockchip_rk3588_pll_enable()
1014 rockchip_rk3588_pll_wait_lock(pll); in rockchip_rk3588_pll_enable()
1016 return 0; in rockchip_rk3588_pll_enable()
1021 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3588_pll_disable() local
1023 writel(HIWORD_UPDATE(RK3588_PLLCON1_PWRDOWN, RK3588_PLLCON1_PWRDOWN, 0), in rockchip_rk3588_pll_disable()
1024 pll->reg_base + RK3588_PLLCON(1)); in rockchip_rk3588_pll_disable()
1029 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3588_pll_is_enabled() local
1030 u32 pllcon = readl(pll->reg_base + RK3588_PLLCON(1)); in rockchip_rk3588_pll_is_enabled()
1052 * Common registering of pll clocks
1065 struct rockchip_clk_pll *pll; in rockchip_clk_register_pll() local
1073 return ERR_PTR(-EINVAL); in rockchip_clk_register_pll()
1076 /* name the actual pll */ in rockchip_clk_register_pll()
1079 pll = kzalloc(sizeof(*pll), GFP_KERNEL); in rockchip_clk_register_pll()
1080 if (!pll) in rockchip_clk_register_pll()
1081 return ERR_PTR(-ENOMEM); in rockchip_clk_register_pll()
1083 /* create the mux on top of the real pll */ in rockchip_clk_register_pll()
1084 pll->pll_mux_ops = &clk_mux_ops; in rockchip_clk_register_pll()
1085 pll_mux = &pll->pll_mux; in rockchip_clk_register_pll()
1086 pll_mux->reg = ctx->reg_base + mode_offset; in rockchip_clk_register_pll()
1087 pll_mux->shift = mode_shift; in rockchip_clk_register_pll()
1089 pll_mux->mask = PLL_RK3328_MODE_MASK; in rockchip_clk_register_pll()
1091 pll_mux->mask = PLL_MODE_MASK; in rockchip_clk_register_pll()
1092 pll_mux->flags = 0; in rockchip_clk_register_pll()
1093 pll_mux->lock = &ctx->lock; in rockchip_clk_register_pll()
1094 pll_mux->hw.init = &init; in rockchip_clk_register_pll()
1101 pll_mux->flags |= CLK_MUX_HIWORD_MASK; in rockchip_clk_register_pll()
1103 /* the actual muxing is xin24m, pll-output, xin32k */ in rockchip_clk_register_pll()
1104 pll_parents[0] = parent_names[0]; in rockchip_clk_register_pll()
1110 init.ops = pll->pll_mux_ops; in rockchip_clk_register_pll()
1117 mux_clk = clk_register(NULL, &pll_mux->hw); in rockchip_clk_register_pll()
1121 /* now create the actual pll */ in rockchip_clk_register_pll()
1127 init.parent_names = &parent_names[0]; in rockchip_clk_register_pll()
1134 for (len = 0; rate_table[len].rate != 0; ) in rockchip_clk_register_pll()
1137 pll->rate_count = len; in rockchip_clk_register_pll()
1138 pll->rate_table = kmemdup_array(rate_table, in rockchip_clk_register_pll()
1139 pll->rate_count, in rockchip_clk_register_pll()
1140 sizeof(*pll->rate_table), in rockchip_clk_register_pll()
1142 WARN(!pll->rate_table, in rockchip_clk_register_pll()
1150 if (!pll->rate_table) in rockchip_clk_register_pll()
1156 if (!pll->rate_table || IS_ERR(ctx->grf)) in rockchip_clk_register_pll()
1162 if (!pll->rate_table) in rockchip_clk_register_pll()
1170 if (!pll->rate_table) in rockchip_clk_register_pll()
1177 pr_warn("%s: Unknown pll type for pll clk %s\n", in rockchip_clk_register_pll()
1181 pll->hw.init = &init; in rockchip_clk_register_pll()
1182 pll->type = pll_type; in rockchip_clk_register_pll()
1183 pll->reg_base = ctx->reg_base + con_offset; in rockchip_clk_register_pll()
1184 pll->lock_offset = grf_lock_offset; in rockchip_clk_register_pll()
1185 pll->lock_shift = lock_shift; in rockchip_clk_register_pll()
1186 pll->flags = clk_pll_flags; in rockchip_clk_register_pll()
1187 pll->lock = &ctx->lock; in rockchip_clk_register_pll()
1188 pll->ctx = ctx; in rockchip_clk_register_pll()
1190 pll_clk = clk_register(NULL, &pll->hw); in rockchip_clk_register_pll()
1192 pr_err("%s: failed to register pll clock %s : %ld\n", in rockchip_clk_register_pll()
1200 kfree(pll->rate_table); in rockchip_clk_register_pll()
1204 kfree(pll); in rockchip_clk_register_pll()