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/linux/arch/riscv/boot/dts/microchip/
H A Dmpfs.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
5 #include "dt-bindings/clock/microchip,mpfs-clock.h"
8 #address-cells = <2>;
9 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 timebase-frequency = <1000000>;
21 i-cache-block-size = <64>;
[all …]
H A Dmpfs-polarberry-fabric.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2022 Microchip Technology Inc */
5 fabric_clk3: fabric-clk3 {
6 compatible = "fixed-clock";
7 #clock-cells = <0>;
8 clock-frequency = <62500000>;
11 fabric_clk1: fabric-clk1 {
12 compatible = "fixed-clock";
13 #clock-cells = <0>;
14 clock-frequency = <125000000>;
[all …]
H A Dmpfs-m100pfs-fabric.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 fabric_clk3: fabric-clk3 {
6 compatible = "fixed-clock";
7 #clock-cells = <0>;
8 clock-frequency = <62500000>;
11 fabric_clk1: fabric-clk1 {
12 compatible = "fixed-clock";
13 #clock-cells = <0>;
14 clock-frequency = <125000000>;
18 compatible = "microchip,pcie-host-1.0";
[all …]
/linux/arch/riscv/boot/dts/sophgo/
H A Dcv1800b.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/pinctrl/pinctrl-cv1800b.h>
9 #include "cv180x-cpus.dtsi"
21 interrupt-parent = <&plic>;
22 dma-noncoherent;
25 compatible = "sophgo,cv1800b-pinctrl";
28 reg-names = "sys", "rtc";
31 clk: clock-controller@3002000 {
32 compatible = "sophgo,cv1800b-clk";
35 #clock-cells = <1>;
[all …]
H A Dsg2002.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/pinctrl/pinctrl-sg2002.h>
10 #include "cv180x-cpus.dtsi"
23 interrupt-parent = <&plic>;
24 dma-noncoherent;
27 compatible = "sophgo,sg2002-pinctrl";
30 reg-names = "sys", "rtc";
33 clk: clock-controller@3002000 {
34 compatible = "sophgo,sg2002-clk", "sophgo,sg2000-clk";
[all …]
H A Dcv1812h.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/pinctrl/pinctrl-cv1812h.h>
10 #include "cv180x-cpus.dtsi"
23 interrupt-parent = <&plic>;
24 dma-noncoherent;
27 compatible = "sophgo,cv1812h-pinctrl";
30 reg-names = "sys", "rtc";
33 clk: clock-controller@3002000 {
34 compatible = "sophgo,cv1812h-clk";
[all …]
/linux/drivers/irqchip/
H A Dirq-sifive-plic.c1 // SPDX-License-Identifier: GPL-2.0
6 #define pr_fmt(fmt) "riscv-plic: " fmt
25 * This driver implements a version of the RISC-V PLIC with the actual layout
28 * https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf
30 * The largest number supported by devices marked as 'sifive,plic-1.0.0', is
31 * 1024, of which device 0 is defined as non-existent by the RISC-V Privileged
100 u32 hwirq_mask = 1 << (hwirq % 32); in __plic_toggle()
112 raw_spin_lock_irqsave(&handler->enable_lock, flags); in plic_toggle()
113 __plic_toggle(handler->enable_base, hwirq, enable); in plic_toggle()
114 raw_spin_unlock_irqrestore(&handler->enable_lock, flags); in plic_toggle()
[all …]
H A Dirq-riscv-intc.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2017-2018 SiFive
8 #define pr_fmt(fmt) "riscv-intc: " fmt
31 unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG; in riscv_intc_irq()
46 * On RISC-V systems local interrupts are masked or unmasked by writing
54 if (IS_ENABLED(CONFIG_32BIT) && d->hwirq >= BITS_PER_LONG) in riscv_intc_irq_mask()
55 csr_clear(CSR_IEH, BIT(d->hwirq - BITS_PER_LONG)); in riscv_intc_irq_mask()
57 csr_clear(CSR_IE, BIT(d->hwirq)); in riscv_intc_irq_mask()
62 if (IS_ENABLED(CONFIG_32BIT) && d->hwirq >= BITS_PER_LONG) in riscv_intc_irq_unmask()
63 csr_set(CSR_IEH, BIT(d->hwirq - BITS_PER_LONG)); in riscv_intc_irq_unmask()
[all …]
/linux/arch/riscv/boot/dts/allwinner/
H A Dsun20i-d1s.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 // Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
6 #include "sunxi-d1s-t113.dtsi"
10 timebase-frequency = <24000000>;
11 #address-cells = <1>;
12 #size-cells = <0>;
19 d-cache-block-size = <64>;
20 d-cache-sets = <256>;
21 d-cache-size = <32768>;
22 i-cache-block-size = <64>;
[all …]
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Driscv,cpu-intc.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,cpu-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V Hart-Level Interrupt Controller (HLIC)
10 RISC-V cores include Control Status Registers (CSRs) which are local to
11 each CPU core (HART in RISC-V terminology) and can be read or written by
16 The RISC-V supervisor ISA manual specifies three interrupt sources that are
19 cores. The timer interrupt comes from an architecturally mandated real-
22 the HLIC, which are routed via the platform-level interrupt controller
[all …]
H A Dsophgo,sg2042-msi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/sophgo,sg2042-msi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen Wang <unicorn_wang@outlook.com>
14 PCIe MSI to PLIC interrupts.
17 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
22 - sophgo,sg2042-msi
23 - sophgo,sg2044-msi
27 - description: clear register
[all …]
H A Dstarfive,jh8100-intc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/starfive,jh8100-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 to handle high-level input interrupt signals. It also send the output
12 interrupt signal to RISC-V PLIC.
15 - Changhuang Liang <changhuang.liang@starfivetech.com>
19 const: starfive,jh8100-intc
22 maxItems: 1
26 maxItems: 1
[all …]
H A Dandestech,plicsw.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/andestech,plicsw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Andes machine-level software interrupt controller
10 In the Andes platform such as QiLai SoC, the PLIC module is instantiated a
12 controller (PLIC_SW). PLIC_SW directly connects to the machine-mode
13 inter-processor interrupt lines of CPUs, so RISC-V per-CPU local interrupt
15 generate machine-mode inter-processor interrupts through programming its
19 - Ben Zong-You Xie <ben717@andestech.com>
[all …]
/linux/arch/riscv/boot/dts/renesas/
H A Dr9a07g043f.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/interrupt-controller/irq.h>
16 #address-cells = <1>;
17 #size-cells = <0>;
18 timebase-frequency = <12000000>;
23 #cooling-cells = <2>;
27 riscv,isa-base = "rv64i";
28 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
31 mmu-type = "riscv,sv39";
32 i-cache-size = <0x8000>;
[all …]
/linux/arch/riscv/boot/dts/andes/
H A Dqilai.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/irq.h>
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <1>;
16 #size-cells = <0>;
17 timebase-frequency = <62500000>;
23 riscv,isa-base = "rv64i";
24 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
[all …]
/linux/Documentation/devicetree/bindings/mmc/
H A Dspacemit,sdhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Yixun Lan <dlan@gentoo.org>
13 - $ref: mmc-controller.yaml#
17 const: spacemit,k1-sdhci
20 maxItems: 1
23 maxItems: 1
27 - description: core clock, used by internal controller
28 - description: io clock, output for SD, SDIO, eMMC device
[all …]
/linux/arch/m68k/include/asm/
H A Dm5272sim.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5272sim.h -- ColdFire 5272 System Integration Module support.
31 #define MCFSIM_ICR1 (MCF_MBAR + 0x20) /* Intr Ctrl reg 1 */
68 #define MCFSIM_DCAR1 (MCF_MBAR + 0x58) /* DRAM 1 Address */
69 #define MCFSIM_DCMR1 (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg */
70 #define MCFSIM_DCCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control */
100 #define MCF_IRQ_EINT1 65 /* External Interrupt 1 */
104 #define MCF_IRQ_TIMER1 69 /* Timer 1 */
109 #define MCF_IRQ_UART1 74 /* UART 1 */
110 #define MCF_IRQ_PLIP 75 /* PLIC 2Khz Periodic */
[all …]
/linux/Documentation/devicetree/bindings/spi/
H A Dmicrochip,mpfs-spi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/microchip,mpfs-spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Conor Dooley <conor.dooley@microchip.com>
19 - items:
20 - enum:
21 - microchip,mpfs-qspi
22 - microchip,pic64gx-qspi
23 - const: microchip,coreqspi-rtl-v2
[all …]
H A Dspi-sifive.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-sifive.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Pragnesh Patel <pragnesh.patel@sifive.com>
11 - Paul Walmsley <paul.walmsley@sifive.com>
12 - Palmer Dabbelt <palmer@sifive.com>
15 - $ref: spi-controller.yaml#
20 - enum:
21 - sifive,fu540-c000-spi
[all …]
/linux/Documentation/devicetree/bindings/gpio/
H A Dsifive,gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Paul Walmsley <paul.walmsley@sifive.com>
15 - enum:
16 - sifive,fu540-c000-gpio
17 - sifive,fu740-c000-gpio
18 - canaan,k210-gpiohs
19 - const: sifive,gpio0
22 maxItems: 1
[all …]
H A Dmicrochip,mpfs-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/microchip,mpfs-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Conor Dooley <conor.dooley@microchip.com>
15 - enum:
16 - microchip,mpfs-gpio
17 - microchip,coregpio-rtl-v3
20 maxItems: 1
25 minItems: 1
[all …]
/linux/Documentation/devicetree/bindings/pwm/
H A Dpwm-sifive.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pwm/pwm-sifive.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Paul Walmsley <paul.walmsley@sifive.com>
19 numbers can be found here -
21 https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm
24 - $ref: pwm.yaml#
29 - enum:
30 - sifive,fu540-c000-pwm
[all …]
/linux/arch/powerpc/include/asm/
H A Dpaca.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * There are some pointers defined that are utilized by PLIC.
21 #include <asm/exception-64e.h>
23 #include <asm/exception-64s.h>
34 #include <asm-generic/mmiowb_types.h>
49 #define get_slb_shadow() (get_paca()->slb_shadow_ptr)
66 * read-only (after boot) fields in the first cacheline to
70 struct lppaca *lppaca_ptr; /* Pointer to LpPaca for PLIC */
96 /* this becomes non-zero. */
105 u64 dscr_default; /* per-CPU default DSCR */
[all …]
/linux/arch/riscv/boot/dts/sifive/
H A Dfu540-c000.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu540-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu540-c000", "sifive,fu540";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
[all …]
H A Dfu740-c000.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu740-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu740-c000", "sifive,fu740";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
29 i-cache-sets = <128>;
[all …]

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