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/linux/drivers/pinctrl/intel/
H A Dpinctrl-intel.h1 /* SPDX-License-Identifier: GPL-2.0 */
26 * struct intel_pingroup - Description about group of pins
27 * @grp: Generic data of the pin group (name and pins)
29 * @modes: If not %NULL this will hold mode for each pin in @pins
38 * struct intel_function - Description about a function
39 * @func: Generic data of the pin function (name and groups of pins)
48 * struct intel_padgroup - Hardware pad group information
50 * @base: Starting pin of this group
67 * enum - Special treatment for GPIO base in pad group
71 * @INTEL_GPIO_BASE_MATCH: matches with starting pin number
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/linux/Documentation/devicetree/bindings/display/
H A Dsolomon,ssd1307fb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Maxime Ripard <mripard@kernel.org>
11 - Javier Martinez Canillas <javierm@redhat.com>
17 - enum:
18 - solomon,ssd1305fb-i2c
19 - solomon,ssd1306fb-i2c
20 - solomon,ssd1307fb-i2c
21 - solomon,ssd1309fb-i2c
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H A Dsolomon,ssd-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/solomon,ssd-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Javier Martinez Canillas <javierm@redhat.com>
16 reset-gpios:
20 dc-gpios:
22 GPIO connected to the controller's D/C# (Data/Command) pin,
23 that is needed for 4-wire SPI to tell the controller if the
31 The default value is controller-dependent.
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/linux/include/linux/mfd/
H A Dsi476x-platform.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * include/media/si476x-platform.h -- Platform data specific definitions
185 * @xcload: Selects the amount of additional on-chip capacitance to
190 * but it will be layout dependent. Range is 0–0x3F i.e.
194 * @intsel: when set A1 pin becomes the interrupt pin; otherwise,
195 * INTB is the interrupt pin
197 * SI476X_BOOTLOADER - Boot loader
198 * SI476X_FM_RECEIVER - FM receiver
199 * SI476X_AM_RECEIVER - AM receiver
200 * SI476X_WB_RECEIVER - Weatherband receiver
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/linux/drivers/net/dsa/
H A Dvitesse-vsc73xx.h1 /* SPDX-License-Identifier: GPL-2.0 */
18 * struct vsc73xx_portinfo - port data structure: contains storage data
34 * struct vsc73xx - VSC73xx state container: main data structure
36 * @reset: The descriptor for the GPIO line tied to the reset pin
42 * @ops: Structure with hardware-dependent operations
65 * struct vsc73xx_ops - VSC73xx methods container
66 * @read: Method for register reading over the hardware-dependent interface
67 * @write: Method for register writing over the hardware-dependent interface
77 * struct vsc73xx_bridge_vlan - VSC73xx driver structure which keeps vlan
/linux/include/linux/platform_data/
H A Di2c-gpio.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * i2c-gpio interface to platform code
11 * struct i2c_gpio_platform_data - Platform-dependent data for i2c-gpio
15 * @sda_is_open_drain: SDA is configured as open drain, i.e. the pin
17 * gpio_get_value() must return the actual pin state even if the
18 * pin is configured as an output.
21 * @sda_has_no_pullup: SDA is used in a non-compliant way and has no pull-up.
22 * Therefore disable open-drain.
26 * @scl_has_no_pullup: SCL is used in a non-compliant way and has no pull-up.
27 * Therefore disable open-drain.
/linux/drivers/pinctrl/visconti/
H A Dpinctrl-common.h1 /* SPDX-License-Identifier: GPL-2.0 */
13 /* PIN */
18 struct pinctrl_pin_desc pin; member
28 .pin = _pin, \
79 /* chip dependent data */
/linux/arch/arm/mach-s3c/
H A Dgpio-cfg.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 * S3C Platform - GPIO pin configuration
12 * pin configuration done such as setting a pin to input or output or
13 * changing the pull-{up,down} configurations.
27 /* forward declaration if gpio-core.h hasn't been included */
41 * per-bank configuration information that other systems such as the
64 /* Defines for generic pin configurations */
73 * s3c_gpio_cfgpin() - Change the GPIO function of a pin.
74 * @pin pin The pin number to configure.
75 * @to to The configuration for the pin's function.
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H A Dgpio-samsung.c1 // SPDX-License-Identifier: GPL-2.0
3 // Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
11 // Samsung - GPIOlib support
31 #include "regs-gpio.h"
32 #include "gpio-samsung.h"
35 #include "gpio-core.h"
36 #include "gpio-cfg.h"
37 #include "gpio-cfg-helpers.h"
43 void __iomem *reg = chip->base + 0x08; in samsung_gpio_setpull_updown()
58 void __iomem *reg = chip->base + 0x08; in samsung_gpio_getpull_updown()
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/linux/sound/pci/hda/
H A Dhda_jack.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Jack-detection handling for HD-audio
35 /* jack-detection stuff */
36 unsigned int pin_sense; /* cached pin-sense value */
37 unsigned int jack_detect:1; /* capable of jack-detection? */
40 unsigned int block_report:1; /* in a transitional state - do not report to userspace */
42 hda_nid_t gated_jack; /* gated is dependent on this jack */
58 * snd_hda_jack_tbl_get - query the jack-table entry for the given NID
60 * @nid: pin NID to refer to
85 * snd_hda_jack_detect_enable - enable the jack-detection
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/linux/include/linux/can/
H A Dbittiming.h1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2020 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de>
15 #define CAN_BITRATE_UNKNOWN (-1U)
21 * struct can_tdc - CAN FD Transmission Delay Compensation parameters
23 * At high bit rates, the propagation delay from the TX pin to the RX
24 * pin of the transceiver causes measurement errors: the sample point
25 * on the RX pin might occur on the previous bit.
27 * To solve this issue, ISO 11898-1 introduces in section 11.3.3
29 * equal to the distance from the start of the bit time on the TX pin
30 * to the actual measurement on the RX pin.
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/linux/Documentation/devicetree/bindings/pinctrl/
H A Drenesas,rzg2l-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/{G2L,V2L} combined Pin and GPIO controller
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
14 The Renesas SoCs of the RZ/{G2L,V2L} alike series feature a combined Pin and
16 Pin multiplexing and GPIO configuration is performed on a per-pin basis.
19 Up to 8 different alternate function modes exist for each single pin.
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/linux/include/media/i2c/
H A Dadv7604.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * adv7604 - Analog Devices ADV7604 video decoder driver
29 ADV7604_BUS_ORDER_GRB, /* Swap 1-2 */
30 ADV7604_BUS_ORDER_RBG, /* Swap 2-3 */
31 ADV7604_BUS_ORDER_BGR, /* Swap 1-3 */
87 /* Platform dependent definition */
89 /* DIS_PWRDNB: 1 if the PWRDNB pin is unused and unconnected */
106 /* Configuration of the INT1 pin */
/linux/Documentation/devicetree/bindings/sound/
H A Dcirrus,cs42l42.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - patches@opensource.cirrus.com
13 The CS42L42 is a low-power audio codec designed for portable applications.
14 It provides a high-dynamic range, stereo DAC for audio playback and a mono
15 high-dynamic-range ADC for audio capture. There is an integrated headset
21 - cirrus,cs42l42
22 - cirrus,cs42l83
29 VP-supply:
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/linux/arch/x86/include/asm/
H A Dvmxfeatures.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 #define NVMXINTS 5 /* N 32-bit words worth of info */
16 /* Pin-Based VM-Execution Controls, EPT/VPID, APIC and VM-Functions, word 0 */
17 #define VMX_FEATURE_INTR_EXITING ( 0*32+ 0) /* VM-Exit on vectored interrupts */
18 #define VMX_FEATURE_NMI_EXITING ( 0*32+ 3) /* VM-Exit on NMIs */
23 /* EPT/VPID features, scattered to bits 16-23 */
28 #define VMX_FEATURE_EPT_5LEVEL ( 0*32+ 20) /* "ept_5level" 5-level EPT paging */
30 /* Aggregated APIC features 24-27 */
34 /* VM-Functions, shifted to bits 28-31 */
37 /* Primary Processor-Based VM-Execution Controls, word 1 */
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/linux/Documentation/filesystems/xfs/
H A Dxfs-delayed-logging-design.rst1 .. SPDX-License-Identifier: GPL-2.0
33 details logged are made up of the changes to in-core structures rather than
34 on-disk structures. Other objects - typically buffers - have their physical
49 together are different and are dependent on the object and/or modification being
64 place. This means that permanent transactions can be used for one-shot
65 modifications, but one-shot reservations cannot be used for permanent
68 In the code, a one-shot transaction pattern looks somewhat like this::
97 While this might look similar to a one-shot transaction, there is an important
123 the on-disk journal.
165 transaction, we have to reserve enough space to record a full leaf-to-root split
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/linux/Documentation/devicetree/bindings/net/
H A Dsti-dwmac.txt10 - compatible : "st,stih407-dwmac"
11 - st,syscon : Should be phandle/offset pair. The phandle to the syscon node which
13 - st,gmac_en: this is to enable the gmac into a dedicated sysctl control
15 - pinctrl-0: pin-control for all the MII mode supported.
18 - resets : phandle pointing to the system reset controller with correct
20 - st,ext-phyclk: valid only for RMII where PHY can generate 50MHz clock or
22 - st,tx-retime-src: This specifies which clk is wired up to the mac for
23 retimeing tx lines. This is totally board dependent and can take one of the
26 - sti-ethclk: this is the phy clock.
27 - sti-clkconf: this is an extra sysconfig register, available in new SoCs,
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/linux/arch/m68k/coldfire/
H A Dm527x.c1 // SPDX-License-Identifier: GPL-2.0
5 * m527x.c -- platform support for ColdFire 527x based boards
7 * Sub-architcture dependent initialization code for the Freescale
10 * Copyright (C) 1999-2004, Greg Ungerer (gerg@snapgear.com)
11 * Copyright (C) 2001-2004, SnapGear Inc. (www.snapgear.com)
45 CLKDEV_INIT("imx1-i2c.0", NULL, &clk_sys),
77 /* setup Port FECI2C Pin Assignment Register for I2C */ in m527x_i2c_init()
85 /* setup Port FECI2C Pin Assignment Register for I2C */ in m527x_i2c_init()
101 * External Pin Mask Setting & Enable External Pin for Interface in m527x_uarts_init()
114 /* Set multi-function pins to ethernet mode for fec0 */ in m527x_fec_init()
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/linux/Documentation/ABI/testing/
H A Dsysfs-ptp41 Write integer to re-configure it.
89 pin offered by the PTP hardware clock. The file name
90 is the hardware dependent pin name. Reading from this
110 This write-only file enables or disables external
128 This write-only file enables or disables periodic
139 This write-only file enables or disables delivery of
/linux/drivers/media/dvb-frontends/drx39xyj/
H A Ddrxj.h3 Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc.
38 /*-------------------------------------------------------------------------
40 -------------------------------------------------------------------------*/
45 /* Check DRX-J specific dap condition */
55 /*-------------------------------------------------------------------------
57 -------------------------------------------------------------------------*/
151 * AGC status information from the DRXJ-IQM-AF.
175 u16 output_level; /* range dependent on AGC */
176 u16 min_output_level; /* range dependent on AGC */
177 u16 max_output_level; /* range dependent on AGC */
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/linux/drivers/pinctrl/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
7 bool "Pin controllers"
15 bool "Support pin multiplexing controllers" if COMPILE_TEST
22 bool "Support pin configuration controllers" if COMPILE_TEST
35 bool "AMD GPIO pin control"
53 tristate "Apple SoC GPIO pin controller driver"
66 will be called pinctrl-apple-gpio.
69 bool "Axis ARTPEC-6 pin controller driver"
74 This is the driver for the Axis ARTPEC-6 pin controller. This driver
75 supports pin function multiplexing as well as pin bias and drive
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/linux/Documentation/networking/pse-pd/
H A Dpse-pi.rst1 .. SPDX-License-Identifier: GPL-2.0
9 eight-pin modular jack, commonly known as the Ethernet RJ45 port. This
14 ---------------------------
19 - Section "33.2.3 PI pin assignments" covers the pin assignments for PoE
21 - Section "145.2.4 PSE PI" addresses the configuration for PoE systems that
25 -------------------------------
31 two pairs of wires, SPE operates on a simpler model due to its single-pair
32 design. As a result, the complexities of choosing between alternative pin
33 assignments for power delivery, as described in the PSE PI for multi-pair
37 --------------------
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/linux/Documentation/driver-api/
H A Dmtdnand.rst10 The generic NAND driver supports almost all NAND and AG-AND based chips
31 --------------------------
37 - [MTD Interface]
43 - [NAND Interface]
48 - [GENERIC]
53 - [DEFAULT]
59 can set the functions which should be replaced by board dependent
65 -------------------------------
71 - [INTERN]
77 - [REPLACEABLE]
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/linux/Documentation/devicetree/bindings/mtd/
H A Draw-nand-chip.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/raw-nand-chip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 - $ref: nand-chip.yaml#
21 The interpretation of these parameters is implementation-defined, so
28 pattern: "^nand@[a-f0-9]$"
32 Contains the chip-select IDs.
34 nand-ecc-placement:
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/linux/drivers/gpu/drm/radeon/
H A Datombios.h2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
214 UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios,
397 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
403 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
410 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
504 …UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0)…
536 #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode
544 …bDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS)
549 … //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode
815 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disab…
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