xref: /linux/arch/m68k/coldfire/m527x.c (revision 762f99f4f3cb41a775b5157dd761217beba65873)
1b2441318SGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0
2f86b9e03SGreg Ungerer /***************************************************************************/
3f86b9e03SGreg Ungerer 
4f86b9e03SGreg Ungerer /*
5ece9ae65SGreg Ungerer  *	m527x.c  -- platform support for ColdFire 527x based boards
6f86b9e03SGreg Ungerer  *
7f86b9e03SGreg Ungerer  *	Sub-architcture dependent initialization code for the Freescale
8ece9ae65SGreg Ungerer  *	5270/5271 and 5274/5275 CPUs.
9f86b9e03SGreg Ungerer  *
10f86b9e03SGreg Ungerer  *	Copyright (C) 1999-2004, Greg Ungerer (gerg@snapgear.com)
11f86b9e03SGreg Ungerer  *	Copyright (C) 2001-2004, SnapGear Inc. (www.snapgear.com)
12f86b9e03SGreg Ungerer  */
13f86b9e03SGreg Ungerer 
14f86b9e03SGreg Ungerer /***************************************************************************/
15f86b9e03SGreg Ungerer 
16*63aadb77SArnd Bergmann #include <linux/clkdev.h>
17f86b9e03SGreg Ungerer #include <linux/kernel.h>
18f86b9e03SGreg Ungerer #include <linux/param.h>
19f86b9e03SGreg Ungerer #include <linux/init.h>
20f86b9e03SGreg Ungerer #include <linux/io.h>
21f86b9e03SGreg Ungerer #include <asm/machdep.h>
22f86b9e03SGreg Ungerer #include <asm/coldfire.h>
23f86b9e03SGreg Ungerer #include <asm/mcfsim.h>
24f86b9e03SGreg Ungerer #include <asm/mcfuart.h>
25f86b9e03SGreg Ungerer #include <asm/mcfclk.h>
26f86b9e03SGreg Ungerer 
27f86b9e03SGreg Ungerer /***************************************************************************/
28f86b9e03SGreg Ungerer 
29f86b9e03SGreg Ungerer DEFINE_CLK(pll, "pll.0", MCF_CLK);
30f86b9e03SGreg Ungerer DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
31f86b9e03SGreg Ungerer 
32*63aadb77SArnd Bergmann static struct clk_lookup m527x_clk_lookup[] = {
33*63aadb77SArnd Bergmann 	CLKDEV_INIT(NULL, "pll.0", &clk_pll),
34*63aadb77SArnd Bergmann 	CLKDEV_INIT(NULL, "sys.0", &clk_sys),
35*63aadb77SArnd Bergmann 	CLKDEV_INIT("mcfpit.0", NULL, &clk_pll),
36*63aadb77SArnd Bergmann 	CLKDEV_INIT("mcfpit.1", NULL, &clk_pll),
37*63aadb77SArnd Bergmann 	CLKDEV_INIT("mcfpit.2", NULL, &clk_pll),
38*63aadb77SArnd Bergmann 	CLKDEV_INIT("mcfpit.3", NULL, &clk_pll),
39*63aadb77SArnd Bergmann 	CLKDEV_INIT("mcfuart.0", NULL, &clk_sys),
40*63aadb77SArnd Bergmann 	CLKDEV_INIT("mcfuart.1", NULL, &clk_sys),
41*63aadb77SArnd Bergmann 	CLKDEV_INIT("mcfuart.2", NULL, &clk_sys),
42*63aadb77SArnd Bergmann 	CLKDEV_INIT("mcfqspi.0", NULL, &clk_sys),
43*63aadb77SArnd Bergmann 	CLKDEV_INIT("fec.0", NULL, &clk_sys),
44*63aadb77SArnd Bergmann 	CLKDEV_INIT("fec.1", NULL, &clk_sys),
45*63aadb77SArnd Bergmann 	CLKDEV_INIT("imx1-i2c.0", NULL, &clk_sys),
46f86b9e03SGreg Ungerer };
47f86b9e03SGreg Ungerer 
48f86b9e03SGreg Ungerer /***************************************************************************/
49f86b9e03SGreg Ungerer 
m527x_qspi_init(void)50f86b9e03SGreg Ungerer static void __init m527x_qspi_init(void)
51f86b9e03SGreg Ungerer {
52f86b9e03SGreg Ungerer #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
53f86b9e03SGreg Ungerer #if defined(CONFIG_M5271)
54f86b9e03SGreg Ungerer 	u16 par;
55f86b9e03SGreg Ungerer 
56f86b9e03SGreg Ungerer 	/* setup QSPS pins for QSPI with gpio CS control */
57f86b9e03SGreg Ungerer 	writeb(0x1f, MCFGPIO_PAR_QSPI);
58f86b9e03SGreg Ungerer 	/* and CS2 & CS3 as gpio */
59f86b9e03SGreg Ungerer 	par = readw(MCFGPIO_PAR_TIMER);
60f86b9e03SGreg Ungerer 	par &= 0x3f3f;
61f86b9e03SGreg Ungerer 	writew(par, MCFGPIO_PAR_TIMER);
62f86b9e03SGreg Ungerer #elif defined(CONFIG_M5275)
63f86b9e03SGreg Ungerer 	/* setup QSPS pins for QSPI with gpio CS control */
64f86b9e03SGreg Ungerer 	writew(0x003e, MCFGPIO_PAR_QSPI);
65f86b9e03SGreg Ungerer #endif
66f86b9e03SGreg Ungerer #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
67f86b9e03SGreg Ungerer }
68f86b9e03SGreg Ungerer 
69f86b9e03SGreg Ungerer /***************************************************************************/
70f86b9e03SGreg Ungerer 
m527x_i2c_init(void)712d24b532SSteven King static void __init m527x_i2c_init(void)
722d24b532SSteven King {
732d24b532SSteven King #if IS_ENABLED(CONFIG_I2C_IMX)
742d24b532SSteven King #if defined(CONFIG_M5271)
752d24b532SSteven King 	u8 par;
762d24b532SSteven King 
772d24b532SSteven King 	/* setup Port FECI2C Pin Assignment Register for I2C */
782d24b532SSteven King 	/*  set PAR_SCL to SCL and PAR_SDA to SDA */
792d24b532SSteven King 	par = readb(MCFGPIO_PAR_FECI2C);
802d24b532SSteven King 	par |= 0x0f;
812d24b532SSteven King 	writeb(par, MCFGPIO_PAR_FECI2C);
822d24b532SSteven King #elif defined(CONFIG_M5275)
832d24b532SSteven King 	u16 par;
842d24b532SSteven King 
852d24b532SSteven King 	/* setup Port FECI2C Pin Assignment Register for I2C */
862d24b532SSteven King 	/*  set PAR_SCL to SCL and PAR_SDA to SDA */
872d24b532SSteven King 	par = readw(MCFGPIO_PAR_FECI2C);
882d24b532SSteven King 	par |= 0x0f;
892d24b532SSteven King 	writew(par, MCFGPIO_PAR_FECI2C);
902d24b532SSteven King #endif
912d24b532SSteven King #endif /* IS_ENABLED(CONFIG_I2C_IMX) */
922d24b532SSteven King }
932d24b532SSteven King 
942d24b532SSteven King /***************************************************************************/
952d24b532SSteven King 
m527x_uarts_init(void)96f86b9e03SGreg Ungerer static void __init m527x_uarts_init(void)
97f86b9e03SGreg Ungerer {
98f86b9e03SGreg Ungerer 	u16 sepmask;
99f86b9e03SGreg Ungerer 
100f86b9e03SGreg Ungerer 	/*
101f86b9e03SGreg Ungerer 	 * External Pin Mask Setting & Enable External Pin for Interface
102f86b9e03SGreg Ungerer 	 */
103f86b9e03SGreg Ungerer 	sepmask = readw(MCFGPIO_PAR_UART);
104f86b9e03SGreg Ungerer 	sepmask |= UART0_ENABLE_MASK | UART1_ENABLE_MASK | UART2_ENABLE_MASK;
105f86b9e03SGreg Ungerer 	writew(sepmask, MCFGPIO_PAR_UART);
106f86b9e03SGreg Ungerer }
107f86b9e03SGreg Ungerer 
108f86b9e03SGreg Ungerer /***************************************************************************/
109f86b9e03SGreg Ungerer 
m527x_fec_init(void)110f86b9e03SGreg Ungerer static void __init m527x_fec_init(void)
111f86b9e03SGreg Ungerer {
112f86b9e03SGreg Ungerer 	u8 v;
113f86b9e03SGreg Ungerer 
114f86b9e03SGreg Ungerer 	/* Set multi-function pins to ethernet mode for fec0 */
115f86b9e03SGreg Ungerer #if defined(CONFIG_M5271)
116f86b9e03SGreg Ungerer 	v = readb(MCFGPIO_PAR_FECI2C);
117f86b9e03SGreg Ungerer 	writeb(v | 0xf0, MCFGPIO_PAR_FECI2C);
118f86b9e03SGreg Ungerer #else
1196e420613SGreg Ungerer 	u16 par;
1206e420613SGreg Ungerer 
121f86b9e03SGreg Ungerer 	par = readw(MCFGPIO_PAR_FECI2C);
122f86b9e03SGreg Ungerer 	writew(par | 0xf00, MCFGPIO_PAR_FECI2C);
123f86b9e03SGreg Ungerer 	v = readb(MCFGPIO_PAR_FEC0HL);
124f86b9e03SGreg Ungerer 	writeb(v | 0xc0, MCFGPIO_PAR_FEC0HL);
125f86b9e03SGreg Ungerer 
126f86b9e03SGreg Ungerer 	/* Set multi-function pins to ethernet mode for fec1 */
127f86b9e03SGreg Ungerer 	par = readw(MCFGPIO_PAR_FECI2C);
128f86b9e03SGreg Ungerer 	writew(par | 0xa0, MCFGPIO_PAR_FECI2C);
129f86b9e03SGreg Ungerer 	v = readb(MCFGPIO_PAR_FEC1HL);
130f86b9e03SGreg Ungerer 	writeb(v | 0xc0, MCFGPIO_PAR_FEC1HL);
131f86b9e03SGreg Ungerer #endif
132f86b9e03SGreg Ungerer }
133f86b9e03SGreg Ungerer 
134f86b9e03SGreg Ungerer /***************************************************************************/
135f86b9e03SGreg Ungerer 
config_BSP(char * commandp,int size)136f86b9e03SGreg Ungerer void __init config_BSP(char *commandp, int size)
137f86b9e03SGreg Ungerer {
138f86b9e03SGreg Ungerer 	mach_sched_init = hw_timer_init;
139f86b9e03SGreg Ungerer 	m527x_uarts_init();
140f86b9e03SGreg Ungerer 	m527x_fec_init();
141f86b9e03SGreg Ungerer 	m527x_qspi_init();
1422d24b532SSteven King 	m527x_i2c_init();
143*63aadb77SArnd Bergmann 	clkdev_add_table(m527x_clk_lookup, ARRAY_SIZE(m527x_clk_lookup));
144f86b9e03SGreg Ungerer }
145f86b9e03SGreg Ungerer 
146f86b9e03SGreg Ungerer /***************************************************************************/
147