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/freebsd/sys/dev/phy/
H A Dphy.c1 /*-
43 #include <dev/phy/phy.h>
44 #include <dev/phy/phy_internal.h>
50 MALLOC_DEFINE(M_PHY, "phy", "Phy framework");
52 /* Default phy methods. */
59 * Phy controller methods.
72 SX_SYSINIT(phy_topology, &phynode_topo_lock, "Phy topology lock");
74 /* ----------------------------------------------------------------------------
76 * Default phy methods for base class.
104 /* ----------------------------------------------------------------------------
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/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dethernet-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David S. Miller <davem@davemloft.net>
19 max-speed:
24 nvmem-cells:
29 nvmem-cell-names:
30 const: mac-address
32 phy-connection-type:
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H A Dethernet-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ethernet PHY Common Properties
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
14 # The dt-schema tools will generate a select statement first by using
21 pattern: "^ethernet-phy(@[a-f0-9]+)?$"
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H A Dethernet-phy-package.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-phy-package.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ethernet PHY Package Common Properties
10 - Christian Marangi <ansuelsmth@gmail.com>
13 PHY packages are multi-port Ethernet PHY of the same family
14 and each Ethernet PHY is affected by the global configuration
15 of the PHY package.
17 Each reg of the PHYs defined in the PHY package node is
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H A Dmotorcomm,yt8xxx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id
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H A Dadi,adin.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
4 $id: http://devicetree.org/schemas/net/adi,adin.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices ADIN1200/ADIN1300 PHY
10 - Marcelo Schmitt <marcelo.schmitt@analog.com>
16 - $ref: ethernet-phy.yaml#
19 adi,rx-internal-delay-ps:
21 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
22 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
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H A Dmarvell,pp2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/marvell,pp2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marcin Wojtas <mw@semihalf.com>
11 - Russell King <linux@armlinux.org>
21 - marvell,armada-375-pp2
22 - marvell,armada-7k-pp22
28 "#address-cells":
31 "#size-cells":
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H A Dmarvell-pp2.txt7 - compatible: should be one of:
8 "marvell,armada-375-pp2"
9 "marvell,armada-7k-pp2"
10 - reg: addresses and length of the register sets for the device.
11 For "marvell,armada-375-pp2", must contain the following register
13 - common controller registers
14 - LMS registers
15 - one register area per Ethernet port
16 For "marvell,armada-7k-pp2" used by 7K/8K and CN913X, must contain the following register
18 - packet processor registers
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H A Dsocionext,uniphier-ave4.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/socionext,uniphier-ave4.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
19 - socionext,uniphier-pro4-ave4
20 - socionext,uniphier-pxs2-ave4
21 - socionext,uniphier-ld11-ave4
22 - socionext,uniphier-ld20-ave4
23 - socionext,uniphier-pxs3-ave4
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/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dintel,combo-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/intel,combo-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dilip Kota <eswara.kota@linux.intel.com>
14 controllers. A single Combophy provides two PHY instances.
18 pattern: "combophy(@.*|-([0-9]|[1-9][0-9]+))?$"
22 - const: intel,combophy-lgm
23 - const: intel,combo-phy
30 - description: ComboPhy core registers
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H A Dbrcm,ns2-drd-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/brcm,ns2-drd-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom Northstar2 USB2 Dual Role Device PHY
10 - Florian Fainelli <florian.fainelli@broadcom.com>
11 - Hauke Mehrtens <hauke@hauke-m.de>
12 - Rafał Miłecki <zajec5@gmail.com>
16 const: brcm,ns2-drd-phy
20 - description: DRD ICFG configurations
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H A Dbrcm,ns2-drd-phy.txt1 BROADCOM NORTHSTAR2 USB2 (DUAL ROLE DEVICE) PHY
4 - compatible: brcm,ns2-drd-phy
5 - reg: offset and length of the NS2 PHY related registers.
6 - reg-names
8 icfg - for DRD ICFG configurations
9 rst-ctrl - for DRD IDM reset
10 crmu-ctrl - for CRMU core vdd, PHY and PHY PLL reset
11 usb2-strap - for port over current polarity reversal
12 - #phy-cells: Must be 0. No args required.
13 - vbus-gpios: vbus gpio binding
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H A Dmotorola,cpcap-usb-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/motorola,cpcap-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Motorola CPCAP PMIC USB PHY
10 - Tony Lindgren <tony@atomide.com>
15 - motorola,cpcap-usb-phy
16 - motorola,mapphone-cpcap-usb-phy
18 '#phy-cells':
22 description: CPCAP PMIC interrupts used by the USB PHY
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H A Dst,spear1310-miphy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/st,spear1310-miphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Pratyush Anand <pratyush.anand@gmail.com>
13 ST Microelectronics SPEAr miphy is a phy controller supporting PCIe and SATA.
18 - st,spear1310-miphy
19 - st,spear1340-miphy
28 '#phy-cells':
33 phy-id:
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H A Dti-phy.txt1 TI PHY: DT DOCUMENTATION FOR PHYs in TI PLATFORMs
3 OMAP CONTROL PHY
6 - compatible: Should be one of
7 "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.
8 "ti,control-phy-usb
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H A Dsocionext,uniphier-usb2-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb2-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier USB2 PHY
10 This describes the devicetree bindings for PHY interface built into
13 controller doesn't include its own High-Speed PHY. This needs to specify
14 USB2 PHY instead of USB3 HS-PHY.
17 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
22 - socionext,uniphier-pro4-usb2-phy
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/freebsd/sys/contrib/device-tree/Bindings/net/dsa/
H A Dsja1105.txt6 - compatible:
8 - "nxp,sja1105e"
9 - "nxp,sja1105t"
10 - "nxp,sja1105p"
11 - "nxp,sja1105q"
12 - "nxp,sja1105r"
13 - "nxp,sja1105s"
15 Although the device ID could be detected at runtime, explicit bindings
18 and the non-SGMII devices, while pin-compatible, are not equal in terms
24 - sja1105,role-mac:
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H A Dnxp,sja1105.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id
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/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dsbc8641d.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
12 /include/ "mpc8641si-pre.dtsi"
35 compatible = "cfi-flash";
37 bank-width = <2>;
38 device-width = <2>;
39 #address-cells = <1>;
40 #size-cells = <1>;
44 read-only;
49 read-only;
58 read-only;
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H A Dmvme7100.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2016 Elettra-Sincrotrone Trieste S.C.p.A.
10 /include/ "mpc8641si-pre.dtsi"
37 phy-handle = <&phy0>;
38 phy-connection-type = "rgmii-id";
42 phy0: ethernet-phy@1 {
45 phy1: ethernet-phy@2 {
48 phy2: ethernet-phy@3 {
51 phy3: ethernet-phy@4 {
57 phy-handle = <&phy1>;
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/freebsd/sys/contrib/device-tree/src/arm64/xilinx/
H A Dzynqmp-zc1751-xm018-dc4.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm018-dc4
5 * (C) Copyright 2015 - 2021, Xilinx, Inc.
10 /dts-v1/;
13 #include "zynqmp-clk-ccf.dtsi"
16 model = "ZynqMP zc1751-xm01
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/freebsd/sys/dev/cxgb/common/
H A Dcxgb_common.h2 SPDX-License-Identifier: BSD-2-Clause
4 Copyright (c) 2007-2009, Chelsio Inc.
64 enum { /* adapter interrupt-maintained statistics */
141 #define WR_FLITS (TX_DESC_FLITS + 1 - SGE_NUM_GENBITS)
157 unsigned char phy_base_addr; /* MDIO PHY base address */
159 unsigned char gpio_intr[MAX_PHYINTRS]; /* GPIO PHY IRQ pins */
339 /* MC5 modes, these must be non-0 */
398 unsigned int chan_map; /* bitmap of in-use Tx channels */
456 return p->tcam_size; in t3_mc5_size()
470 return p->size; in t3_mc7_size()
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/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dfsl-ls1043a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
11 /dts-v1/;
12 #include "fsl-ls1043a.dtsi"
16 compatible = "fsl,ls1043a-rdb", "fsl,ls1043a";
26 stdout-path = "serial0:115200n8";
36 shunt-resistor = <1000>;
67 #address-cells = <2>;
68 #size-cells = <1>;
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/freebsd/sys/contrib/device-tree/src/arm/nxp/ls/
H A Dls1021a-tsn.dts1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright 2016-2018 NXP Semiconductors
6 /dts-v1/;
10 model = "NXP LS1021A-TSN Board";
11 compatible = "fsl,ls1021a-tsn", "fsl,ls1021a";
13 sys_mclk: clock-mclk {
14 compatible = "fixed-clock";
15 #clock-cells = <0>;
16 clock-frequency = <24576000>;
19 reg_vdda_codec: regulator-3V3 {
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/freebsd/sys/contrib/dev/iwlwifi/fw/api/
H A Dbinding.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2012-2014, 2020, 2022, 2024 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
17 * struct iwl_binding_cmd_v1 - configuring bindings
19 * @id_and_color: ID and color of the relevant Binding,
22 * @macs: array of MAC id and colors which belong to the binding,
24 * @phy: PHY id and color which belongs to the binding,
33 __le32 phy; member
37 * struct iwl_binding_cmd - configuring bindings
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