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/linux/Documentation/devicetree/bindings/phy/
H A Dti,phy-am654-serdes.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/ti,phy-am654-serdes.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI AM654 SERDES
10 This binding describes the TI AM654 SERDES. AM654 SERDES can be configured
14 - Kishon Vijay Abraham I <kishon@ti.com>
19 - ti,phy-am654-serdes
24 reg-names:
26 - const: serdes
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/linux/drivers/phy/ti/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for TI platforms
6 tristate "TI DA8xx USB PHY Driver"
11 Enable this to support the USB PHY on DA8xx SoCs.
13 This driver controls both the USB 1.1 PHY and the USB 2.0 PHY.
16 tristate "TI dm816x USB PHY driver"
25 tristate "TI AM654 SERDES support"
33 This option enables support for TI AM654 SerDes PHY used for
37 tristate "TI J721E WIZ (SERDES Wrapper) support"
47 SoC. WIZ is a serdes wrapper used to configure some of the input
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H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_PHY_DA8XX_USB) += phy-da8xx-usb.o
3 obj-$(CONFIG_PHY_DM816X_USB) += phy-dm816x-usb.o
4 obj-$(CONFIG_OMAP_CONTROL_PHY) += phy-omap-control.o
5 obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o
6 obj-$(CONFIG_TI_PIPE3) += phy-ti-pipe3.o
7 obj-$(CONFIG_PHY_TUSB1210) += phy-tusb1210.o
8 obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o
9 obj-$(CONFIG_PHY_AM654_SERDES) += phy-am654-serdes.o
10 obj-$(CONFIG_PHY_TI_GMII_SEL) += phy-gmii-sel.o
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H A Dphy-am654-serdes.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe SERDES driver for AM654x SoC
5 * Copyright (C) 2018 - 2019 Texas Instruments Incorporated - http://www.ti.com/
9 #include <dt-bindings/phy/phy.h>
12 #include <linux/clk-provider.h>
18 #include <linux/phy/phy.h>
142 /* Mid-speed initial calibration control */
145 /* High-speed initial calibration control */
148 /* Mid-speed recalibration control */
151 /* High-speed recalibration control */
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/linux/arch/arm64/boot/dts/ti/
H A Dk3-am65-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy-am654-serdes.h>
11 compatible = "mmio-sram";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 atf-sram@0 {
21 sysfw-sram@f0000 {
25 l3cache-sram@100000 {
30 gic500: interrupt-controller@1800000 {
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H A Dk3-am654-pcie-usb3.dtso1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * DT overlay for SERDES personality card: 1lane PCIe + USB3.0 DRD on AM654 EVM
5 * Copyright (C) 2018-2024 Texas Instruments Incorporated - http://www.ti.com/
8 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/phy/phy-am654-serdes.h>
14 #include "k3-pinctrl.h"
21 num-lanes = <1>;
23 phy-names = "pcie-phy0";
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H A Dk3-am654-pcie-usb2.dtso1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * DT overlay for SERDES personality card: 2lane PCIe + USB2.0 Host on AM654 EVM
5 * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/
8 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/phy/phy-am654-serdes.h>
13 #include "k3-pinctrl.h"
16 assigned-clocks = <&k3_clks 153 4>,
19 assigned-clock-parents = <&k3_clks 153 8>,
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H A Dk3-j721e-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy.h>
8 #include <dt-bindings/phy/phy-ti.h>
9 #include <dt-bindings/mux/mux.h>
11 #include "k3-serdes.h"
14 cmn_refclk: clock-cmnrefclk {
15 #clock-cells = <0>;
16 compatible = "fixed-clock";
17 clock-frequency = <0>;
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H A Dk3-j784s4-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/mux/mux.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/phy/phy-ti.h>
12 #include "k3-serdes.h"
15 serdes_refclk: clock-serdes {
16 #clock-cells = <0>;
17 compatible = "fixed-clock";
25 compatible = "mmio-sram";
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H A Dk3-j721s2-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/phy/phy-cadence.h>
9 #include <dt-bindings/phy/phy-ti.h>
12 serdes_refclk: clock-cmnrefclk {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <0>;
21 compatible = "mmio-sram";
23 #address-cells = <1>;
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H A Dk3-j7200-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
9 serdes_refclk: serdes-refclk {
10 #clock-cells = <0>;
11 compatible = "fixed-clock";
17 compatible = "mmio-sram";
19 #address-cells = <1>;
20 #size-cells = <1>;
23 atf-sram@0 {
28 scm_conf: scm-conf@100000 {
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H A Dk3-am64-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/phy/phy-cadence.h>
9 #include <dt-bindings/phy/phy-ti.h>
12 serdes_refclk: clock-cmnrefclk {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <0>;
21 compatible = "mmio-sram";
23 #address-cells = <1>;
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/linux/Documentation/devicetree/bindings/net/
H A Dti,k3-am654-cpsw-nuss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ti,k3-am654-cpsw-nuss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Siddharth Vadapalli <s-vadapalli@ti.com>
11 - Roger Quadros <rogerq@kernel.org>
22 Complex (UDMA-P) controller.
52 "#address-cells": true
53 "#size-cells": true
57 - ti,am642-cpsw-nuss
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/linux/Documentation/devicetree/bindings/soc/ti/
H A Dti,j721e-system-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/soc/ti/ti,j721e-system-controller.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 represent as any specific type of device. The typical use-case is
15 for some other node's driver, or platform-specific code, to acquire
22 - Kishon Vijay Abraham I <kishon@kernel.org>
23 - Roger Quadros <rogerq@kernel.org>
28 - enum:
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/linux/drivers/net/ethernet/ti/
H A Dam65-cpsw-nuss.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
25 #include <linux/phy/phy.h>
32 #include <linux/dma/ti-cppi5.h>
33 #include <linux/dma/k3-udma-glue.h>
39 #include "am65-cpsw-nuss.h"
40 #include "am65-cpsw-switchdev.h"
41 #include "k3-cppi-desc-pool.h"
42 #include "am65-cpts.h"
125 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
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/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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