| /linux/Documentation/driver-api/memory-devices/ |
| H A D | ti-gpmc.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 GPMC (General Purpose Memory Controller)
7 GPMC is an unified memory controller dedicated to interfacing external
8 memory devices like
14 * Pseudo-SRAM devices
23 GPMC has certain timings that has to be programmed for proper
24 functioning of the peripheral, while peripheral has another set of
25 timings. To have peripheral work with gpmc, peripheral timings has to
26 be translated to the form gpmc can understand. The way it has to be
27 translated depends on the connected peripheral. Also there is a
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| /linux/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | mc-peripheral-props.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/mc-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for a Memory Controller bus.
10 Many Memory Controllers need to add properties to peripheral devices.
13 to be defined in the peripheral node because they are per-peripheral
14 and there can be multiple peripherals attached to a controller. All
20 - Marek Vasut <marex@denx.de>
26 bank-width:
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| /linux/Documentation/devicetree/bindings/iommu/ |
| H A D | samsung,sysmmu.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos IOMMU H/W, System MMU (System Memory Management Unit)
10 - Marek Szyprowski <m.szyprowski@samsung.com>
14 physical memory chunks visible as a contiguous region to DMA-capable peripheral
15 devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth.
17 System MMU is an IOMMU and supports identical translation table format to
20 another capabilities like L2 TLB or block-fetch buffers to minimize translation
23 System MMUs are in many to one relation with peripheral devices, i.e. single
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| /linux/Documentation/devicetree/bindings/dma/ |
| H A D | atmel-xdma.txt | |
| H A D | atmel-dma.txt | 1 * Atmel Direct Memory Access Controller (DMA)
4 - compatible: Should be "atmel,<chip>-dma".
5 - reg: Should contain DMA registers location and length.
6 - interrupts: Should contain DMA interrupt.
7 - #dma-cells: Must be <2>, used to represent the number of integer cells in
13 compatible = "atmel,at91sam9g45-dma";
16 #dma-cells = <2>;
19 DMA clients connected to the Atmel DMA controller must use the format
20 described in the dma.txt file, using a three-cell specifier for each channel:
24 1. A phandle pointing to the DMA controller.
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| /linux/drivers/gpu/drm/ |
| H A D | drm_mipi_dsi.c | 4 * Copyright (C) 2012-2013, Samsung Electronics, Co., Ltd.
7 * Permission is hereby granted, free of charge, to any person obtaining a
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
44 * These functions contain some common logic and helpers to deal with MIPI DSI
60 if (!strcmp(dsi->name, drv->name)) in mipi_dsi_device_match()
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| /linux/Documentation/driver-api/ |
| H A D | sm501.rst | 15 ----
27 peripheral set as platform devices for the specific drivers.
29 The core re-uses the platform device system as the platform device
30 system provides enough features to support the drivers without the
31 need to create a new bus-type and the associated code to go with it.
35 ---------
37 Each peripheral has a view of the device which is implicitly narrowed to
38 the specific set of resources that peripheral requires in order to
41 The centralised memory allocation allows the driver to ensure that the
42 maximum possible resource allocation can be made to the video subsystem
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| H A D | spi.rst | 1 Serial Peripheral Interface (SPI)
4 SPI is the "Serial Peripheral Interface", widely used with embedded
7 often in the range of 1-20 MHz), a "Master Out, Slave In" (MOSI) data
11 words of various sizes on the way to and from system memory. An
12 additional chipselect line is usually active-low (nCS); four signals are
13 normally used for each peripheral, plus sometimes an interrupt.
15 The SPI bus facilities listed here provide a generalized interface to
16 declare SPI busses and devices, manage them according to the standard
18 only "master" side interfaces are supported, where Linux talks to SPI
19 peripherals and does not implement such a peripheral itself. (Interfaces
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| /linux/arch/mips/include/asm/txx9/ |
| H A D | dmac.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
14 * struct txx9dmac_platform_data - Controller configuration parameters
24 * struct txx9dmac_chan_platform_data - Channel configuration parameters
32 * struct txx9dmac_slave - Controller-specific information about a slave
34 * memory-to-peripheral transfers
36 * peripheral-to-memory transfers
37 * @reg_width: peripheral register width
|
| /linux/Documentation/devicetree/bindings/dma/stm32/ |
| H A D | st,stm32-dma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/stm32/st,stm32-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The STM32 DMA is a general-purpose direct memory access controller capable of
11 supporting 8 independent DMA channels. Each channel can have up to 8 requests.
12 DMA clients connected to the STM32 DMA controller must use the format
13 described in the dma.txt file, using a four-cell specifier for each
14 channel: a phandle to the DMA controller plus the following four integer cells:
19 -bit 9: Peripheral Increment Address
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| /linux/Documentation/devicetree/bindings/spi/ |
| H A D | spi-peripheral-props.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for a SPI bus.
10 Many SPI controllers need to add properties to peripheral devices. They could
11 be common properties like spi-max-frequency, spi-cpha, etc. or they could be
13 need to be defined in the peripheral node because they are per-peripheral and
14 there can be multiple peripherals attached to a controller. All those
19 - Mark Brown <broonie@kernel.org>
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| /linux/Documentation/devicetree/ |
| H A D | overlay-notes.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 This document describes the implementation of the in-kernel
9 companion document to Documentation/devicetree/dynamic-resolution-notes.rst[1]
12 -----------------
14 A Devicetree's overlay purpose is to modify the kernel's live tree, and
23 ---- foo.dts ---------------------------------------------------------------
25 /dts-v1/;
39 ---- foo.dts ---------------------------------------------------------------
44 ---- bar.dts - overlay target location by label ----------------------------
45 /dts-v1/;
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| /linux/arch/powerpc/platforms/chrp/ |
| H A D | gg2.h | 2 * include/asm-ppc/gg2.h -- VLSI VAS96011/12 `Golden Gate 2' register definitions
11 * This file is subject to the terms and conditions of the GNU General Public
20 * Memory Map (CHRP mode)
23 #define GG2_PCI_MEM_BASE 0xc0000000 /* Peripheral memory space */
24 #define GG2_ISA_MEM_BASE 0xf7000000 /* Peripheral memory alias */
25 #define GG2_ISA_IO_BASE 0xf8000000 /* Peripheral I/O space */
|
| /linux/drivers/firmware/qcom/ |
| H A D | qcom_scm.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/arm-smccc.h>
13 #include <linux/dma-mapping.h>
29 #include <linux/reset-controller.h>
47 /* control access to the interconnect path */
70 * struct qcom_scm_qseecom_resp - QSEECOM SCM call response.
153 ret = clk_prepare_enable(__scm->core_clk); in qcom_scm_clk_enable()
157 ret = clk_prepare_enable(__scm->iface_clk); in qcom_scm_clk_enable()
161 ret = clk_prepare_enable(__scm->bus_clk); in qcom_scm_clk_enable()
168 clk_disable_unprepare(__scm->iface_clk); in qcom_scm_clk_enable()
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| /linux/Documentation/devicetree/bindings/dma/ti/ |
| H A D | k3-bcdma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
5 ---
6 $id: http://devicetree.org/schemas/dma/ti/k3-bcdm
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| /linux/drivers/usb/gadget/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
4 # (a) a peripheral controller, and
7 # NOTE: Gadget support ** DOES NOT ** depend on host-side CONFIG_USB !!
9 # - Host systems (like PCs) need CONFIG_USB (with "A" jacks).
10 # - Peripherals (like PDAs) need CONFIG_USB_GADGET (with "B" jacks).
11 # - Some systems have both kinds of controllers.
13 # With help from a special transceiver and a "Mini-AB" jack, systems with
14 # both kinds of controller can also support "USB On-the-Go" (CONFIG_USB_OTG).
23 PC) controlling up to 127 peripheral devices.
24 The USB hardware is asymmetric, which makes it easier to set up:
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| /linux/Documentation/devicetree/bindings/remoteproc/ |
| H A D | qcom,sc8180x-pas.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,sc8180x-pas.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SC8180X Peripheral Authentication Service
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
13 Qualcomm SC8180X SoC Peripheral Authentication Service loads and boots
19 - qcom,sc8180x-adsp-pas
20 - qcom,sc8180x-cdsp-pas
21 - qcom,sc8180x-mpss-pas
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| H A D | qcom,sdx55-pas.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,sdx55-pas.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SDX55 Peripheral Authentication Service
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
13 Qualcomm SDX55 SoC Peripheral Authentication Service loads and boots firmware
19 - qcom,sdx55-mpss-pas
26 - description: XO clock
28 clock-names:
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| H A D | qcom,qcs404-pas.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,qcs404-pas.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QCS404 Peripheral Authentication Service
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
13 Qualcomm QCS404 SoC Peripheral Authentication Service loads and boots
19 - qcom,qcs404-adsp-pas
20 - qcom,qcs404-cdsp-pas
21 - qcom,qcs404-wcss-pas
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| /linux/Documentation/userspace-api/media/ |
| H A D | glossary.rst | 1 .. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
9 The goal of this section is to standardize the terms used within the media
17 A :term:`Device Driver` that implements the main logic to talk with
23 An API designed to receive and transmit data via an HDMI
40 A character device node in the file system used to control and
46 An API designed to control a subset of the :term:`Media Hardware`
58 **Field-programmable Gate Array**
60 An :term:`IC` circuit designed to be configured by a customer or
63 See https://en.wikipedia.org/wiki/Field-programmable_gate_array.
70 Hardware Peripheral
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| /linux/Documentation/mhi/ |
| H A D | mhi.rst | 1 .. SPDX-License-Identifier: GPL-2.0
13 by the host processors to control and communicate with modem devices over high
14 speed peripheral buses or shared memory. Even though MHI can be easily adapted
15 to any peripheral buses, it is primarily used with PCIe based devices. MHI
26 ----
28 MMIO (Memory mapped IO) consists of a set of registers in the device hardware,
29 which are mapped to the host memory space by the peripheral buses like PCIe.
32 MHI control registers: Access to MHI configurations registers
35 for downloading the firmware to the device before MHI initialization.
37 Channel Doorbell array: Channel Doorbell (DB) registers used by the host to
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| /linux/drivers/bus/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
29 Say y here to enable support for the ARM Logic Module bus
37 Driver for the Broadcom Set Top Box System-on-a-chip internal bus
42 bool "Baikal-T1 APB-bus driver"
46 Baikal-T1 AXI-APB bridge is used to access the SoC subsystem CSRs.
47 IO requests are routed to this bus by means of the DW AMBA 3 AXI
50 reported to the APB terminator (APB Errors Handler Block). This
51 driver provides the interrupt handler to detect the erroneous
53 errors counter. The counter and the APB-bus operations timeout can be
57 bool "Baikal-T1 AXI-bus driver"
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| /linux/drivers/usb/gadget/udc/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
4 # (a) a peripheral controller, and
7 # NOTE: Gadget support ** DOES NOT ** depend on host-side CONFIG_USB !!
9 # - Host systems (like PCs) need CONFIG_USB (with "A" jacks).
10 # - Peripherals (like PDAs) need CONFIG_USB_GADGET (with "B" jacks).
11 # - Some systems have both kinds of controllers.
13 # With help from a special transceiver and a "Mini-AB" jack, systems with
14 # both kinds of controller can also support "USB On-the-Go" (CONFIG_USB_OTG).
18 # USB Peripheral Controller Support
22 # - integrated/SOC controllers first
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| /linux/Documentation/devicetree/bindings/reset/ |
| H A D | nxp,lpc1850-rgu.txt | 4 Please also refer to reset.txt in this directory for common reset
8 - compatible: Should be "nxp,lpc1850-rgu"
9 - reg: register base and length
10 - clocks: phandle and clock specifier to RGU clocks
11 - clock-names: should contain "delay" and "reg"
12 - #reset-cells: should be 1
14 See table below for valid peripheral reset numbers. Numbers not
18 Reset Peripheral
20 12 ARM Cortex-M0 subsystem core (LPC43xx only)
27 21 External memory controller (EMC)
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| /linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | marvell,icu.txt | 2 --------------------------------
5 responsible for collecting all wired-interrupt sources in the CP and
6 communicating them to the GIC in the AP, the unit translates interrupt
7 requests on input wires to MSG memory mapped transactions to the GIC.
8 These messages will access a different GIC memory area depending on
13 - compatible: Should be "marvell,cp110-icu"
15 - reg: Should contain ICU registers location and length.
22 - compatible: Should be one of:
23 * "marvell,cp110-icu-nsr"
24 * "marvell,cp110-icu-sr"
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