1*33d71d26SKumar Gala /* 2*33d71d26SKumar Gala * include/asm-ppc/gg2.h -- VLSI VAS96011/12 `Golden Gate 2' register definitions 3*33d71d26SKumar Gala * 4*33d71d26SKumar Gala * Copyright (C) 1997 Geert Uytterhoeven 5*33d71d26SKumar Gala * 6*33d71d26SKumar Gala * This file is based on the following documentation: 7*33d71d26SKumar Gala * 8*33d71d26SKumar Gala * The VAS96011/12 Chipset, Data Book, Edition 1.0 9*33d71d26SKumar Gala * VLSI Technology, Inc. 10*33d71d26SKumar Gala * 11*33d71d26SKumar Gala * This file is subject to the terms and conditions of the GNU General Public 12*33d71d26SKumar Gala * License. See the file COPYING in the main directory of this archive 13*33d71d26SKumar Gala * for more details. 14*33d71d26SKumar Gala */ 15*33d71d26SKumar Gala 16*33d71d26SKumar Gala #ifndef _ASMPPC_GG2_H 17*33d71d26SKumar Gala #define _ASMPPC_GG2_H 18*33d71d26SKumar Gala 19*33d71d26SKumar Gala /* 20*33d71d26SKumar Gala * Memory Map (CHRP mode) 21*33d71d26SKumar Gala */ 22*33d71d26SKumar Gala 23*33d71d26SKumar Gala #define GG2_PCI_MEM_BASE 0xc0000000 /* Peripheral memory space */ 24*33d71d26SKumar Gala #define GG2_ISA_MEM_BASE 0xf7000000 /* Peripheral memory alias */ 25*33d71d26SKumar Gala #define GG2_ISA_IO_BASE 0xf8000000 /* Peripheral I/O space */ 26*33d71d26SKumar Gala #define GG2_PCI_CONFIG_BASE 0xfec00000 /* PCI configuration space */ 27*33d71d26SKumar Gala #define GG2_INT_ACK_SPECIAL 0xfec80000 /* Interrupt acknowledge and */ 28*33d71d26SKumar Gala /* special PCI cycles */ 29*33d71d26SKumar Gala #define GG2_ROM_BASE0 0xff000000 /* ROM bank 0 */ 30*33d71d26SKumar Gala #define GG2_ROM_BASE1 0xff800000 /* ROM bank 1 */ 31*33d71d26SKumar Gala 32*33d71d26SKumar Gala 33*33d71d26SKumar Gala /* 34*33d71d26SKumar Gala * GG2 specific PCI Registers 35*33d71d26SKumar Gala */ 36*33d71d26SKumar Gala 37*33d71d26SKumar Gala extern void __iomem *gg2_pci_config_base; /* kernel virtual address */ 38*33d71d26SKumar Gala 39*33d71d26SKumar Gala #define GG2_PCI_BUSNO 0x40 /* Bus number */ 40*33d71d26SKumar Gala #define GG2_PCI_SUBBUSNO 0x41 /* Subordinate bus number */ 41*33d71d26SKumar Gala #define GG2_PCI_DISCCTR 0x42 /* Disconnect counter */ 42*33d71d26SKumar Gala #define GG2_PCI_PPC_CTRL 0x50 /* PowerPC interface control register */ 43*33d71d26SKumar Gala #define GG2_PCI_ADDR_MAP 0x5c /* Address map */ 44*33d71d26SKumar Gala #define GG2_PCI_PCI_CTRL 0x60 /* PCI interface control register */ 45*33d71d26SKumar Gala #define GG2_PCI_ROM_CTRL 0x70 /* ROM interface control register */ 46*33d71d26SKumar Gala #define GG2_PCI_ROM_TIME 0x74 /* ROM timing */ 47*33d71d26SKumar Gala #define GG2_PCI_CC_CTRL 0x80 /* Cache controller control register */ 48*33d71d26SKumar Gala #define GG2_PCI_DRAM_BANK0 0x90 /* Control register for DRAM bank #0 */ 49*33d71d26SKumar Gala #define GG2_PCI_DRAM_BANK1 0x94 /* Control register for DRAM bank #1 */ 50*33d71d26SKumar Gala #define GG2_PCI_DRAM_BANK2 0x98 /* Control register for DRAM bank #2 */ 51*33d71d26SKumar Gala #define GG2_PCI_DRAM_BANK3 0x9c /* Control register for DRAM bank #3 */ 52*33d71d26SKumar Gala #define GG2_PCI_DRAM_BANK4 0xa0 /* Control register for DRAM bank #4 */ 53*33d71d26SKumar Gala #define GG2_PCI_DRAM_BANK5 0xa4 /* Control register for DRAM bank #5 */ 54*33d71d26SKumar Gala #define GG2_PCI_DRAM_TIME0 0xb0 /* Timing parameters set #0 */ 55*33d71d26SKumar Gala #define GG2_PCI_DRAM_TIME1 0xb4 /* Timing parameters set #1 */ 56*33d71d26SKumar Gala #define GG2_PCI_DRAM_CTRL 0xc0 /* DRAM control */ 57*33d71d26SKumar Gala #define GG2_PCI_ERR_CTRL 0xd0 /* Error control register */ 58*33d71d26SKumar Gala #define GG2_PCI_ERR_STATUS 0xd4 /* Error status register */ 59*33d71d26SKumar Gala /* Cleared when read */ 60*33d71d26SKumar Gala 61*33d71d26SKumar Gala #endif /* _ASMPPC_GG2_H */ 62