| /freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ |
| H A D | mc-peripheral-props.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/mc-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for a Memory Controller bus.
10 Many Memory Controllers need to add properties to peripheral devices.
13 to be defined in the peripheral node because they are per-peripheral
20 - Marek Vasut <marex@denx.de>
26 bank-width:
32 - reg
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|
| /freebsd/sys/contrib/device-tree/Bindings/serial/ |
| H A D | fsl-imx-uart.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/fsl-im
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| /freebsd/sys/contrib/device-tree/Bindings/spmi/ |
| H A D | qcom,spmi-pmic-arb.txt | 4 controller with wrapping arbitration logic to allow for multiple on-chip
13 See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt for
17 - compatible : should be "qcom,spmi-pmic-arb".
18 - reg-names : must contain:
19 "core" - core registers
20 "intr" - interrupt controller registers
21 "cnfg" - configuration registers
23 "chnls" - tx-channel per virtual slave registers.
24 "obsrvr" - rx-channel (called observer) per virtual slave registers.
26 - reg : address + size pairs describing the PMIC arb register sets; order must
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| H A D | qcom,spmi-pmic-arb.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/spmi/qcom,spmi-pmic-arb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stephen Boyd <sboyd@kernel.org>
14 controller with wrapping arbitration logic to allow for multiple on-chip
21 - $ref: spmi.yaml
25 const: qcom,spmi-pmic-arb
29 - items: # V1
30 - description: core registers
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| H A D | qcom,x1e80100-spmi-pmic-arb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spmi/qcom,x1e80100-spmi-pmic-arb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stephen Boyd <sboyd@kernel.org>
14 controller with wrapping arbitration logic to allow for multiple on-chip
22 const: qcom,x1e80100-spmi-pmic-arb
26 - description: core registers
27 - description: tx-channel per virtual slave registers
28 - description: rx-channel (called observer) per virtual slave registers
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| /freebsd/sys/contrib/device-tree/Bindings/spi/ |
| H A D | spi-peripheral-props.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for a SPI bus.
10 Many SPI controllers need to add properties to peripheral devices. They could
11 be common properties like spi-max-frequency, spi-cpha, etc. or they could be
13 need to be defined in the peripheral node because they are per-peripheral and
19 - Mark Brown <broonie@kernel.org>
27 - minimum: 0
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|
| H A D | qcom,spi-qup.txt | 1 Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI)
4 and an input FIFO) for serial peripheral interface (SPI) mini-core.
10 - compatible: Should contain:
11 "qcom,spi-qup-v1.1.1" for 8660, 8960 and 8064.
12 "qcom,spi-qup-v2.1.1" for 8974 and later
13 "qcom,spi-qup-v2.2.1" for 8974 v2 and later.
15 - reg: Should contain base register location and length
16 - interrupts: Interrupt number used by this controller
18 - clocks: Should contain the core clock and the AHB clock.
19 - clock-names: Should be "core" for the core clock and "iface" for the
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|
| /freebsd/sys/contrib/device-tree/Bindings/pinctrl/ |
| H A D | atmel,at91rm9200-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/atmel,at91rm9200-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manikandan Muralidharan <manikandan.m@microchip.com>
22 - items:
23 - enum:
24 - atmel,at91rm9200-pinctrl
25 - atmel,at91sam9x5-pinctrl
26 - atmel,sama5d3-pinctrl
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|
| H A D | atmel,at91-pinctrl.txt | 10 Please refer to pinctrl-bindings.txt in this directory for details of the
18 such as pull-up, multi drive, etc.
21 - compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl"
22 or "atmel,sama5d3-pinctrl" or "microchip,sam9x60-pinctrl"
23 or "microchip,sam9x7-pinctrl", "microchip,sam9x60-pinctrl"
24 - atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
29 Each column will represent the possible peripheral of the pinctrl
33 Peripheral: 2 ( A and B)
42 For each peripheral/bank we will describe in a u32 if a pin can be
45 Let's take the pioA on peripheral B
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|
| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | ste-u300-syscon-clock.txt | 1 Clock bindings for ST-Ericsson U300 System Controller Clocks
6 - compatible: must be "stericsson,u300-syscon-clk"
7 - #clock-cells: must be <0>
8 - clock-type: specifies the type of clock:
12 - clock-id: specifies the clock in the type range
15 - clocks: parent clock(s)
17 The available clocks per type are as follows:
20 -------------------
21 0 0 Slow peripheral bridge clock
28 1 0 Fast peripheral bridge clock
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|
| H A D | imx7ulp-clock.txt | 4 Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
19 ---------------------------------------------------------------------
23 processor, system, peripheral bus and external memory interface clocks,
24 source selection for peripheral clocks and control of power saving
29 - compatible: Should be "fsl,imx7ulp-scg1".
30 - reg : Should contain registers location and length.
31 - #clock-cells: Should be <1>.
32 - clocks: Should contain the fixed input clocks.
33 - clock-names: Should contain the following clock names:
36 Peripheral Clock Control (PCC) modules:
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|
| /freebsd/sys/contrib/device-tree/Bindings/phy/ |
| H A D | nvidia,tegra186-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
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|
| H A D | nvidia,tegra194-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra194-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
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|
| H A D | nvidia,tegra124-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
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|
| H A D | nvidia,tegra210-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xus
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| /freebsd/sys/contrib/device-tree/Bindings/sound/ |
| H A D | apple,mca.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 MCA is an I2S transceiver peripheral found on M1 and other Apple chips. It is
15 - Martin Povišer <povik+lin@cutebit.org>
18 - $ref: dai-common.yaml#
23 - enum:
24 - apple,t6000-mca
25 - apple,t8103-mca
26 - apple,t8112-mca
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|
| H A D | mchp-i2s-mcc.txt | 1 * Microchip I2S Multi-Channel Controller
4 - compatible: Should be "microchip,sam9x60-i2smcc".
5 - reg: Should be the physical base address of the controller and the
7 - interrupts: Should contain the interrupt for the controller.
8 - dmas: Should be one per channel name listed in the dma-names property,
9 as described in atmel-dma.txt and dma.txt files.
10 - dma-names: Identifier string for each DMA request line in the dmas property.
12 - clocks: Must contain an entry for each entry in clock-names.
13 Please refer to clock-bindings.txt.
14 - clock-names: Should be one of each entry matching the clocks phandles list:
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| H A D | atmel-i2s.txt | 4 - compatible: Should be "atmel,sama5d2-i2s".
5 - reg: Should be the physical base address of the controller and the
7 - interrupts: Should contain the interrupt for the controller.
8 - dmas: Should be one per channel name listed in the dma-names property,
9 as described in atmel-dma.txt and dma.txt files.
10 - dma-names: Two dmas have to be defined, "tx" and "rx".
12 if this mode is used, one "rx-tx" name must be used.
13 - clocks: Must contain an entry for each entry in clock-names.
14 Please refer to clock-bindings.txt.
15 - clock-names: Should be one of each entry matching the clocks phandles list:
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|
| /freebsd/share/man/man4/ |
| H A D | ppbus.4 | 42 system provides a uniform, modular and architecture-independent
48 .Bl -bullet -offset indent
50 architecture-independent macros or functions to access parallel ports
57 with kernel-in drivers.
61 and non-standard software:
63 .Bl -column "Driver" -compact
66 .It Sy pps Ta "Pulse per second Timing Interface"
67 .It Sy lpbb Ta "Philips official parallel port I2C bit-banging interface"
73 .Bl -column "Driver" -compact
86 parallel port bus, then initialize it and upper peripheral device drivers.
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| H A D | apic.4 | 36 .Bd -ragged -offset indent
42 .Bl -ohang
54 There is typically one I/O APIC for each peripheral bus in the system.
57 In addition, they are able to accept and generate inter-processor interrupts
61 they receive from peripheral buses to one or more local APICs.
63 Each local APIC includes one 32-bit programmable timer.
65 Event timer provided by the driver supports both one-shot and periodic modes.
66 Because of local APIC nature it is per-CPU.
|
| /freebsd/sys/contrib/device-tree/Bindings/dma/stm32/ |
| H A D | st,stm32-dma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/stm32/st,stm32-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The STM32 DMA is a general-purpose direct memory access controller capable of
13 described in the dma.txt file, using a four-cell specifier for each
19 -bit 9: Peripheral Increment Address
22 -bit 10: Memory Increment Address
25 -bit 15: Peripheral Increment Offset Size
26 0x0: offset size is linked to the peripheral bus width
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| /freebsd/sys/contrib/device-tree/Bindings/dma/ |
| H A D | st,stm32-dma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/st,stm32-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The STM32 DMA is a general-purpose direct memory access controller capable of
13 described in the dma.txt file, using a four-cell specifier for each
19 -bit 9: Peripheral Increment Address
22 -bit 10: Memory Increment Address
25 -bit 15: Peripheral Increment Offset Size
26 0x0: offset size is linked to the peripheral bus width
[all …]
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| H A D | img-mdc-dma.txt | 1 * IMG Multi-threaded DMA Controller (MDC)
4 - compatible: Must be "img,pistachio-mdc-dma".
5 - reg: Must contain the base address and length of the MDC registers.
6 - interrupts: Must contain all the per-channel DMA interrupts.
7 - clocks: Must contain an entry for each entry in clock-names.
8 See ../clock/clock-bindings.txt for details.
9 - clock-names: Must include the following entries:
10 - sys: MDC system interface clock.
11 - img,cr-periph: Must contain a phandle to the peripheral control syscon
13 - img,max-burst-multiplier: Must be the maximum supported burst size multiplier.
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|
| /freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/ |
| H A D | brcm,bcm2836-l1-intc.txt | 1 BCM2836 per-CPU interrupt controller
3 The BCM2836 has a per-cpu interrupt controller for the timer, PMU
5 peripheral (GPU) events, which chain to the BCM2835-style interrupt
10 - compatible: Should be "brcm,bcm2836-l1-intc"
11 - reg: Specifies base physical address and size of the
13 - interrupt-controller: Identifies the node as an interrupt controller
14 - #interrupt-cells: Specifies the number of cells needed to encode an
32 compatible = "brcm,bcm2836-l1-intc";
34 interrupt-controller;
35 #interrupt-cells = <2>;
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| H A D | brcm,bcm2836-l1-intc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm2836-l1-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: BCM2836 per-CPU interrupt controller
10 - Stefan Wahren <wahrenst@gmx.net>
11 - Raspberry Pi Kernel Maintenance <kernel-list@raspberrypi.com>
14 The BCM2836 has a per-cpu interrupt controller for the timer, PMU
16 peripheral (GPU) events, which chain to the BCM2835-style interrupt
20 - $ref: /schemas/interrupt-controller.yaml#
[all …]
|