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/linux/Documentation/admin-guide/perf/
H A Dhisi-pcie-pmu.rst2 HiSilicon PCIe Performance Monitoring Unit (PMU)
5 On Hip09, HiSilicon PCIe Performance Monitoring Unit (PMU) could monitor
6 bandwidth, latency, bus utilization and buffer occupancy data of PCIe.
8 Each PCIe Core has a PMU to monitor multi Root Ports of this PCIe Core and
9 all Endpoints downstream these Root Ports.
12 HiSilicon PCIe PMU driver
15 The PCIe PMU driver registers a perf PMU with the name of its sicl-id and PCIe
30 The "bus" sysfs file allows users to get the bus number of Root Ports
31 monitored by PMU. Furthermore users can get the Root Ports range in
40 ------------------------------------------
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/linux/Documentation/devicetree/bindings/pci/
H A Dnvidia,tegra20-pcie.txt1 NVIDIA Tegra PCIe controller
4 - compatible: Must be:
5 - "nvidia,tegra20-pcie": for Tegra20
6 - "nvidia,tegra30-pcie": for Tegra30
7 - "nvidia,tegra124-pcie": for Tegra124 and Tegra132
8 - "nvidia,tegra210-pcie": for Tegra210
9 - "nvidia,tegra186-pcie": for Tegra186
10 - power-domains: To ungate power partition by BPMP powergate driver. Must
11 contain BPMP phandle and PCIe power partition ID. This is required only
13 - device_type: Must be "pci"
[all …]
H A Dapple,pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/apple,pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Apple PCIe host controller
10 - Mark Kettenis <kettenis@openbsd.org>
13 The Apple PCIe host controller is a PCIe host controller with
14 multiple root ports present in Apple ARM SoC platforms, including
16 The controller incorporates Synopsys DesigWare PCIe logic to
17 implements its root ports. But the ATU found on most DesignWare
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H A Dsnps,dw-pcie.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare PCIe interface
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
14 Synopsys DesignWare PCIe host controller
16 # Please create a separate DT-schema for your DWC PCIe Root Port controller
17 # and make sure it's assigned with the vendor-specific compatible string.
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H A Dmediatek,mt7621-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/mediatek,mt7621-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek MT7621 PCIe controller
10 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
13 MediaTek MT7621 PCIe subsys supports a single Root Complex (RC)
14 with 3 Root Ports. Each Root Port supports a Gen1 1-lane Link
16 MT7621 PCIe HOST Topology
18 .-------.
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H A Dbaikal,bt1-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/baikal,bt1-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Baikal-T1 PCIe Root Port Controller
10 - Serge Semin <fancer.lancer@gmail.com>
13 Embedded into Baikal-T1 SoC Root Complex controller with a single port
14 activated. It's based on the DWC RC PCIe v4.60a IP-core, which is configured
15 to have just a single Root Port function and is capable of establishing the
18 performed by software. There four in- and four outbound iATU regions
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H A Dmicrochip,pcie-host.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/microchip,pcie-host.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip PCIe Root Port Bridge Controller
10 - Daire McNamara <daire.mcnamara@microchip.com>
13 - $ref: plda,xpressrich3-axi-common.yaml#
14 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
18 const: microchip,pcie-host-1.0 # PolarFire
23 reg-names:
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H A Dnvidia,tegra194-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra194 (and later) PCIe controller (Synopsys DesignWare Core based)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Vidya Sagar <vidyas@nvidia.com>
15 This PCIe controller is based on the Synopsys DesignWare PCIe IP and thus
16 inherits all the common properties defined in snps,dw-pcie.yaml. Some of
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/linux/tools/perf/Documentation/
H A Dperf-iostat.txt1 perf-iostat(1)
5 ----
6 perf-iostat - Show I/O performance metrics
9 --------
12 'perf iostat' <ports> \-- <command> [<options>]
15 -----------
16 Mode is intended to provide four I/O performance metrics per each PCIe root port:
18 - Inbound Read - I/O devices below root port read from the host memory, in MB
20 - Inbound Write - I/O devices below root port write to the host memory, in MB
22 - Outbound Read - CPU reads from I/O devices below root port, in MB
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/linux/drivers/pci/controller/
H A Dpci-mvebu.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe driver for Marvell Armada 370 and Armada XP SoCs
5 * Author: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
27 #include "../pci-bridge-emul.h"
30 * PCIe unit register offsets.
40 #define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
83 /* Structure representing all PCIe interfaces */
99 /* Structure representing one PCIe interface */
103 u32 port; member
116 struct mvebu_pcie *pcie; member
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H A Dpcie-altera.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright Altera Corporation (C) 2013-2015. All rights reserved
6 * Description: Altera PCIe host controller driver
45 #define S10_RP_CFG_ADDR(pcie, reg) \ argument
46 (((pcie)->hip_base) + (reg) + (1 << 20))
47 #define S10_RP_SECONDARY(pcie) \ argument
48 readb(S10_RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
59 #define TLP_CFG_DW0(pcie, cfg) \ argument
62 #define TLP_CFG_DW1(pcie, tag, be) \ argument
63 (((PCI_DEVID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be))
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H A Dpcie-xilinx.c1 // SPDX-License-Identifier: GPL-2.0+
3 * PCIe host controller driver for Xilinx AXI PCIe Bridge
5 * Copyright (c) 2012 - 2014 Xilinx, Inc.
7 * Based on the Tegra PCIe driver
15 #include <linux/irqchip/irq-msi-lib.h>
25 #include <linux/pci-ecam.h>
45 #define XILINX_PCIE_INTR_STR_ERR BIT(2)
66 /* Root Port Error FIFO Read Register definitions */
71 /* Root Port Interrupt FIFO Read Register 1 definitions */
82 /* Root Port Interrupt FIFO Read Register 2 definitions */
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/linux/arch/powerpc/boot/dts/
H A Dturris1x.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright 2013 - 2022 CZ.NIC z.s.p.o. (http://www.nic.cz/)
8 * and available at: https://docs.turris.cz/hw/turris-1x/turris-1x/
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/leds/common.h>
14 /include/ "fsl/p2020si-pre.dtsi"
41 gpio-controller@18 {
45 #gpio-cells = <2>;
46 gpio-controller;
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H A Dcurrituck.dts7 * License version 2. This program is licensed "as is" without
11 /dts-v1/;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 dcr-parent = <&{/cpus/cpu@0}>;
27 #address-cells = <1>;
28 #size-cells = <0>;
34 clock-frequency = <1600000000>; // 1.6 GHz
35 timebase-frequency = <100000000>; // 100Mhz
36 i-cache-line-size = <32>;
[all …]
H A Dakebono.dts8 * License version 2. This program is licensed "as is" without
12 /dts-v1/;
17 #address-cells = <2>;
18 #size-cells = <2>;
21 dcr-parent = <&{/cpus/cpu@0}>;
28 #address-cells = <1>;
29 #size-cells = <0>;
35 clock-frequency = <1600000000>; // 1.6 GHz
36 timebase-frequency = <100000000>; // 100Mhz
37 i-cache-line-size = <32>;
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/linux/Documentation/driver-api/cxl/
H A Dtheory-of-operation.rst1 .. SPDX-License-Identifier: GPL-2.0
14 range across multiple devices underneath a host-bridge or interleaved
15 across host-bridges.
20 logical device, the CXL subsystem is tasked to take PCIe and ACPI objects and
28 Platform firmware enumerates a menu of interleave options at the "CXL root port"
29 (Linux term for the top of the CXL decode topology). From there, PCIe topology
31 Each PCIe Switch in the path between the root and an endpoint introduces a point
34 interleave cycles across multiple Root Ports. An intervening Switch between a
35 port and an endpoint may interleave cycles across multiple Downstream Switch
39 module generates an emulated CXL topology of 2 Host Bridges each with 2 Root
[all …]
/linux/drivers/pci/controller/cadence/
H A Dpcie-cadence.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 // Cadence PCIe controller driver.
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
12 #include <linux/pci-epf.h>
14 #include "pcie-cadence-lga-reg
293 struct cdns_pcie pcie; global() member
337 struct cdns_pcie pcie; global() member
355 cdns_pcie_writel(struct cdns_pcie * pcie,u32 reg,u32 value) cdns_pcie_writel() argument
360 cdns_pcie_readl(struct cdns_pcie * pcie,u32 reg) cdns_pcie_readl() argument
365 cdns_pcie_readw(struct cdns_pcie * pcie,u32 reg) cdns_pcie_readw() argument
370 cdns_pcie_readb(struct cdns_pcie * pcie,u32 reg) cdns_pcie_readb() argument
375 cdns_pcie_read_cfg_byte(struct cdns_pcie * pcie,int where,u8 * val) cdns_pcie_read_cfg_byte() argument
382 cdns_pcie_read_cfg_word(struct cdns_pcie * pcie,int where,u16 * val) cdns_pcie_read_cfg_word() argument
389 cdns_pcie_read_cfg_dword(struct cdns_pcie * pcie,int where,u32 * val) cdns_pcie_read_cfg_dword() argument
437 cdns_pcie_rp_writeb(struct cdns_pcie * pcie,u32 reg,u8 value) cdns_pcie_rp_writeb() argument
445 cdns_pcie_rp_writew(struct cdns_pcie * pcie,u32 reg,u16 value) cdns_pcie_rp_writew() argument
453 cdns_pcie_rp_readw(struct cdns_pcie * pcie,u32 reg) cdns_pcie_rp_readw() argument
461 cdns_pcie_ep_fn_writeb(struct cdns_pcie * pcie,u8 fn,u32 reg,u8 value) cdns_pcie_ep_fn_writeb() argument
469 cdns_pcie_ep_fn_writew(struct cdns_pcie * pcie,u8 fn,u32 reg,u16 value) cdns_pcie_ep_fn_writew() argument
477 cdns_pcie_ep_fn_writel(struct cdns_pcie * pcie,u8 fn,u32 reg,u32 value) cdns_pcie_ep_fn_writel() argument
483 cdns_pcie_ep_fn_readw(struct cdns_pcie * pcie,u8 fn,u32 reg) cdns_pcie_ep_fn_readw() argument
490 cdns_pcie_ep_fn_readl(struct cdns_pcie * pcie,u8 fn,u32 reg) cdns_pcie_ep_fn_readl() argument
495 cdns_pcie_start_link(struct cdns_pcie * pcie) cdns_pcie_start_link() argument
503 cdns_pcie_stop_link(struct cdns_pcie * pcie) cdns_pcie_stop_link() argument
509 cdns_pcie_link_up(struct cdns_pcie * pcie) cdns_pcie_link_up() argument
[all...]
/linux/drivers/pci/pcie/
H A Daspm.c1 // SPDX-License-Identifier: GPL-2.0
3 * Enable PCIe link L0s/L1 state and Clock Power Management
50 cap = &save_state->cap.data[0]; in pci_save_ltr_state()
66 cap = &save_state->cap.data[0]; in pci_restore_ltr_state()
74 pdev->l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); in pci_configure_aspm_l1ss()
77 2 * sizeof(u32)); in pci_configure_aspm_l1ss()
85 struct pci_dev *parent = pdev->bus->self; in pci_save_aspm_l1ss_state()
90 * If this is a Downstream Port, we never restore the L1SS state in pci_save_aspm_l1ss_state()
92 * Upstream Port below it. in pci_save_aspm_l1ss_state()
97 if (!pdev->l1ss || !parent->l1ss) in pci_save_aspm_l1ss_state()
[all …]
H A Dbwctrl.c1 // SPDX-License-Identifier: GPL-2.0+
3 * PCIe bandwidth controller
8 * Copyright (C) 2023-2024 Intel Corporation
10 * The PCIe bandwidth controller provides a way to alter PCIe Link Speeds
12 * notification capability is required for all Root Ports and Downstream
15 * This service port driver hooks into the Bandwidth Notification interrupt
30 #include <linux/pci-bwctrl.h>
39 * struct pcie_bwctrl_data - PCIe bandwidth controller
41 * @cdev: Thermal cooling device associated with the port
48 /* Prevent port removal during Link Speed changes. */
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H A Daer.c1 // SPDX-License-Identifier: GPL-2.0
3 * Implement the AER root port service driver. The driver registers an IRQ
4 * handler. When a root port triggers an AER interrupt, the IRQ handler
5 * collects Root Port status and schedules work.
11 * (C) Copyright 2009 Hewlett-Packard Development Company, L.P.
22 #include <linux/pci-acpi.h>
42 dev_printk(level, &(pdev)->dev, fmt, ##arg)
55 struct pci_dev *rpd; /* Root Port device */
66 * at its link partner (e.g. Root Port) because the errors will be
85 * Fields for Root Ports & Root Complex Event Collectors only; these
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H A Dportdrv.c1 // SPDX-License-Identifier: GPL-2.0
3 * Purpose: PCI Express Port Bus Driver
26 * The PCIe Capability Interrupt Message Number (PCIe r3.1, sec 7.8.2) must
27 * be one of the first 32 MSI-X entries. Per PCI r3.0, sec 6.8.3.1, MSI
32 #define get_descriptor_id(type, service) (((type - 4) << 8) | service)
41 * release_pcie_device - fre
293 struct pcie_device *pcie; pcie_device_init() local
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/linux/Documentation/devicetree/bindings/net/dsa/
H A Dmscc,ocelot.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vladimir Oltean <vladimir.oltean@nxp.com>
11 - Claudiu Manoil <claudiu.manoil@nxp.com>
12 - Alexandre Belloni <alexandre.belloni@bootlin.com>
13 - UNGLinuxDriver@microchip.com
16 There are multiple switches which are either part of the Ocelot-1 family, or
19 SPI or PCIe. The present DSA binding shall be used when the host controlling
20 them performs packet I/O primarily through an Ethernet port of the switch
[all …]
/linux/arch/arm/mach-mv78xx0/
H A Dpcie.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mach-mv78xx0/pcie.c
5 * PCIe functions for Marvell MV78xx0 SoCs
14 #include <plat/pcie.h>
18 #define MV78XX0_MBUS_PCIE_MEM_TARGET(port, lane) ((port) ? 8 : 4) argument
19 #define MV78XX0_MBUS_PCIE_MEM_ATTR(port, lane) (0xf8 & ~(0x10 << (lane))) argument
20 #define MV78XX0_MBUS_PCIE_IO_TARGET(port, lane) ((port) ? 8 : 4) argument
21 #define MV78XX0_MBUS_PCIE_IO_ATTR(port, lane) (0xf0 & ~(0x10 << (lane))) argument
60 pcie_io_space.name = "PCIe I/O Space"; in mv78xx0_pcie_preinit()
63 MV78XX0_PCIE_IO_PHYS_BASE(0) + MV78XX0_PCIE_IO_SIZE * 8 - 1; in mv78xx0_pcie_preinit()
[all …]
/linux/include/linux/
H A Dpci-ide.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Common helpers for drivers (e.g. low-level PCI/TSM drivers) implementing the
5 * PCIe r7.0 section 6.33 Integrity & Data Encryption (IDE)
7 * Copyright(c) 2024-2025 Intel Corporation. All rights reserved.
18 * In addition to the resources in each partner port the
19 * platform / host-bridge additionally has a Stream ID pool that
20 * it shares across root ports. Let pci_ide_stream_alloc() use
21 * the alloc_stream_index() helper as endpoints and root ports.
27 * struct pci_ide_partner - Per port pair Selective IDE Stream settings
28 * @rid_start: Partner Port Requester ID range start
[all …]
/linux/drivers/pci/controller/plda/
H A Dpcie-microchip-host.c1 // SPDX-License-Identifier: GPL-2.0
3 * Microchip AXI PCIe Bridge host controller driver
5 * Copyright (c) 2018 - 2020 Microchip Corporation. All rights reserved.
21 #include <linux/pci-ecam.h>
26 #include "../pci-host-common.h"
27 #include "pcie-plda.h"
32 /* PCIe Bridge Phy and Controller Phy offsets */
36 /* PCIe Controller Phy Regs */
58 #define ECC_CONTROL_TX_RAM_INJ_ERROR_2 BIT(2)
79 #define PCIE_EVENT_INT_DLUP_EXIT_INT BIT(2)
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