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/linux/Documentation/admin-guide/perf/
H A Dhisi-pcie-pmu.rst2 HiSilicon PCIe Performance Monitoring Unit (PMU)
5 On Hip09, HiSilicon PCIe Performance Monitoring Unit (PMU) could monitor
6 bandwidth, latency, bus utilization and buffer occupancy data of PCIe.
8 Each PCIe Core has a PMU to monitor multi Root Ports of this PCIe Core and
9 all Endpoints downstream these Root Ports.
12 HiSilicon PCIe PMU driver
15 The PCIe PMU driver registers a perf PMU with the name of its sicl-id and PCIe
30 The "bus" sysfs file allows users to get the bus number of Root Ports
31 monitored by PMU. Furthermore users can get the Root Ports range in
40 ------------------------------------------
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/linux/tools/perf/Documentation/
H A Dperf-iostat.txt1 perf-iostat(1)
5 ----
6 perf-iostat - Show I/O performance metrics
9 --------
12 'perf iostat' <ports> \-- <command> [<options>]
15 -----------
16 Mode is intended to provide four I/O performance metrics per each PCIe root port:
18 - Inbound Read - I/O devices below root port read from the host memory, in MB
20 - Inbound Write - I/O devices below root port write to the host memory, in MB
22 - Outbound Read - CPU reads from I/O devices below root port, in MB
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/linux/Documentation/devicetree/bindings/pci/
H A Dnvidia,tegra20-pcie.txt1 NVIDIA Tegra PCIe controller
4 - compatible: Must be:
5 - "nvidia,tegra20-pcie": for Tegra20
6 - "nvidia,tegra30-pcie": for Tegra30
7 - "nvidia,tegra124-pcie": for Tegra124 and Tegra132
8 - "nvidia,tegra210-pcie": for Tegra210
9 - "nvidia,tegra186-pcie": for Tegra186
10 - power-domains: To ungate power partition by BPMP powergate driver. Must
11 contain BPMP phandle and PCIe power partition ID. This is required only
13 - device_type: Must be "pci"
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H A Dpci.txt3 PCI Bus Binding to: IEEE Std 1275-1994
4 https://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf
9 https://www.devicetree.org/open-firmware/practice/imap/imap0_9d.pdf
14 - linux,pci-domain:
19 may be assigned to root buses behind different host bridges. The domain
21 - max-link-speed:
25 unsupported link speed, etc. Must be '4' for gen4, '3' for gen3, '2'
27 - reset-gpios:
30 - supports-clkreq:
32 root port to downstream device and host bridge drivers can do programming
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H A Dmediatek,mt7621-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/mediatek,mt7621-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek MT7621 PCIe controller
10 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
13 MediaTek MT7621 PCIe subsys supports a single Root Complex (RC)
14 with 3 Root Ports. Each Root Port supports a Gen1 1-lane Link
16 MT7621 PCIe HOST Topology
18 .-------.
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H A Dbaikal,bt1-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/baikal,bt1-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Baikal-T1 PCIe Root Port Controller
10 - Serge Semin <fancer.lancer@gmail.com>
13 Embedded into Baikal-T1 SoC Root Complex controller with a single port
14 activated. It's based on the DWC RC PCIe v4.60a IP-core, which is configured
15 to have just a single Root Port function and is capable of establishing the
18 performed by software. There four in- and four outbound iATU regions
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H A Dmediatek-pcie.txt1 MediaTek Gen2 PCIe controller
4 - compatible: Should contain one of the following strings:
5 "mediatek,mt2701-pcie"
6 "mediatek,mt2712-pcie"
7 "mediatek,mt7622-pcie"
8 "mediatek,mt7623-pcie"
9 "mediatek,mt7629-pcie"
10 "airoha,en7523-pcie"
11 - device_type: Must be "pci"
12 - reg: Base addresses and lengths of the root ports.
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H A Dsnps,dw-pcie-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DWC PCIe RP/EP controller
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
14 Generic Synopsys DesignWare PCIe Root Port and Endpoint controller
22 DWC PCIe CSR space is normally accessed over the dedicated Data Bus
23 Interface - DBI. In accordance with the reference manual the register
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H A Dnvidia,tegra194-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra194 (and later) PCIe controller (Synopsys DesignWare Core based)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Vidya Sagar <vidyas@nvidia.com>
15 This PCIe controller is based on the Synopsys DesignWare PCIe IP and thus
16 inherits all the common properties defined in snps,dw-pcie.yaml. Some of
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H A Dnvidia,tegra194-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra194 (and later) PCIe Endpoint controller (Synopsys DesignWare Core based)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Vidya Sagar <vidyas@nvidia.com>
15 This PCIe controller is based on the Synopsys DesignWare PCIe IP and thus
16 inherits all the common properties defined in snps,dw-pcie-ep.yaml. Some
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/linux/arch/powerpc/boot/dts/
H A Dturris1x.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright 2013 - 2022 CZ.NIC z.s.p.o. (http://www.nic.cz/)
8 * and available at: https://docs.turris.cz/hw/turris-1x/turris-1x/
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/leds/common.h>
14 /include/ "fsl/p2020si-pre.dtsi"
41 gpio-controller@18 {
45 #gpio-cells = <2>;
46 gpio-controller;
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H A Dcurrituck.dts7 * License version 2. This program is licensed "as is" without
11 /dts-v1/;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 dcr-parent = <&{/cpus/cpu@0}>;
27 #address-cells = <1>;
28 #size-cells = <0>;
34 clock-frequency = <1600000000>; // 1.6 GHz
35 timebase-frequency = <100000000>; // 100Mhz
36 i-cache-line-size = <32>;
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H A Dakebono.dts8 * License version 2. This program is licensed "as is" without
12 /dts-v1/;
17 #address-cells = <2>;
18 #size-cells = <2>;
21 dcr-parent = <&{/cpus/cpu@0}>;
28 #address-cells = <1>;
29 #size-cells = <0>;
35 clock-frequency = <1600000000>; // 1.6 GHz
36 timebase-frequency = <100000000>; // 100Mhz
37 i-cache-line-size = <32>;
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H A Dredwood.dts7 * License version 2. This program is licensed "as is" without
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
26 #address-cells = <1>;
27 #size-cells = <0>;
33 clock-frequency = <0>; /* Filled in by U-Boot */
34 timebase-frequency = <0>; /* Filled in by U-Boot */
35 i-cache-line-size = <32>;
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H A Dkatmai.dts11 * License version 2. This program is licensed "as is" without
15 /dts-v1/;
18 #address-cells = <2>;
19 #size-cells = <2>;
22 dcr-parent = <&{/cpus/cpu@0}>;
32 #address-cells = <1>;
33 #size-cells = <0>;
39 clock-frequency = <0>; /* Filled in by zImage */
40 timebase-frequency = <0>; /* Filled in by zImage */
41 i-cache-line-size = <32>;
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/linux/Documentation/driver-api/cxl/
H A Dmemory-devices.rst1 .. SPDX-License-Identifier: GPL-2.0
14 range across multiple devices underneath a host-bridge or interleaved
15 across host-bridges.
20 logical device, the CXL subsystem is tasked to take PCIe and ACPI objects and
28 Platform firmware enumerates a menu of interleave options at the "CXL root port"
29 (Linux term for the top of the CXL decode topology). From there, PCIe topology
31 Each PCIe Switch in the path between the root and an endpoint introduces a point
34 interleave cycles across multiple Root Ports. An intervening Switch between a
35 port and an endpoint may interleave cycles across multiple Downstream Switch
39 module generates an emulated CXL topology of 2 Host Bridges each with 2 Root
[all …]
/linux/drivers/pci/controller/
H A Dpcie-xilinx.c1 // SPDX-License-Identifier: GPL-2.0+
3 * PCIe host controller driver for Xilinx AXI PCIe Bridge
5 * Copyright (c) 2012 - 2014 Xilinx, Inc.
7 * Based on the Tegra PCIe driver
24 #include <linux/pci-ecam.h>
44 #define XILINX_PCIE_INTR_STR_ERR BIT(2)
65 /* Root Port Error FIFO Read Register definitions */
70 /* Root Port Interrupt FIFO Read Register 1 definitions */
81 /* Root Port Interrupt FIFO Read Register 2 definitions */
84 /* Root Port Status/control Register definitions */
[all …]
/linux/drivers/pci/pcie/
H A Daspm.c1 // SPDX-License-Identifier: GPL-2.0
3 * Enable PCIe link L0s/L1 state and Clock Power Management
49 cap = &save_state->cap.data[0]; in pci_save_ltr_state()
65 cap = &save_state->cap.data[0]; in pci_restore_ltr_state()
73 pdev->l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); in pci_configure_aspm_l1ss()
76 2 * sizeof(u32)); in pci_configure_aspm_l1ss()
84 struct pci_dev *parent = pdev->bus->self; in pci_save_aspm_l1ss_state()
89 * If this is a Downstream Port, we never restore the L1SS state in pci_save_aspm_l1ss_state()
91 * Upstream Port below it. in pci_save_aspm_l1ss_state()
96 if (!pdev->l1ss || !parent->l1ss) in pci_save_aspm_l1ss_state()
[all …]
/linux/Documentation/devicetree/bindings/net/dsa/
H A Dmscc,ocelot.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vladimir Oltean <vladimir.oltean@nxp.com>
11 - Claudiu Manoil <claudiu.manoil@nxp.com>
12 - Alexandre Belloni <alexandre.belloni@bootlin.com>
13 - UNGLinuxDriver@microchip.com
16 There are multiple switches which are either part of the Ocelot-1 family, or
19 SPI or PCIe. The present DSA binding shall be used when the host controlling
20 them performs packet I/O primarily through an Ethernet port of the switch
[all …]
/linux/arch/arm/mach-mv78xx0/
H A Dpcie.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mach-mv78xx0/pcie.c
5 * PCIe functions for Marvell MV78xx0 SoCs
14 #include <plat/pcie.h>
18 #define MV78XX0_MBUS_PCIE_MEM_TARGET(port, lane) ((port) ? 8 : 4) argument
19 #define MV78XX0_MBUS_PCIE_MEM_ATTR(port, lane) (0xf8 & ~(0x10 << (lane))) argument
20 #define MV78XX0_MBUS_PCIE_IO_TARGET(port, lane) ((port) ? 8 : 4) argument
21 #define MV78XX0_MBUS_PCIE_IO_ATTR(port, lane) (0xf0 & ~(0x10 << (lane))) argument
60 pcie_io_space.name = "PCIe I/O Space"; in mv78xx0_pcie_preinit()
63 MV78XX0_PCIE_IO_PHYS_BASE(0) + MV78XX0_PCIE_IO_SIZE * 8 - 1; in mv78xx0_pcie_preinit()
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/linux/Documentation/ABI/testing/
H A Dsysfs-devices-mapping5 Each IIO stack (PCIe root port) has its own IIO PMON block, so
6 each dieX file (where X is die number) holds "Segment:Root Bus"
7 for PCIe root port, which can be monitored by that IIO PMON
9 For example, on 4-die Xeon platform with up to 6 IIO stacks per
14 -r--r--r-- /sys/devices/uncore_iio_0/die0
15 -r--r--r-- /sys/devices/uncore_iio_0/die1
16 -r--r--r-- /sys/devices/uncore_iio_0/die2
17 -r--r--r-- /sys/devices/uncore_iio_0/die3
33 IIO PMU 0 on die 2 belongs to PCI RP on bus 0x80, domain 0x0000
44 For example, 4-die Sapphire Rapids platform has the following
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H A Dsysfs-bus-cxl4 Contact: linux-cxl@vger.kernel.org
6 (WO) If userspace manually unbinds a port the kernel schedules
14 Contact: linux-cxl@vger.kernel.org
17 Memory Device Output Payload in the CXL-2.0
24 Contact: linux-cxl@vger.kernel.org
34 Contact: linux-cxl@vger.kernel.org
42 Contact: linux-cxl@vger.kernel.org
46 Payload in the CXL-2.0 specification.
52 Contact: linux-cxl@vger.kernel.org
58 class-ids can be compared against a similar "qos_class"
[all …]
H A Dsysfs-bus-pci-devices-aer_stats1 PCIe Device AER statistics
2 --------------------------
7 counters may increment at its link partner (e.g. root port) because the
15 Contact: linux-pci@vger.kernel.org, rajatja@google.com
23 Receiver Error 2
28 Advisory Non-Fatal 0
31 TOTAL_ERR_COR 2
36 Contact: linux-pci@vger.kernel.org, rajatja@google.com
66 Contact: linux-pci@vger.kernel.org, rajatja@google.com
93 PCIe Rootport AER statistics
[all …]
/linux/drivers/pci/controller/dwc/
H A Dpcie-al.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Amazon's Annapurna Labs IP (used in chips
12 #include <linux/pci-ecam.h>
13 #include <linux/pci-acpi.h>
25 struct pci_config_window *cfg = bus->sysdata; in al_pcie_map_bus()
26 struct al_pcie_acpi *pcie = cfg->priv; in al_pcie_map_bus() local
27 void __iomem *dbi_base = pcie->dbi_base; in al_pcie_map_bus()
29 if (bus->number == cfg->busr.start) { in al_pcie_map_bus()
31 * The DW PCIe core doesn't filter out transactions to other in al_pcie_map_bus()
32 * devices/functions on the root bus num, so we do this here. in al_pcie_map_bus()
[all …]
/linux/drivers/pci/controller/cadence/
H A Dpcie-cadence-host.c1 // SPDX-License-Identifier: GPL-2.0
3 // Cadence PCIe host controller driver.
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
13 #include "pcie-cadence.h"
33 struct cdns_pcie *pcie = &rc->pcie; in cdns_pci_map_bus() local
34 unsigned int busn = bus->number; in cdns_pci_map_bus()
39 * Only the root port (devfn == 0) is connected to this bus. in cdns_pci_map_bus()
46 return pcie->reg_base + (where & 0xfff); in cdns_pci_map_bus()
49 if (!(cdns_pcie_readl(pcie, CDNS_PCIE_LM_BASE) & 0x1)) in cdns_pci_map_bus()
51 /* Clear AXI link-down status */ in cdns_pci_map_bus()
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