1 // SPDX-License-Identifier: GPL-2.0-only
3  * arch/arm/mach-mv78xx0/pcie.c
5  * PCIe functions for Marvell MV78xx0 SoCs
14 #include <plat/pcie.h>
18 #define MV78XX0_MBUS_PCIE_MEM_TARGET(port, lane) ((port) ? 8 : 4)  argument
19 #define MV78XX0_MBUS_PCIE_MEM_ATTR(port, lane)   (0xf8 & ~(0x10 << (lane)))  argument
20 #define MV78XX0_MBUS_PCIE_IO_TARGET(port, lane)  ((port) ? 8 : 4)  argument
21 #define MV78XX0_MBUS_PCIE_IO_ATTR(port, lane)    (0xf0 & ~(0x10 << (lane)))  argument
60 	pcie_io_space.name = "PCIe I/O Space";  in mv78xx0_pcie_preinit()
63 		MV78XX0_PCIE_IO_PHYS_BASE(0) + MV78XX0_PCIE_IO_SIZE * 8 - 1;  in mv78xx0_pcie_preinit()
66 		panic("can't allocate PCIe I/O space");  in mv78xx0_pcie_preinit()
69 		panic("invalid number of PCIe ports");  in mv78xx0_pcie_preinit()
77 		snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),  in mv78xx0_pcie_preinit()
78 			"PCIe %d.%d MEM", pp->maj, pp->min);  in mv78xx0_pcie_preinit()
79 		pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;  in mv78xx0_pcie_preinit()
80 		pp->res.name = pp->mem_space_name;  in mv78xx0_pcie_preinit()
81 		pp->res.flags = IORESOURCE_MEM;  in mv78xx0_pcie_preinit()
82 		pp->res.start = start;  in mv78xx0_pcie_preinit()
83 		pp->res.end = start + size_each - 1;  in mv78xx0_pcie_preinit()
86 		if (request_resource(&iomem_resource, &pp->res))  in mv78xx0_pcie_preinit()
87 			panic("can't allocate PCIe MEM sub-space");  in mv78xx0_pcie_preinit()
89 		mvebu_mbus_add_window_by_id(MV78XX0_MBUS_PCIE_MEM_TARGET(pp->maj, pp->min),  in mv78xx0_pcie_preinit()
90 					    MV78XX0_MBUS_PCIE_MEM_ATTR(pp->maj, pp->min),  in mv78xx0_pcie_preinit()
91 					    pp->res.start, resource_size(&pp->res));  in mv78xx0_pcie_preinit()
92 		mvebu_mbus_add_window_remap_by_id(MV78XX0_MBUS_PCIE_IO_TARGET(pp->maj, pp->min),  in mv78xx0_pcie_preinit()
93 						  MV78XX0_MBUS_PCIE_IO_ATTR(pp->maj, pp->min),  in mv78xx0_pcie_preinit()
107 	sys->private_data = pp;  in mv78xx0_pcie_setup()
108 	pp->root_bus_nr = sys->busnr;  in mv78xx0_pcie_setup()
111 	 * Generic PCIe unit setup.  in mv78xx0_pcie_setup()
113 	orion_pcie_set_local_bus_nr(pp->base, sys->busnr);  in mv78xx0_pcie_setup()
114 	orion_pcie_setup(pp->base);  in mv78xx0_pcie_setup()
117 	realio.end = realio.start + SZ_64K - 1;  in mv78xx0_pcie_setup()
120 	pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset);  in mv78xx0_pcie_setup()
131 	if (bus == pp->root_bus_nr && dev > 1)  in pcie_valid_config()
140 	struct pci_sys_data *sys = bus->sysdata;  in pcie_rd_conf()
141 	struct pcie_port *pp = sys->private_data;  in pcie_rd_conf()
145 	if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {  in pcie_rd_conf()
150 	spin_lock_irqsave(&pp->conf_lock, flags);  in pcie_rd_conf()
151 	ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);  in pcie_rd_conf()
152 	spin_unlock_irqrestore(&pp->conf_lock, flags);  in pcie_rd_conf()
160 	struct pci_sys_data *sys = bus->sysdata;  in pcie_wr_conf()
161 	struct pcie_port *pp = sys->private_data;  in pcie_wr_conf()
165 	if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)  in pcie_wr_conf()
168 	spin_lock_irqsave(&pp->conf_lock, flags);  in pcie_wr_conf()
169 	ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);  in pcie_wr_conf()
170 	spin_unlock_irqrestore(&pp->conf_lock, flags);  in pcie_wr_conf()
181  * The root complex has a hardwired class of PCI_CLASS_MEMORY_OTHER, when it
182  * is operating as a root complex this needs to be switched to
188 	if (dev->bus->parent == NULL && dev->devfn == 0) {  in rc_pci_fixup()
191 		dev->class &= 0xff;  in rc_pci_fixup()
192 		dev->class |= PCI_CLASS_BRIDGE_HOST << 8;  in rc_pci_fixup()
194 			r->start = 0;  in rc_pci_fixup()
195 			r->end   = 0;  in rc_pci_fixup()
196 			r->flags = 0;  in rc_pci_fixup()
208 		return -EINVAL;  in mv78xx0_pcie_scan_bus()
211 	list_splice_init(&sys->resources, &bridge->windows);  in mv78xx0_pcie_scan_bus()
212 	bridge->dev.parent = NULL;  in mv78xx0_pcie_scan_bus()
213 	bridge->sysdata = sys;  in mv78xx0_pcie_scan_bus()
214 	bridge->busnr = sys->busnr;  in mv78xx0_pcie_scan_bus()
215 	bridge->ops = &pcie_ops;  in mv78xx0_pcie_scan_bus()
223 	struct pci_sys_data *sys = dev->bus->sysdata;  in mv78xx0_pcie_map_irq()
224 	struct pcie_port *pp = sys->private_data;  in mv78xx0_pcie_map_irq()
226 	return IRQ_MV78XX0_PCIE_00 + (pp->maj << 2) + pp->min;  in mv78xx0_pcie_map_irq()
239 	printk(KERN_INFO "MV78xx0 PCIe port %d.%d: ", maj, min);  in add_pcie_port()
246 		pp->maj = maj;  in add_pcie_port()
247 		pp->min = min;  in add_pcie_port()
248 		pp->root_bus_nr = -1;  in add_pcie_port()
249 		pp->base = base;  in add_pcie_port()
250 		spin_lock_init(&pp->conf_lock);  in add_pcie_port()
251 		memset(&pp->res, 0, sizeof(pp->res));  in add_pcie_port()
265 			add_pcie_port(0, 2, PCIE02_VIRT_BASE);  in mv78xx0_pcie_init()
274 			add_pcie_port(1, 2, PCIE12_VIRT_BASE);  in mv78xx0_pcie_init()